3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 DECLARE_GLOBAL_DATA_PTR
;
32 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
34 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
36 #define PROFF_SMC PROFF_SMC1
37 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
39 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
41 #define PROFF_SMC PROFF_SMC2
42 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
44 #endif /* CONFIG_8xx_CONS_SMCx */
46 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
48 #define PROFF_SCC PROFF_SCC1
49 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
51 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
53 #define PROFF_SCC PROFF_SCC2
54 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
56 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
58 #define PROFF_SCC PROFF_SCC3
59 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
61 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
63 #define PROFF_SCC PROFF_SCC4
64 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
66 #endif /* CONFIG_8xx_CONS_SCCx */
68 static void serial_setdivisor(volatile cpm8xx_t
*cp
)
70 int divisor
=(gd
->cpu_clk
+ 8*gd
->baudrate
)/16/gd
->baudrate
;
72 if(divisor
/16>0x1000) {
73 /* bad divisor, assume 50Mhz clock and 9600 baud */
74 divisor
=(50*1000*1000 + 8*9600)/16/9600;
77 #ifdef CONFIG_SYS_BRGCLK_PRESCALE
78 divisor
/= CONFIG_SYS_BRGCLK_PRESCALE
;
82 cp
->cp_brgc1
=((divisor
-1)<<1) | CPM_BRG_EN
;
84 cp
->cp_brgc1
=((divisor
/16-1)<<1) | CPM_BRG_EN
| CPM_BRG_DIV16
;
88 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
91 * Minimal serial functions needed to use one of the SMC ports
92 * as serial console interface.
95 static void smc_setbrg (void)
97 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
98 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
100 /* Set up the baud rate generator.
101 * See 8xx_io/commproc.c for details.
106 cp
->cp_simode
= 0x00000000;
108 serial_setdivisor(cp
);
111 static int smc_init (void)
113 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
115 volatile smc_uart_t
*up
;
116 volatile cbd_t
*tbdf
, *rbdf
;
117 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
118 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
119 volatile iop8xx_t
*ip
= (iop8xx_t
*)&(im
->im_ioport
);
123 /* initialize pointers to SMC */
125 sp
= (smc_t
*) &(cp
->cp_smc
[SMC_INDEX
]);
126 up
= (smc_uart_t
*) &cp
->cp_dparam
[PROFF_SMC
];
127 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
128 up
= (smc_uart_t
*) &cp
->cp_dpmem
[up
->smc_rpbase
];
130 /* Disable relocation */
134 /* Disable transmitter/receiver.
136 sp
->smc_smcmr
&= ~(SMCMR_REN
| SMCMR_TEN
);
140 im
->im_siu_conf
.sc_sdcr
= 1;
142 /* clear error conditions */
143 #ifdef CONFIG_SYS_SDSR
144 im
->im_sdma
.sdma_sdsr
= CONFIG_SYS_SDSR
;
146 im
->im_sdma
.sdma_sdsr
= 0x83;
149 /* clear SDMA interrupt mask */
150 #ifdef CONFIG_SYS_SDMR
151 im
->im_sdma
.sdma_sdmr
= CONFIG_SYS_SDMR
;
153 im
->im_sdma
.sdma_sdmr
= 0x00;
156 #if defined(CONFIG_8xx_CONS_SMC1)
157 /* Use Port B for SMC1 instead of other functions.
159 cp
->cp_pbpar
|= 0x000000c0;
160 cp
->cp_pbdir
&= ~0x000000c0;
161 cp
->cp_pbodr
&= ~0x000000c0;
162 #else /* CONFIG_8xx_CONS_SMC2 */
163 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
164 /* Use Port A for SMC2 instead of other functions.
166 ip
->iop_papar
|= 0x00c0;
167 ip
->iop_padir
&= ~0x00c0;
168 ip
->iop_paodr
&= ~0x00c0;
169 # else /* must be a 860 then */
170 /* Use Port B for SMC2 instead of other functions.
172 cp
->cp_pbpar
|= 0x00000c00;
173 cp
->cp_pbdir
&= ~0x00000c00;
174 cp
->cp_pbodr
&= ~0x00000c00;
178 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
180 #if defined(CONFIG_8xx_CONS_SMC1)
181 *((uint
*) BCSR1
) &= ~BCSR1_RS232EN_1
;
183 *((uint
*) BCSR1
) &= ~BCSR1_RS232EN_2
;
185 #endif /* CONFIG_FADS */
187 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
188 /* Enable Monitor Port Transceiver */
189 *((uchar
*) BCSR0
) |= BCSR0_ENMONXCVR
;
190 #endif /* CONFIG_RPXLITE */
192 /* Set the physical address of the host memory buffers in
193 * the buffer descriptors.
196 #ifdef CONFIG_SYS_ALLOC_DPRAM
197 dpaddr
= dpram_alloc_align (sizeof(cbd_t
)*2 + 2, 8) ;
199 dpaddr
= CPM_SERIAL_BASE
;
202 /* Allocate space for two buffer descriptors in the DP ram.
203 * For now, this address seems OK, but it may have to
204 * change with newer versions of the firmware.
205 * damm: allocating space after the two buffers for rx/tx data
208 rbdf
= (cbd_t
*)&cp
->cp_dpmem
[dpaddr
];
209 rbdf
->cbd_bufaddr
= (uint
) (rbdf
+2);
212 tbdf
->cbd_bufaddr
= ((uint
) (rbdf
+2)) + 1;
215 /* Set up the uart parameters in the parameter ram.
217 up
->smc_rbase
= dpaddr
;
218 up
->smc_tbase
= dpaddr
+sizeof(cbd_t
);
219 up
->smc_rfcr
= SMC_EB
;
220 up
->smc_tfcr
= SMC_EB
;
221 #if defined (CONFIG_SYS_SMC_UCODE_PATCH)
222 up
->smc_rbptr
= up
->smc_rbase
;
223 up
->smc_tbptr
= up
->smc_tbase
;
228 #if defined(CONFIG_MBX)
230 #endif /* CONFIG_MBX */
232 /* Set UART mode, 8 bit, no parity, one stop.
233 * Enable receive and transmit.
235 sp
->smc_smcmr
= smcr_mk_clen(9) | SMCMR_SM_UART
;
237 /* Mask all interrupts and remove anything pending.
242 #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
243 /* clock source is PLD */
245 /* set freq to 19200 Baud */
246 *((volatile uchar
*) CONFIG_SYS_SPC1920_PLD_BASE
+6) = 0x3;
247 /* configure clk4 as input */
248 im
->im_ioport
.iop_pdpar
|= 0x800;
249 im
->im_ioport
.iop_pddir
&= ~0x800;
251 cp
->cp_simode
= ((cp
->cp_simode
& ~0xf000) | 0x7000);
253 /* Set up the baud rate generator */
257 /* Make the first buffer the only buffer.
259 tbdf
->cbd_sc
|= BD_SC_WRAP
;
260 rbdf
->cbd_sc
|= BD_SC_EMPTY
| BD_SC_WRAP
;
262 /* Single character receive.
267 /* Initialize Tx/Rx parameters.
270 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
273 cp
->cp_cpcr
= mk_cr_cmd(CPM_CR_CH_SMC
, CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
275 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
278 /* Enable transmitter/receiver.
280 sp
->smc_smcmr
|= SMCMR_REN
| SMCMR_TEN
;
286 smc_putc(const char c
)
288 volatile cbd_t
*tbdf
;
290 volatile smc_uart_t
*up
;
291 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
292 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
294 #ifdef CONFIG_MODEM_SUPPORT
302 up
= (smc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SMC
];
303 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
304 up
= (smc_uart_t
*) &cpmp
->cp_dpmem
[up
->smc_rpbase
];
307 tbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->smc_tbase
];
309 /* Wait for last character to go.
312 buf
= (char *)tbdf
->cbd_bufaddr
;
315 tbdf
->cbd_datlen
= 1;
316 tbdf
->cbd_sc
|= BD_SC_READY
;
319 while (tbdf
->cbd_sc
& BD_SC_READY
) {
326 smc_puts (const char *s
)
336 volatile cbd_t
*rbdf
;
337 volatile unsigned char *buf
;
338 volatile smc_uart_t
*up
;
339 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
340 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
343 up
= (smc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SMC
];
344 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
345 up
= (smc_uart_t
*) &cpmp
->cp_dpmem
[up
->smc_rpbase
];
348 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->smc_rbase
];
350 /* Wait for character to show up.
352 buf
= (unsigned char *)rbdf
->cbd_bufaddr
;
354 while (rbdf
->cbd_sc
& BD_SC_EMPTY
)
358 rbdf
->cbd_sc
|= BD_SC_EMPTY
;
366 volatile cbd_t
*rbdf
;
367 volatile smc_uart_t
*up
;
368 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
369 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
371 up
= (smc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SMC
];
372 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
373 up
= (smc_uart_t
*) &cpmp
->cp_dpmem
[up
->smc_rpbase
];
376 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->smc_rbase
];
378 return(!(rbdf
->cbd_sc
& BD_SC_EMPTY
));
381 struct serial_device serial_smc_device
=
393 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
395 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
396 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
401 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
402 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
404 /* Set up the baud rate generator.
405 * See 8xx_io/commproc.c for details.
410 cp
->cp_sicr
&= ~(0x000000FF << (8 * SCC_INDEX
));
412 serial_setdivisor(cp
);
415 static int scc_init (void)
417 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
419 volatile scc_uart_t
*up
;
420 volatile cbd_t
*tbdf
, *rbdf
;
421 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
423 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
424 volatile iop8xx_t
*ip
= (iop8xx_t
*)&(im
->im_ioport
);
427 /* initialize pointers to SCC */
429 sp
= (scc_t
*) &(cp
->cp_scc
[SCC_INDEX
]);
430 up
= (scc_uart_t
*) &cp
->cp_dparam
[PROFF_SCC
];
432 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
433 { /* Disable Ethernet, enable Serial */
437 c
&= ~0x40; /* enable COM3 */
438 c
|= 0x80; /* disable Ethernet */
442 cp
->cp_pbpar
|= 0x2000;
443 cp
->cp_pbdat
|= 0x2000;
444 cp
->cp_pbdir
|= 0x2000;
446 #endif /* CONFIG_LWMON */
448 /* Disable transmitter/receiver.
450 sp
->scc_gsmrl
&= ~(SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
452 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
454 * The MPC850 has SCC3 on Port B
456 cp
->cp_pbpar
|= 0x06;
457 cp
->cp_pbdir
&= ~0x06;
458 cp
->cp_pbodr
&= ~0x06;
460 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
462 * Standard configuration for SCC's is on Part A
464 ip
->iop_papar
|= ((3 << (2 * SCC_INDEX
)));
465 ip
->iop_padir
&= ~((3 << (2 * SCC_INDEX
)));
466 ip
->iop_paodr
&= ~((3 << (2 * SCC_INDEX
)));
469 * The IP860 has SCC3 and SCC4 on Port D
471 ip
->iop_pdpar
|= ((3 << (2 * SCC_INDEX
)));
474 /* Allocate space for two buffer descriptors in the DP ram.
477 #ifdef CONFIG_SYS_ALLOC_DPRAM
478 dpaddr
= dpram_alloc_align (sizeof(cbd_t
)*2 + 2, 8) ;
480 dpaddr
= CPM_SERIAL2_BASE
;
485 im
->im_siu_conf
.sc_sdcr
= 0x0001;
487 /* Set the physical address of the host memory buffers in
488 * the buffer descriptors.
491 rbdf
= (cbd_t
*)&cp
->cp_dpmem
[dpaddr
];
492 rbdf
->cbd_bufaddr
= (uint
) (rbdf
+2);
495 tbdf
->cbd_bufaddr
= ((uint
) (rbdf
+2)) + 1;
498 /* Set up the baud rate generator.
502 /* Set up the uart parameters in the parameter ram.
504 up
->scc_genscc
.scc_rbase
= dpaddr
;
505 up
->scc_genscc
.scc_tbase
= dpaddr
+sizeof(cbd_t
);
507 /* Initialize Tx/Rx parameters.
509 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
511 cp
->cp_cpcr
= mk_cr_cmd(CPM_CR_CH_SCC
, CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
513 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
516 up
->scc_genscc
.scc_rfcr
= SCC_EB
| 0x05;
517 up
->scc_genscc
.scc_tfcr
= SCC_EB
| 0x05;
519 up
->scc_genscc
.scc_mrblr
= 1; /* Single character receive */
520 up
->scc_maxidl
= 0; /* disable max idle */
521 up
->scc_brkcr
= 1; /* send one break character on stop TX */
529 up
->scc_char1
= 0x8000;
530 up
->scc_char2
= 0x8000;
531 up
->scc_char3
= 0x8000;
532 up
->scc_char4
= 0x8000;
533 up
->scc_char5
= 0x8000;
534 up
->scc_char6
= 0x8000;
535 up
->scc_char7
= 0x8000;
536 up
->scc_char8
= 0x8000;
537 up
->scc_rccm
= 0xc0ff;
539 /* Set low latency / small fifo.
541 sp
->scc_gsmrh
= SCC_GSMRH_RFW
;
543 /* Set SCC(x) clock mode to 16x
544 * See 8xx_io/commproc.c for details.
549 /* Set UART mode, clock divider 16 on Tx and Rx
551 sp
->scc_gsmrl
&= ~0xF;
553 (SCC_GSMRL_MODE_UART
| SCC_GSMRL_TDCR_16
| SCC_GSMRL_RDCR_16
);
556 sp
->scc_psmr
|= SCU_PSMR_CL
;
558 /* Mask all interrupts and remove anything pending.
561 sp
->scc_scce
= 0xffff;
562 sp
->scc_dsr
= 0x7e7e;
563 sp
->scc_psmr
= 0x3000;
565 /* Make the first buffer the only buffer.
567 tbdf
->cbd_sc
|= BD_SC_WRAP
;
568 rbdf
->cbd_sc
|= BD_SC_EMPTY
| BD_SC_WRAP
;
570 /* Enable transmitter/receiver.
572 sp
->scc_gsmrl
|= (SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
578 scc_putc(const char c
)
580 volatile cbd_t
*tbdf
;
582 volatile scc_uart_t
*up
;
583 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
584 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
586 #ifdef CONFIG_MODEM_SUPPORT
594 up
= (scc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SCC
];
596 tbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->scc_genscc
.scc_tbase
];
598 /* Wait for last character to go.
601 buf
= (char *)tbdf
->cbd_bufaddr
;
604 tbdf
->cbd_datlen
= 1;
605 tbdf
->cbd_sc
|= BD_SC_READY
;
608 while (tbdf
->cbd_sc
& BD_SC_READY
) {
615 scc_puts (const char *s
)
625 volatile cbd_t
*rbdf
;
626 volatile unsigned char *buf
;
627 volatile scc_uart_t
*up
;
628 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
629 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
632 up
= (scc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SCC
];
634 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->scc_genscc
.scc_rbase
];
636 /* Wait for character to show up.
638 buf
= (unsigned char *)rbdf
->cbd_bufaddr
;
640 while (rbdf
->cbd_sc
& BD_SC_EMPTY
)
644 rbdf
->cbd_sc
|= BD_SC_EMPTY
;
652 volatile cbd_t
*rbdf
;
653 volatile scc_uart_t
*up
;
654 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
655 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
657 up
= (scc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SCC
];
659 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->scc_genscc
.scc_rbase
];
661 return(!(rbdf
->cbd_sc
& BD_SC_EMPTY
));
664 struct serial_device serial_scc_device
=
676 #endif /* CONFIG_8xx_CONS_SCCx */
678 #ifdef CONFIG_MODEM_SUPPORT
679 void disable_putc(void)
684 void enable_putc(void)
690 #if defined(CONFIG_CMD_KGDB)
693 kgdb_serial_init(void)
697 if (strcmp(default_serial_console()->ctlr
, "SMC") == 0)
699 #if defined(CONFIG_8xx_CONS_SMC1)
701 #elif defined(CONFIG_8xx_CONS_SMC2)
705 else if (strcmp(default_serial_console()->ctlr
, "SMC") == 0)
707 #if defined(CONFIG_8xx_CONS_SCC1)
709 #elif defined(CONFIG_8xx_CONS_SCC2)
711 #elif defined(CONFIG_8xx_CONS_SCC3)
713 #elif defined(CONFIG_8xx_CONS_SCC4)
720 serial_printf("[on %s%d] ", default_serial_console()->ctlr
, i
);
731 putDebugStr (const char *str
)
739 return serial_getc();
743 kgdb_interruptible (int yes
)
749 #endif /* CONFIG_8xx_CONS_NONE */