cpu/mpc8xx/speed.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc8xx.h>
  26 #include <asm/processor.h>
  27
  28 #define PITC_SHIFT 16
  29 #define PITR_SHIFT 16
  30 /* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
  31 #define SPEED_PIT_COUNTS 58
  32 #define SPEED_PITC       ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
  33 #define SPEED_PITC_INIT  ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)
  34
  35 #if !defined(CONFIG_8xx_GCLK_FREQ)
  36 /* Access functions for the Machine State Register */
  37 static __inline__ unsigned long get_msr(void)
  38 {
  39         unsigned long msr;
  40
  41         asm volatile("mfmsr %0" : "=r" (msr) :);
  42         return msr;
  43 }
  44
  45 static __inline__ void set_msr(unsigned long msr)
  46 {
  47         asm volatile("mtmsr %0" : : "r" (msr));
  48 }
  49 #endif
  50
  51 /* ------------------------------------------------------------------------- */
  52
  53 /*
  54  * Measure CPU clock speed (core clock GCLK1, GCLK2),
  55  * also determine bus clock speed (checking bus divider factor)
  56  *
  57  * (Approx. GCLK frequency in Hz)
  58  *
  59  * Initializes timer 2 and PIT, but disables them before return.
  60  * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4]
  61  *
  62  * When measuring the CPU clock against the PIT, we count cpu clocks
  63  * for 58/8192 seconds with a prescale divide by 177 for the cpu clock.
  64  * These strange values for the timing interval and prescaling are used
  65  * because the formula for the CPU clock is:
  66  *
  67  *   CPU clock = count * (177 * (8192 / 58))
  68  *
  69  *             = count * 24999.7241
  70  *
  71  *   which is very close to
  72  *
  73  *             = count * 25000
  74  *
  75  * Since the count gives the CPU clock divided by 25000, we can get
  76  * the CPU clock rounded to the nearest 0.1 MHz by
  77  *
  78  *   CPU clock = ((count + 2) / 4) * 100000;
  79  *
  80  * The rounding is important since the measurement is sometimes going
  81  * to be high or low by 0.025 MHz, depending on exactly how the clocks
  82  * and counters interact. By rounding we get the exact answer for any
  83  * CPU clock that is an even multiple of 0.1 MHz.
  84  */
  85
  86 int get_clocks (void)
  87 {
  88         DECLARE_GLOBAL_DATA_PTR;
  89
  90         volatile immap_t *immr = (immap_t *) CFG_IMMR;
  91 #ifndef CONFIG_8xx_GCLK_FREQ
  92         volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
  93         ulong timer2_val;
  94         ulong msr_val;
  95
  96         /* Reset + Stop Timer 2, no cascading
  97          */
  98         timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2);
  99
 100         /* Keep stopped, halt in debug mode
 101          */
 102         timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2);
 103
 104         /* Timer 2 setup:
 105          * Output ref. interrupt disable, int. clock
 106          * Prescale by 177. Note that prescaler divides by value + 1
 107          * so we must subtract 1 here.
 108          */
 109         timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
 110
 111         timerp->cpmt_tcn2 = 0;          /* reset state      */
 112         timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2   */
 113
 114         /*
 115          * PIT setup:
 116          *
 117          * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
 118          * so the count value would be SPEED_PITC_COUNTS - 1.
 119          * But there would be an uncertainty in the start time of 1/4
 120          * count since when we enable the PIT the count is not
 121          * synchronized to the 32768 Hz oscillator. The trick here is
 122          * to start the count higher and wait until the PIT count
 123          * changes to the required value before starting timer 2.
 124          *
 125          * One count high should be enough, but occasionally the start
 126          * is off by 1 or 2 counts of 32768 Hz. With the start value
 127          * set two counts high it seems very reliable.
 128          */
 129
 130         immr->im_sitk.sitk_pitck = KAPWR_KEY;   /* PIT initialization */
 131         immr->im_sit.sit_pitc = SPEED_PITC_INIT;
 132
 133         immr->im_sitk.sitk_piscrk = KAPWR_KEY;
 134         immr->im_sit.sit_piscr = CFG_PISCR;
 135
 136         /*
 137          * Start measurement - disable interrupts, just in case
 138          */
 139         msr_val = get_msr ();
 140         set_msr (msr_val & ~MSR_EE);
 141
 142         immr->im_sit.sit_piscr |= PISCR_PTE;
 143
 144         /* spin until get exact count when we want to start */
 145         while (immr->im_sit.sit_pitr > SPEED_PITC);
 146
 147         timerp->cpmt_tgcr &= ~TGCR_STP2;        /* Start Timer 2    */
 148         while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
 149         timerp->cpmt_tgcr |= TGCR_STP2;         /* Stop  Timer 2    */
 150
 151         /* re-enable external interrupts if they were on */
 152         set_msr (msr_val);
 153
 154         /* Disable timer and PIT
 155          */
 156         timer2_val = timerp->cpmt_tcn2;         /* save before reset timer */
 157
 158         timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
 159         immr->im_sit.sit_piscr &= ~PISCR_PTE;
 160
 161         gd->cpu_clk = ((timer2_val + 2) / 4) * 100000L; /* convert to Hz    */
 162
 163 #else /* CONFIG_8xx_GCLK_FREQ */
 164
 165         /*
 166          * If for some reason measuring the gclk frequency won't
 167          * work, we return the hardwired value.
 168          * (For example, the cogent CMA286-60 CPU module has no
 169          * separate oscillator for PITRTCLK)
 170          */
 171
 172         gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
 173
 174 #endif /* CONFIG_8xx_GCLK_FREQ */
 175
 176         if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) {
 177                 /* No Bus Divider active */
 178                 gd->bus_clk = gd->cpu_clk;
 179         } else {
 180                 /* The MPC8xx has only one BDF: half clock speed */
 181                 gd->bus_clk = gd->cpu_clk / 2;
 182         }
 183
 184         return (0);
 185 }
 186
 187 /* ------------------------------------------------------------------------- */