cpu/mpc8xxx/ddr/options.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_ddr_sdram.h>
  11
  12 #include "ddr.h"
  13
  14 /* Board-specific functions defined in each board's ddr.c */
  15 extern void fsl_ddr_board_options(memctl_options_t *popts,
  16                 dimm_params_t *pdimm,
  17                 unsigned int ctrl_num);
  18
  19 unsigned int populate_memctl_options(int all_DIMMs_registered,
  20                         memctl_options_t *popts,
  21                         dimm_params_t *pdimm,
  22                         unsigned int ctrl_num)
  23 {
  24         unsigned int i;
  25         const char *p;
  26
  27         /* Chip select options. */
  28
  29         /* Pick chip-select local options. */
  30         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  31                 /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
  32
  33                 /* only for single CS? */
  34                 popts->cs_local_opts[i].odt_rd_cfg = 0;
  35
  36                 popts->cs_local_opts[i].odt_wr_cfg = 1;
  37                 popts->cs_local_opts[i].auto_precharge = 0;
  38         }
  39
  40         /* Pick interleaving mode. */
  41
  42         /*
  43          * 0 = no interleaving
  44          * 1 = interleaving between 2 controllers
  45          */
  46         popts->memctl_interleaving = 0;
  47
  48         /*
  49          * 0 = cacheline
  50          * 1 = page
  51          * 2 = (logical) bank
  52          * 3 = superbank (only if CS interleaving is enabled)
  53          */
  54         popts->memctl_interleaving_mode = 0;
  55
  56         /*
  57          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
  58          * 1: page:      bit to the left of the column bits selects the memctl
  59          * 2: bank:      bit to the left of the bank bits selects the memctl
  60          * 3: superbank: bit to the left of the chip select selects the memctl
  61          *
  62          * NOTE: ba_intlv (rank interleaving) is independent of memory
  63          * controller interleaving; it is only within a memory controller.
  64          * Must use superbank interleaving if rank interleaving is used and
  65          * memory controller interleaving is enabled.
  66          */
  67
  68         /*
  69          * 0 = no
  70          * 0x40 = CS0,CS1
  71          * 0x20 = CS2,CS3
  72          * 0x60 = CS0,CS1 + CS2,CS3
  73          * 0x04 = CS0,CS1,CS2,CS3
  74          */
  75         popts->ba_intlv_ctl = 0;
  76
  77         /* Memory Organization Parameters */
  78         popts->registered_dimm_en = all_DIMMs_registered;
  79
  80         /* Operational Mode Paramters */
  81
  82         /* Pick ECC modes */
  83 #ifdef CONFIG_DDR_ECC
  84         popts->ECC_mode = 1;              /* 0 = disabled, 1 = enabled */
  85 #else
  86         popts->ECC_mode = 0;              /* 0 = disabled, 1 = enabled */
  87 #endif
  88         popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
  89
  90         /*
  91          * Choose DQS config
  92          * 0 for DDR1
  93          * 1 for DDR2
  94          */
  95 #if defined(CONFIG_FSL_DDR1)
  96         popts->DQS_config = 0;
  97 #elif defined(CONFIG_FSL_DDR2)
  98         popts->DQS_config = 1;
  99 #else
 100 #error "Fix DQS for DDR3"
 101 #endif
 102
 103         /* Choose self-refresh during sleep. */
 104         popts->self_refresh_in_sleep = 1;
 105
 106         /* Choose dynamic power management mode. */
 107         popts->dynamic_power = 0;
 108
 109         /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
 110         popts->data_bus_width = 0;
 111
 112         /* Choose burst length. */
 113         popts->burst_length = 4;        /* has to be 4 for DDR2 */
 114
 115         /* Global Timing Parameters. */
 116         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
 117
 118         /* Pick a caslat override. */
 119         popts->cas_latency_override = 0;
 120         popts->cas_latency_override_value = 3;
 121         if (popts->cas_latency_override) {
 122                 debug("using caslat override value = %u\n",
 123                        popts->cas_latency_override_value);
 124         }
 125
 126         /* Decide whether to use the computed derated latency */
 127         popts->use_derated_caslat = 0;
 128
 129         /* Choose an additive latency. */
 130         popts->additive_latency_override = 0;
 131         popts->additive_latency_override_value = 3;
 132         if (popts->additive_latency_override) {
 133                 debug("using additive latency override value = %u\n",
 134                        popts->additive_latency_override_value);
 135         }
 136
 137         /*
 138          * 2T_EN setting
 139          *
 140          * Factors to consider for 2T_EN:
 141          *      - number of DIMMs installed
 142          *      - number of components, number of active ranks
 143          *      - how much time you want to spend playing around
 144          */
 145         popts->twoT_en = 1;
 146         popts->threeT_en = 0;
 147
 148         /*
 149          * BSTTOPRE precharge interval
 150          *
 151          * Set this to 0 for global auto precharge
 152          *
 153          * FIXME: Should this be configured in picoseconds?
 154          * Why it should be in ps:  better understanding of this
 155          * relative to actual DRAM timing parameters such as tRAS.
 156          * e.g. tRAS(min) = 40 ns
 157          */
 158         popts->bstopre = 0x100;
 159
 160         /* Minimum CKE pulse width -- tCKE(MIN) */
 161         popts->tCKE_clock_pulse_width_ps
 162                 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 163
 164         /*
 165          * Window for four activates -- tFAW
 166          *
 167          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 168          * FIXME: varies depending upon number of column addresses or data
 169          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 170          */
 171 #if defined(CONFIG_FSL_DDR1)
 172         popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
 173
 174 #elif defined(CONFIG_FSL_DDR2)
 175         /*
 176          * x4/x8;  some datasheets have 35000
 177          * x16 wide columns only?  Use 50000?
 178          */
 179         popts->tFAW_window_four_activates_ps = 37500;
 180
 181 #elif defined(CONFIG_FSL_DDR3)
 182 #error "FIXME determine four activates for DDR3"
 183 #endif
 184
 185         /*
 186          * Check interleaving configuration from environment.
 187          * Please refer to doc/README.fsl-ddr for the detail.
 188          *
 189          * If memory controller interleaving is enabled, then the data
 190          * bus widths must be programmed identically for the 2 memory
 191          * controllers.
 192          *
 193          * XXX: Attempt to set both controllers to the same chip select
 194          * interleaving mode. It will do a best effort to get the
 195          * requested ranks interleaved together such that the result
 196          * should be a subset of the requested configuration.
 197          */
 198         if ((p = getenv("memctl_intlv_ctl")) != NULL) {
 199                 if (pdimm[0].n_ranks == 0) {
 200                         printf("There is no rank on CS0. Because only rank on \
 201                                 CS0 and ranks chip-select interleaved with CS0\
 202                                 are controller interleaved, force non memory \
 203                                 controller interleaving\n");
 204                         popts->memctl_interleaving = 0;
 205                 } else {
 206                         popts->memctl_interleaving = 1;
 207                         if (strcmp(p, "cacheline") == 0)
 208                                 popts->memctl_interleaving_mode =
 209                                         FSL_DDR_CACHE_LINE_INTERLEAVING;
 210                         else if (strcmp(p, "page") == 0)
 211                                 popts->memctl_interleaving_mode =
 212                                         FSL_DDR_PAGE_INTERLEAVING;
 213                         else if (strcmp(p, "bank") == 0)
 214                                 popts->memctl_interleaving_mode =
 215                                         FSL_DDR_BANK_INTERLEAVING;
 216                         else if (strcmp(p, "superbank") == 0)
 217                                 popts->memctl_interleaving_mode =
 218                                         FSL_DDR_SUPERBANK_INTERLEAVING;
 219                         else
 220                                 popts->memctl_interleaving_mode =
 221                                                 simple_strtoul(p, NULL, 0);
 222                 }
 223         }
 224
 225         if( (p = getenv("ba_intlv_ctl")) != NULL) {
 226                 if (strcmp(p, "cs0_cs1") == 0)
 227                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 228                 else if (strcmp(p, "cs2_cs3") == 0)
 229                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 230                 else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
 231                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 232                 else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
 233                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 234                 else
 235                         popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);
 236
 237                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 238                 case FSL_DDR_CS0_CS1_CS2_CS3:
 239                 case FSL_DDR_CS0_CS1:
 240                         if (pdimm[0].n_ranks != 2) {
 241                                 popts->ba_intlv_ctl = 0;
 242                                 printf("No enough bank(chip-select) for \
 243                                         CS0+CS1, force non-interleaving!\n");
 244                         }
 245                         break;
 246                 case FSL_DDR_CS2_CS3:
 247                         if (pdimm[1].n_ranks !=2){
 248                                 popts->ba_intlv_ctl = 0;
 249                                 printf("No enough bank(CS) for CS2+CS3, \
 250                                         force non-interleaving!\n");
 251                         }
 252                         break;
 253                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 254                         if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
 255                                 popts->ba_intlv_ctl = 0;
 256                                 printf("No enough bank(CS) for CS0+CS1 or \
 257                                          CS2+CS3, force non-interleaving!\n");
 258                         }
 259                         break;
 260                 default:
 261                         popts->ba_intlv_ctl = 0;
 262                         break;
 263                 }
 264         }
 265
 266         fsl_ddr_board_options(popts, pdimm, ctrl_num);
 267
 268         return 0;
 269 }