1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 * 21-Nov-03 pavel.bartusek@sysgo.com
71 * - set ZMII bridge speed on 440
73 *-----------------------------------------------------------------------------*/
76 #include <asm/processor.h>
79 #include <405gp_enet.h>
86 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
87 ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI))
89 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
90 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
94 * Use PKTBUFSRX (include/net.h) instead of setting NUM_RX_BUFF again
95 * These both variables are used to define the same thing!
96 * #define NUM_RX_BUFF 4
98 #define NUM_RX_BUFF PKTBUFSRX
100 /* Ethernet Transmit and Receive Buffers */
102 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
103 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
105 #define ENET_MAX_MTU PKTSIZE
106 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
108 static char *txbuf_ptr
;
110 /* define the number of channels implemented */
114 /*-----------------------------------------------------------------------------+
115 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
116 * Interrupt Controller).
117 *-----------------------------------------------------------------------------*/
118 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
119 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
120 #define EMAC_UIC_DEF UIC_ENET
122 /*-----------------------------------------------------------------------------+
123 * Global variables. TX and RX descriptors and buffers.
124 *-----------------------------------------------------------------------------*/
125 static volatile mal_desc_t
*tx
;
126 static volatile mal_desc_t
*rx
;
127 static mal_desc_t
*alloc_tx_buf
= NULL
;
128 static mal_desc_t
*alloc_rx_buf
= NULL
;
131 static unsigned long emac_ier
;
132 static unsigned long mal_ier
;
135 /* Statistic Areas */
136 #define MAX_ERR_LOG 10
144 static struct stats
{ /* Statistic Block */
145 struct emac_stats emac
;
147 short tx_err_log
[MAX_ERR_LOG
];
148 short rx_err_log
[MAX_ERR_LOG
];
151 static int first_init
= 0;
153 static int tx_err_index
= 0; /* Transmit Error Index for tx_err_log */
154 static int rx_err_index
= 0; /* Receive Error Index for rx_err_log */
156 static int rx_slot
= 0; /* MAL Receive Slot */
157 static int rx_i_index
= 0; /* Receive Interrupt Queue Index */
158 static int rx_u_index
= 0; /* Receive User Queue Index */
159 static int rx_ready
[NUM_RX_BUFF
]; /* Receive Ready Queue */
161 static int tx_slot
= 0; /* MAL Transmit Slot */
162 static int tx_i_index
= 0; /* Transmit Interrupt Queue Index */
163 static int tx_u_index
= 0; /* Transmit User Queue Index */
164 static int tx_run
[NUM_TX_BUFF
]; /* Transmit Running Queue */
168 static int packetSent
= 0;
169 static int packetReceived
= 0;
170 static int packetHandled
= 0;
173 static char emac_hwd_addr
[ENET_ADDR_LENGTH
];
175 static bd_t
*bis_save
= NULL
; /* for eth_init upon mal error */
177 static int is_receiving
= 0; /* sync with eth interrupt */
178 static int print_speed
= 1; /* print speed message upon start */
180 /*-----------------------------------------------------------------------------+
181 * Prototypes and externals.
182 *-----------------------------------------------------------------------------*/
183 static void enet_rcv (unsigned long malisr
);
184 static int enetInt(void);
185 static void mal_err (unsigned long isr
, unsigned long uic
, unsigned long mal_def
,
186 unsigned long mal_errr
);
187 static void emac_err (unsigned long isr
);
189 static void ppc_4xx_eth_halt (struct eth_device
*dev
)
191 mtdcr (malier
, 0x00000000); /* disable mal interrupts */
192 out32 (EMAC_IER
, 0x00000000); /* disable emac interrupts */
195 mtdcr (malmcr
, MAL_CR_MMSR
);
198 while (mfdcr (malmcr
) & MAL_CR_MMSR
) {
202 out32 (EMAC_M0
, EMAC_M0_SRST
);
204 print_speed
= 1; /* print speed message again next time */
208 static int ppc_4xx_eth_init (struct eth_device
*dev
, bd_t
* bis
)
214 unsigned long duplex
;
216 unsigned short reg_short
;
219 mtmsr (msr
& ~(MSR_EE
)); /* disable interrupts */
224 * packetHandled <= packetReceived <= packetHandled+PKTBUFSRX
225 * In the most cases packetHandled = packetReceived, but it
226 * is possible that new packets (without relationship with
227 * current transfer) have got the time to arrived before
228 * netloop calls eth_halt
230 printf ("About preceeding transfer:\n"
231 "- Sent packet number %d\n"
232 "- Received packet number %d\n"
233 "- Handled packet number %d\n",
234 packetSent
, packetReceived
, packetHandled
);
241 mtdcr (malmcr
, MAL_CR_MMSR
);
243 while (mfdcr (malmcr
) & MAL_CR_MMSR
) {
246 tx_err_index
= 0; /* Transmit Error Index for tx_err_log */
247 rx_err_index
= 0; /* Receive Error Index for rx_err_log */
249 rx_slot
= 0; /* MAL Receive Slot */
250 rx_i_index
= 0; /* Receive Interrupt Queue Index */
251 rx_u_index
= 0; /* Receive User Queue Index */
253 tx_slot
= 0; /* MAL Transmit Slot */
254 tx_i_index
= 0; /* Transmit Interrupt Queue Index */
255 tx_u_index
= 0; /* Transmit User Queue Index */
257 #if defined(CONFIG_440)
259 out32 (ZMII_FER
, ZMII_RMII
| ZMII_MDI0
);
260 #endif /* CONFIG_440 */
263 out32 (EMAC_M0
, EMAC_M0_SRST
);
265 /* wait for PHY to complete auto negotiation */
267 #ifndef CONFIG_CS8952_PHY
268 miiphy_read (CONFIG_PHY_ADDR
, PHY_BMSR
, ®_short
);
271 * Wait if PHY is able of autonegotiation and autonegotiation is not complete
273 if ((reg_short
& PHY_BMSR_AUTN_ABLE
)
274 && !(reg_short
& PHY_BMSR_AUTN_COMP
)) {
275 puts ("Waiting for PHY auto negotiation to complete");
277 while (!(reg_short
& PHY_BMSR_AUTN_COMP
)) {
281 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
282 puts (" TIMEOUT !\n");
286 if ((i
++ % 1000) == 0)
288 udelay (1000); /* 1 ms */
289 miiphy_read (CONFIG_PHY_ADDR
, PHY_BMSR
, ®_short
);
292 udelay (500000); /* another 500 ms (results in faster booting) */
295 speed
= miiphy_speed (CONFIG_PHY_ADDR
);
296 duplex
= miiphy_duplex (CONFIG_PHY_ADDR
);
299 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
300 (int) speed
, (duplex
== HALF
) ? "HALF" : "FULL");
303 /* set the Mal configuration reg */
304 #if defined(CONFIG_440)
305 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
306 if( get_pvr() == PVR_440GP_RB
)
307 mtdcr (malmcr
, MAL_CR_OPBBL
| MAL_CR_LEA
| MAL_CR_PLBLT_DEFAULT
);
310 mtdcr (malmcr
, MAL_CR_PLBB
| MAL_CR_OPBBL
| MAL_CR_LEA
| MAL_CR_PLBLT_DEFAULT
);
313 /* Free "old" buffers */
314 if (alloc_tx_buf
) free(alloc_tx_buf
);
315 if (alloc_rx_buf
) free(alloc_rx_buf
);
318 * Malloc MAL buffer desciptors, make sure they are
319 * aligned on cache line boundary size
320 * (401/403/IOP480 = 16, 405 = 32)
321 * and doesn't cross cache block boundaries.
323 alloc_tx_buf
= (mal_desc_t
*)malloc((sizeof(mal_desc_t
) * NUM_TX_BUFF
) +
324 ((2 * CFG_CACHELINE_SIZE
) - 2));
325 if (((int)alloc_tx_buf
& CACHELINE_MASK
) != 0) {
326 tx
= (mal_desc_t
*)((int)alloc_tx_buf
+ CFG_CACHELINE_SIZE
-
327 ((int)alloc_tx_buf
& CACHELINE_MASK
));
332 alloc_rx_buf
= (mal_desc_t
*)malloc((sizeof(mal_desc_t
) * NUM_RX_BUFF
) +
333 ((2 * CFG_CACHELINE_SIZE
) - 2));
334 if (((int)alloc_rx_buf
& CACHELINE_MASK
) != 0) {
335 rx
= (mal_desc_t
*)((int)alloc_rx_buf
+ CFG_CACHELINE_SIZE
-
336 ((int)alloc_rx_buf
& CACHELINE_MASK
));
341 for (i
= 0; i
< NUM_TX_BUFF
; i
++) {
345 txbuf_ptr
= (char *) malloc (ENET_MAX_MTU_ALIGNED
);
346 tx
[i
].data_ptr
= txbuf_ptr
;
347 if ((NUM_TX_BUFF
- 1) == i
)
348 tx
[i
].ctrl
|= MAL_TX_CTRL_WRAP
;
351 printf ("TX_BUFF %d @ 0x%08lx\n", i
, (ulong
) tx
[i
].data_ptr
);
355 for (i
= 0; i
< NUM_RX_BUFF
; i
++) {
358 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
359 rx
[i
].data_ptr
= (char *) NetRxPackets
[i
];
360 if ((NUM_RX_BUFF
- 1) == i
)
361 rx
[i
].ctrl
|= MAL_RX_CTRL_WRAP
;
362 rx
[i
].ctrl
|= MAL_RX_CTRL_EMPTY
| MAL_RX_CTRL_INTR
;
365 printf ("RX_BUFF %d @ 0x%08lx\n", i
, (ulong
) rx
[i
].data_ptr
);
369 memcpy (emac_hwd_addr
, bis
->bi_enetaddr
, ENET_ADDR_LENGTH
);
373 reg
|= emac_hwd_addr
[0]; /* set high address */
375 reg
|= emac_hwd_addr
[1];
377 out32 (EMAC_IAH
, reg
);
380 reg
|= emac_hwd_addr
[2]; /* set low address */
382 reg
|= emac_hwd_addr
[3];
384 reg
|= emac_hwd_addr
[4];
386 reg
|= emac_hwd_addr
[5];
388 out32 (EMAC_IAL
, reg
);
390 /* setup MAL tx & rx channel pointers */
391 mtdcr (maltxctp0r
, tx
);
392 mtdcr (malrxctp0r
, rx
);
394 /* Reset transmit and receive channels */
395 mtdcr (malrxcarr
, 0x80000000); /* 2 channels */
396 mtdcr (maltxcarr
, 0x80000000); /* 2 channels */
398 /* Enable MAL transmit and receive channels */
399 mtdcr (maltxcasr
, 0x80000000); /* 1 channel */
400 mtdcr (malrxcasr
, 0x80000000); /* 1 channel */
402 /* set RX buffer size */
403 mtdcr (malrcbs0
, ENET_MAX_MTU_ALIGNED
/ 16);
405 /* set transmit enable & receive enable */
406 out32 (EMAC_M0
, EMAC_M0_TXE
| EMAC_M0_RXE
);
408 /* set receive fifo to 4k and tx fifo to 2k */
409 mode_reg
= EMAC_M1_RFS_4K
| EMAC_M1_TX_FIFO_2K
;
412 if (speed
== _100BASET
)
413 mode_reg
= mode_reg
| EMAC_M1_MF_100MBPS
| EMAC_M1_IST
;
415 mode_reg
= mode_reg
& ~0x00C00000; /* 10 MBPS */
417 mode_reg
= mode_reg
| 0x80000000 | EMAC_M1_IST
;
419 out32 (EMAC_M1
, mode_reg
);
421 #if defined(CONFIG_440)
422 /* set speed in the ZMII bridge */
423 if (speed
== _100BASET
)
424 out32(ZMII_SSR
, in32(ZMII_SSR
) | 0x10000000);
426 out32(ZMII_SSR
, in32(ZMII_SSR
) & ~0x10000000);
429 /* Enable broadcast and indvidual address */
430 out32 (EMAC_RXM
, EMAC_RMR_BAE
| EMAC_RMR_IAE
431 /*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );
433 /* we probably need to set the tx mode1 reg? maybe at tx time */
435 /* set transmit request threshold register */
436 out32 (EMAC_TRTR
, 0x18000000); /* 256 byte threshold */
438 /* set receive low/high water mark register */
439 #if defined(CONFIG_440)
440 /* 440GP has a 64 byte burst length */
441 out32 (EMAC_RX_HI_LO_WMARK
, 0x80009000);
442 out32 (EMAC_TXM1
, 0xf8640000);
443 #else /* CONFIG_440 */
444 /* 405s have a 16 byte burst length */
445 out32 (EMAC_RX_HI_LO_WMARK
, 0x0f002000);
446 #endif /* CONFIG_440 */
449 out32 (EMAC_I_FRAME_GAP_REG
, 0x00000008);
451 if (first_init
== 0) {
453 * Connect interrupt service routines
455 irq_install_handler (VECNUM_EWU0
, (interrupt_handler_t
*) enetInt
, NULL
);
456 irq_install_handler (VECNUM_MS
, (interrupt_handler_t
*) enetInt
, NULL
);
457 irq_install_handler (VECNUM_MTE
, (interrupt_handler_t
*) enetInt
, NULL
);
458 irq_install_handler (VECNUM_MRE
, (interrupt_handler_t
*) enetInt
, NULL
);
459 irq_install_handler (VECNUM_TXDE
, (interrupt_handler_t
*) enetInt
, NULL
);
460 irq_install_handler (VECNUM_RXDE
, (interrupt_handler_t
*) enetInt
, NULL
);
461 irq_install_handler (VECNUM_ETH0
, (interrupt_handler_t
*) enetInt
, NULL
);
464 /* set up interrupt handler */
465 /* setup interrupt controler to take interrupts from the MAL &
467 mtdcr (uicsr
, 0xffffffff); /* clear pending interrupts */
468 mtdcr (uicer
, mfdcr (uicer
) | MAL_UIC_DEF
| EMAC_UIC_DEF
);
470 /* set the MAL IER ??? names may change with new spec ??? */
471 mal_ier
= MAL_IER_DE
| MAL_IER_NE
| MAL_IER_TE
| MAL_IER_OPBE
|
473 mtdcr (malesr
, 0xffffffff); /* clear pending interrupts */
474 mtdcr (maltxdeir
, 0xffffffff); /* clear pending interrupts */
475 mtdcr (malrxdeir
, 0xffffffff); /* clear pending interrupts */
476 mtdcr (malier
, mal_ier
);
479 emac_ier
= EMAC_ISR_PTLE
| EMAC_ISR_BFCS
|
480 EMAC_ISR_PTLE
| EMAC_ISR_ORE
| EMAC_ISR_IRE
;
481 if (speed
== _100BASET
)
482 emac_ier
= emac_ier
| EMAC_ISR_SYE
;
484 out32 (EMAC_ISR
, 0xffffffff); /* clear pending interrupts */
485 out32 (EMAC_IER
, emac_ier
);
487 mtmsr (msr
); /* enable interrupts again */
496 static int ppc_4xx_eth_send (struct eth_device
*dev
, volatile void *ptr
, int len
)
498 struct enet_frame
*ef_ptr
;
499 ulong time_start
, time_now
;
500 unsigned long temp_txm0
;
502 ef_ptr
= (struct enet_frame
*) ptr
;
504 /*-----------------------------------------------------------------------+
505 * Copy in our address into the frame.
506 *-----------------------------------------------------------------------*/
507 (void) memcpy (ef_ptr
->source_addr
, emac_hwd_addr
, ENET_ADDR_LENGTH
);
509 /*-----------------------------------------------------------------------+
510 * If frame is too long or too short, modify length.
511 *-----------------------------------------------------------------------*/
512 if (len
> ENET_MAX_MTU
)
515 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
516 memcpy ((void *) txbuf_ptr
, (const void *) ptr
, len
);
518 /*-----------------------------------------------------------------------+
519 * set TX Buffer busy, and send it
520 *-----------------------------------------------------------------------*/
521 tx
[tx_slot
].ctrl
= (MAL_TX_CTRL_LAST
|
522 EMAC_TX_CTRL_GFCS
| EMAC_TX_CTRL_GP
) &
523 ~(EMAC_TX_CTRL_ISA
| EMAC_TX_CTRL_RSA
);
524 if ((NUM_TX_BUFF
- 1) == tx_slot
)
525 tx
[tx_slot
].ctrl
|= MAL_TX_CTRL_WRAP
;
527 tx
[tx_slot
].data_len
= (short) len
;
528 tx
[tx_slot
].ctrl
|= MAL_TX_CTRL_READY
;
530 __asm__
volatile ("eieio");
531 out32 (EMAC_TXM0
, in32 (EMAC_TXM0
) | EMAC_TXM0_GNP0
);
536 /*-----------------------------------------------------------------------+
537 * poll unitl the packet is sent and then make sure it is OK
538 *-----------------------------------------------------------------------*/
539 time_start
= get_timer (0);
541 temp_txm0
= in32 (EMAC_TXM0
);
542 /* loop until either TINT turns on or 3 seconds elapse */
543 if ((temp_txm0
& EMAC_TXM0_GNP0
) != 0) {
544 /* transmit is done, so now check for errors
545 * If there is an error, an interrupt should
546 * happen when we return
548 time_now
= get_timer (0);
549 if ((time_now
- time_start
) > 3000) {
559 #if defined(CONFIG_440)
560 /*-----------------------------------------------------------------------------+
562 | EnetInt is the interrupt handler. It will determine the
563 | cause of the interrupt and call the apporpriate servive
565 +-----------------------------------------------------------------------------*/
569 int rc
= -1; /* default to not us */
570 unsigned long mal_isr
;
571 unsigned long emac_isr
= 0;
572 unsigned long mal_rx_eob
;
573 unsigned long my_uic0msr
, my_uic1msr
;
575 /* enter loop that stays in interrupt code until nothing to service */
579 my_uic0msr
= mfdcr (uic0msr
);
580 my_uic1msr
= mfdcr (uic1msr
);
582 if (!(my_uic0msr
& UIC_MRE
)
583 && !(my_uic1msr
& (UIC_ETH0
| UIC_MS
| UIC_MTDE
| UIC_MRDE
))) {
588 /* get and clear controller status interrupts */
589 /* look at Mal and EMAC interrupts */
590 if ((my_uic0msr
& UIC_MRE
)
591 || (my_uic1msr
& (UIC_MS
| UIC_MTDE
| UIC_MRDE
))) {
592 /* we have a MAL interrupt */
593 mal_isr
= mfdcr (malesr
);
594 /* look for mal error */
595 if (my_uic1msr
& (UIC_MS
| UIC_MTDE
| UIC_MRDE
)) {
596 mal_err (mal_isr
, my_uic0msr
, MAL_UIC_DEF
, MAL_UIC_ERR
);
601 if (UIC_ETH0
& my_uic1msr
) { /* look for EMAC errors */
602 emac_isr
= in32 (EMAC_ISR
);
603 if ((emac_ier
& emac_isr
) != 0) {
609 if ((emac_ier
& emac_isr
)
610 || (my_uic1msr
& (UIC_MS
| UIC_MTDE
| UIC_MRDE
))) {
611 mtdcr (uic0sr
, UIC_MRE
); /* Clear */
612 mtdcr (uic1sr
, UIC_ETH0
| UIC_MS
| UIC_MTDE
| UIC_MRDE
); /* Clear */
613 return (rc
); /* we had errors so get out */
616 /* handle MAL RX EOB interupt from a receive */
617 /* check for EOB on valid channels */
618 if (my_uic0msr
& UIC_MRE
) {
619 mal_rx_eob
= mfdcr (malrxeobisr
);
620 if ((mal_rx_eob
& 0x80000000) != 0) { /* call emac routine for channel 0 */
622 mtdcr(malrxeobisr, mal_rx_eob); */
624 /* indicate that we serviced an interrupt */
629 mtdcr (uic0sr
, UIC_MRE
); /* Clear */
630 mtdcr (uic1sr
, UIC_ETH0
| UIC_MS
| UIC_MTDE
| UIC_MRDE
); /* Clear */
635 #else /* CONFIG_440 */
636 /*-----------------------------------------------------------------------------+
638 * EnetInt is the interrupt handler. It will determine the
639 * cause of the interrupt and call the apporpriate servive
641 *-----------------------------------------------------------------------------*/
645 int rc
= -1; /* default to not us */
646 unsigned long mal_isr
;
647 unsigned long emac_isr
= 0;
648 unsigned long mal_rx_eob
;
649 unsigned long my_uicmsr
;
651 /* enter loop that stays in interrupt code until nothing to service */
655 my_uicmsr
= mfdcr (uicmsr
);
656 if ((my_uicmsr
& (MAL_UIC_DEF
| EMAC_UIC_DEF
)) == 0) { /* not for us */
661 /* get and clear controller status interrupts */
662 /* look at Mal and EMAC interrupts */
663 if ((MAL_UIC_DEF
& my_uicmsr
) != 0) { /* we have a MAL interrupt */
664 mal_isr
= mfdcr (malesr
);
665 /* look for mal error */
666 if ((my_uicmsr
& MAL_UIC_ERR
) != 0) {
667 mal_err (mal_isr
, my_uicmsr
, MAL_UIC_DEF
, MAL_UIC_ERR
);
672 if ((EMAC_UIC_DEF
& my_uicmsr
) != 0) { /* look for EMAC errors */
673 emac_isr
= in32 (EMAC_ISR
);
674 if ((emac_ier
& emac_isr
) != 0) {
680 if (((emac_ier
& emac_isr
) != 0) | ((MAL_UIC_ERR
& my_uicmsr
) != 0)) {
681 mtdcr (uicsr
, MAL_UIC_DEF
| EMAC_UIC_DEF
); /* Clear */
682 return (rc
); /* we had errors so get out */
686 /* handle MAL RX EOB interupt from a receive */
687 /* check for EOB on valid channels */
688 if ((my_uicmsr
& UIC_MAL_RXEOB
) != 0) {
689 mal_rx_eob
= mfdcr (malrxeobisr
);
690 if ((mal_rx_eob
& 0x80000000) != 0) { /* call emac routine for channel 0 */
692 mtdcr(malrxeobisr, mal_rx_eob); */
694 /* indicate that we serviced an interrupt */
699 mtdcr (uicsr
, MAL_UIC_DEF
| EMAC_UIC_DEF
); /* Clear */
705 #endif /* CONFIG_440 */
707 /*-----------------------------------------------------------------------------+
709 *-----------------------------------------------------------------------------*/
710 static void mal_err (unsigned long isr
, unsigned long uic
, unsigned long maldef
,
711 unsigned long mal_errr
)
713 mtdcr (malesr
, isr
); /* clear interrupt */
715 /* clear DE interrupt */
716 mtdcr (maltxdeir
, 0xC0000000);
717 mtdcr (malrxdeir
, 0x80000000);
720 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n",
721 isr
, uic
, maldef
, mal_errr
);
725 * MAL error is RX DE error (out of rx buffers)! This is OK here, upon
726 * many incoming packets with only 4 rx buffers.
728 printf ("M"); /* just to see something upon mal error */
732 eth_init (bis_save
); /* start again... */
735 /*-----------------------------------------------------------------------------+
737 *-----------------------------------------------------------------------------*/
738 static void emac_err (unsigned long isr
)
740 printf ("EMAC error occured.... ISR = %lx\n", isr
);
741 out32 (EMAC_ISR
, isr
);
744 /*-----------------------------------------------------------------------------+
745 * enet_rcv() handles the ethernet receive data
746 *-----------------------------------------------------------------------------*/
747 static void enet_rcv (unsigned long malisr
)
749 struct enet_frame
*ef_ptr
;
750 unsigned long data_len
;
751 unsigned long rx_eob_isr
;
757 rx_eob_isr
= mfdcr (malrxeobisr
);
758 if ((0x80000000 >> (EMAC_RXCHL
- 1)) & rx_eob_isr
) {
760 mtdcr (malrxeobisr
, rx_eob_isr
);
763 while (1) { /* do all */
766 if ((MAL_RX_CTRL_EMPTY
& rx
[i
].ctrl
)
767 || (loop_count
>= NUM_RX_BUFF
))
771 if (NUM_RX_BUFF
== rx_slot
)
774 data_len
= (unsigned long) rx
[i
].data_len
; /* Get len */
776 if (data_len
> ENET_MAX_MTU
) /* Check len */
779 if (EMAC_RX_ERRORS
& rx
[i
].ctrl
) { /* Check Errors */
781 stats
.rx_err_log
[rx_err_index
] = rx
[i
].ctrl
;
783 if (rx_err_index
== MAX_ERR_LOG
)
786 } /* data_len < max mtu */
788 if (!data_len
) { /* no data */
789 rx
[i
].ctrl
|= MAL_RX_CTRL_EMPTY
; /* Free Recv Buffer */
791 stats
.emac
.data_len_err
++; /* Error at Rx */
796 /* Check if user has already eaten buffer */
797 /* if not => ERROR */
798 else if (rx_ready
[rx_i_index
] != -1) {
800 printf ("ERROR : Receive buffers are full!\n");
803 stats
.emac
.rx_frames
++;
804 stats
.emac
.rx
+= data_len
;
805 ef_ptr
= (struct enet_frame
*) rx
[i
].data_ptr
;
812 rx_ready
[rx_i_index
] = i
;
814 if (NUM_RX_BUFF
== rx_i_index
)
817 /* printf("X"); /|* test-only *|/ */
820 * free receive buffer only when
821 * buffer has been handled (eth_rx)
822 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
826 } /* if EMACK_RXCHL */
830 static int ppc_4xx_eth_rx (struct eth_device
*dev
)
836 is_receiving
= 1; /* tell driver */
840 * use ring buffer and
841 * get index from rx buffer desciptor queue
843 user_index
= rx_ready
[rx_u_index
];
844 if (user_index
== -1) {
846 break; /* nothing received - leave for() loop */
850 mtmsr (msr
& ~(MSR_EE
));
852 length
= rx
[user_index
].data_len
;
854 /* Pass the packet up to the protocol layers. */
855 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
856 /* NetReceive(NetRxPackets[i], length); */
857 NetReceive (NetRxPackets
[user_index
], length
- 4);
858 /* Free Recv Buffer */
859 rx
[user_index
].ctrl
|= MAL_RX_CTRL_EMPTY
;
860 /* Free rx buffer descriptor queue */
861 rx_ready
[rx_u_index
] = -1;
863 if (NUM_RX_BUFF
== rx_u_index
)
870 mtmsr (msr
); /* Enable IRQ's */
873 is_receiving
= 0; /* tell driver */
878 #if defined(CONFIG_NET_MULTI)
879 int ppc_4xx_eth_initialize(bd_t
*bis
)
881 struct eth_device
*dev
;
884 dev
= malloc (sizeof *dev
);
886 printf(__FUNCTION__
": Cannot allocate eth_device\n");
890 sprintf(dev
->name
, "ppc_4xx_eth%d", eth_num
);
891 dev
->priv
= (void *) eth_num
;
892 dev
->init
= ppc_4xx_eth_init
;
893 dev
->halt
= ppc_4xx_eth_halt
;
894 dev
->send
= ppc_4xx_eth_send
;
895 dev
->recv
= ppc_4xx_eth_rx
;
899 #else /* !defined(CONFIG_NET_MULTI) */
902 ppc_4xx_eth_halt(NULL
);
905 int eth_init (bd_t
*bis
)
907 return (ppc_4xx_eth_init(NULL
, bis
));
909 int eth_send(volatile void *packet
, int length
)
911 return (ppc_4xx_eth_send(NULL
, packet
, length
));
916 return (ppc_4xx_eth_rx(NULL
));
918 #endif /* !defined(CONFIG_NET_MULTI) */
920 #endif /* CONFIG_405GP */