cpu/ppc4xx/40x_spd_sdram.c

   1 /*
   2  * cpu/ppc4xx/40x_spd_sdram.c
   3  * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
   4  * SDRAM controller. Those are all current 405 PPC's.
   5  *
   6  * (C) Copyright 2001
   7  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   8  *
   9  * Based on code by:
  10  *
  11  * Kenneth Johansson ,Ericsson AB.
  12  * kenneth.johansson@etx.ericsson.se
  13  *
  14  * hacked up by bill hunter. fixed so we could run before
  15  * serial_init and console_init. previous version avoided this by
  16  * running out of cache memory during serial/console init, then running
  17  * this code later.
  18  *
  19  * (C) Copyright 2002
  20  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  21  * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
  22  *
  23  * (C) Copyright 2005
  24  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  25  *
  26  * See file CREDITS for list of people who contributed to this
  27  * project.
  28  *
  29  * This program is free software; you can redistribute it and/or
  30  * modify it under the terms of the GNU General Public License as
  31  * published by the Free Software Foundation; either version 2 of
  32  * the License, or (at your option) any later version.
  33  *
  34  * This program is distributed in the hope that it will be useful,
  35  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  36  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  37  * GNU General Public License for more details.
  38  *
  39  * You should have received a copy of the GNU General Public License
  40  * along with this program; if not, write to the Free Software
  41  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  42  * MA 02111-1307 USA
  43  */
  44
  45 #include <common.h>
  46 #include <asm/processor.h>
  47 #include <i2c.h>
  48 #include <ppc4xx.h>
  49
  50 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
  51
  52 /*
  53  * Set default values
  54  */
  55 #ifndef CONFIG_SYS_I2C_SPEED
  56 #define CONFIG_SYS_I2C_SPEED    50000
  57 #endif
  58
  59 #ifndef CONFIG_SYS_I2C_SLAVE
  60 #define CONFIG_SYS_I2C_SLAVE    0xFE
  61 #endif
  62
  63 #define ONE_BILLION     1000000000
  64
  65 #define  SDRAM0_CFG_DCE         0x80000000
  66 #define  SDRAM0_CFG_SRE         0x40000000
  67 #define  SDRAM0_CFG_PME         0x20000000
  68 #define  SDRAM0_CFG_MEMCHK      0x10000000
  69 #define  SDRAM0_CFG_REGEN       0x08000000
  70 #define  SDRAM0_CFG_ECCDD       0x00400000
  71 #define  SDRAM0_CFG_EMDULR      0x00200000
  72 #define  SDRAM0_CFG_DRW_SHIFT   (31-6)
  73 #define  SDRAM0_CFG_BRPF_SHIFT  (31-8)
  74
  75 #define  SDRAM0_TR_CASL_SHIFT   (31-8)
  76 #define  SDRAM0_TR_PTA_SHIFT    (31-13)
  77 #define  SDRAM0_TR_CTP_SHIFT    (31-15)
  78 #define  SDRAM0_TR_LDF_SHIFT    (31-17)
  79 #define  SDRAM0_TR_RFTA_SHIFT   (31-29)
  80 #define  SDRAM0_TR_RCD_SHIFT    (31-31)
  81
  82 #define  SDRAM0_RTR_SHIFT       (31-15)
  83 #define  SDRAM0_ECCCFG_SHIFT    (31-11)
  84
  85 /* SDRAM0_CFG enable macro  */
  86 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
  87
  88 #define SDRAM0_BXCR_SZ_MASK     0x000e0000
  89 #define SDRAM0_BXCR_AM_MASK     0x0000e000
  90
  91 #define SDRAM0_BXCR_SZ_SHIFT    (31-14)
  92 #define SDRAM0_BXCR_AM_SHIFT    (31-18)
  93
  94 #define SDRAM0_BXCR_SZ(x)       ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
  95 #define SDRAM0_BXCR_AM(x)       ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
  96
  97 #ifdef CONFIG_SPDDRAM_SILENT
  98 # define SPD_ERR(x) do { return 0; } while (0)
  99 #else
 100 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
 101 #endif
 102
 103 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
 104
 105 /* function prototypes */
 106 int spd_read(uint addr);
 107
 108
 109 /*
 110  * This function is reading data from the DIMM module EEPROM over the SPD bus
 111  * and uses that to program the sdram controller.
 112  *
 113  * This works on boards that has the same schematics that the AMCC walnut has.
 114  *
 115  * Input: null for default I2C spd functions or a pointer to a custom function
 116  * returning spd_data.
 117  */
 118
 119 long int spd_sdram(int(read_spd)(uint addr))
 120 {
 121         int tmp,row,col;
 122         int total_size,bank_size,bank_code;
 123         int ecc_on;
 124         int mode;
 125         int bank_cnt;
 126
 127         int sdram0_pmit=0x07c00000;
 128 #ifndef CONFIG_405EP /* not on PPC405EP */
 129         int sdram0_besr0 = -1;
 130         int sdram0_besr1 = -1;
 131         int sdram0_eccesr = -1;
 132 #endif
 133         int sdram0_ecccfg;
 134
 135         int sdram0_rtr=0;
 136         int sdram0_tr=0;
 137
 138         int sdram0_b0cr;
 139         int sdram0_b1cr;
 140         int sdram0_b2cr;
 141         int sdram0_b3cr;
 142
 143         int sdram0_cfg=0;
 144
 145         int t_rp;
 146         int t_rcd;
 147         int t_ras;
 148         int t_rc;
 149         int min_cas;
 150
 151         PPC4xx_SYS_INFO sys_info;
 152         unsigned long bus_period_x_10;
 153
 154         /*
 155          * get the board info
 156          */
 157         get_sys_info(&sys_info);
 158         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 159
 160         if (read_spd == 0){
 161                 read_spd=spd_read;
 162                 /*
 163                  * Make sure I2C controller is initialized
 164                  * before continuing.
 165                  */
 166                 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 167         }
 168
 169         /* Make shure we are using SDRAM */
 170         if (read_spd(2) != 0x04) {
 171                 SPD_ERR("SDRAM - non SDRAM memory module found\n");
 172         }
 173
 174         /* ------------------------------------------------------------------
 175          * configure memory timing register
 176          *
 177          * data from DIMM:
 178          * 27   IN Row Precharge Time ( t RP)
 179          * 29   MIN RAS to CAS Delay ( t RCD)
 180          * 127   Component and Clock Detail ,clk0-clk3, junction temp, CAS
 181          * -------------------------------------------------------------------*/
 182
 183         /*
 184          * first figure out which cas latency mode to use
 185          * use the min supported mode
 186          */
 187
 188         tmp = read_spd(127) & 0x6;
 189         if (tmp == 0x02) {              /* only cas = 2 supported */
 190                 min_cas = 2;
 191 /*              t_ck = read_spd(9); */
 192 /*              t_ac = read_spd(10); */
 193         } else if (tmp == 0x04) {       /* only cas = 3 supported */
 194                 min_cas = 3;
 195 /*              t_ck = read_spd(9); */
 196 /*              t_ac = read_spd(10); */
 197         } else if (tmp == 0x06) {       /* 2,3 supported, so use 2 */
 198                 min_cas = 2;
 199 /*              t_ck = read_spd(23); */
 200 /*              t_ac = read_spd(24); */
 201         } else {
 202                 SPD_ERR("SDRAM - unsupported CAS latency \n");
 203         }
 204
 205         /* get some timing values, t_rp,t_rcd,t_ras,t_rc
 206          */
 207         t_rp = read_spd(27);
 208         t_rcd = read_spd(29);
 209         t_ras = read_spd(30);
 210         t_rc = t_ras + t_rp;
 211
 212         /* The following timing calcs subtract 1 before deviding.
 213          * this has effect of using ceiling instead of floor rounding,
 214          * and also subtracting 1 to convert number to reg value
 215          */
 216         /* set up CASL */
 217         sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
 218         /* set up PTA */
 219         sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
 220         /* set up CTP */
 221         tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
 222         if (tmp < 1)
 223                 tmp = 1;
 224         sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
 225         /* set LDF      = 2 cycles, reg value = 1 */
 226         sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
 227         /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
 228         tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
 229         if (tmp < 0)
 230                 tmp = 0;
 231         if (tmp > 6)
 232                 tmp = 6;
 233         sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
 234         /* set RCD = t_rcd/bus_period*/
 235         sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
 236
 237
 238         /*------------------------------------------------------------------
 239          * configure RTR register
 240          * -------------------------------------------------------------------*/
 241         row = read_spd(3);
 242         col = read_spd(4);
 243         tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
 244         switch (tmp) {
 245         case 0x00:
 246                 tmp = 15625;
 247                 break;
 248         case 0x01:
 249                 tmp = 15625 / 4;
 250                 break;
 251         case 0x02:
 252                 tmp = 15625 / 2;
 253                 break;
 254         case 0x03:
 255                 tmp = 15625 * 2;
 256                 break;
 257         case 0x04:
 258                 tmp = 15625 * 4;
 259                 break;
 260         case 0x05:
 261                 tmp = 15625 * 8;
 262                 break;
 263         default:
 264                 SPD_ERR("SDRAM - Bad refresh period \n");
 265         }
 266         /* convert from nsec to bus cycles */
 267         tmp = (tmp * 10) / bus_period_x_10;
 268         sdram0_rtr = (tmp & 0x3ff8) <<  SDRAM0_RTR_SHIFT;
 269
 270         /*------------------------------------------------------------------
 271          * determine the number of banks used
 272          * -------------------------------------------------------------------*/
 273         /* byte 7:6 is module data width */
 274         if (read_spd(7) != 0)
 275                 SPD_ERR("SDRAM - unsupported module width\n");
 276         tmp = read_spd(6);
 277         if (tmp < 32)
 278                 SPD_ERR("SDRAM - unsupported module width\n");
 279         else if (tmp < 64)
 280                 bank_cnt = 1;           /* one bank per sdram side */
 281         else if (tmp < 73)
 282                 bank_cnt = 2;   /* need two banks per side */
 283         else if (tmp < 161)
 284                 bank_cnt = 4;   /* need four banks per side */
 285         else
 286                 SPD_ERR("SDRAM - unsupported module width\n");
 287
 288         /* byte 5 is the module row count (refered to as dimm "sides") */
 289         tmp = read_spd(5);
 290         if (tmp == 1)
 291                 ;
 292         else if (tmp==2)
 293                 bank_cnt *= 2;
 294         else if (tmp==4)
 295                 bank_cnt *= 4;
 296         else
 297                 bank_cnt = 8;           /* 8 is an error code */
 298
 299         if (bank_cnt > 4)       /* we only have 4 banks to work with */
 300                 SPD_ERR("SDRAM - unsupported module rows for this width\n");
 301
 302         /* now check for ECC ability of module. We only support ECC
 303          *   on 32 bit wide devices with 8 bit ECC.
 304          */
 305         if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
 306                 sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
 307                 ecc_on = 1;
 308         } else {
 309                 sdram0_ecccfg = 0;
 310                 ecc_on = 0;
 311         }
 312
 313         /*------------------------------------------------------------------
 314          * calculate total size
 315          * -------------------------------------------------------------------*/
 316         /* calculate total size and do sanity check */
 317         tmp = read_spd(31);
 318         total_size = 1 << 22;   /* total_size = 4MB */
 319         /* now multiply 4M by the smallest device row density */
 320         /* note that we don't support asymetric rows */
 321         while (((tmp & 0x0001) == 0) && (tmp != 0)) {
 322                 total_size = total_size << 1;
 323                 tmp = tmp >> 1;
 324         }
 325         total_size *= read_spd(5);      /* mult by module rows (dimm sides) */
 326
 327         /*------------------------------------------------------------------
 328          * map  rows * cols * banks to a mode
 329          * -------------------------------------------------------------------*/
 330
 331         switch (row) {
 332         case 11:
 333                 switch (col) {
 334                 case 8:
 335                         mode=4; /* mode 5 */
 336                         break;
 337                 case 9:
 338                 case 10:
 339                         mode=0; /* mode 1 */
 340                         break;
 341                 default:
 342                         SPD_ERR("SDRAM - unsupported mode\n");
 343                 }
 344                 break;
 345         case 12:
 346                 switch (col) {
 347                 case 8:
 348                         mode=3; /* mode 4 */
 349                         break;
 350                 case 9:
 351                 case 10:
 352                         mode=1; /* mode 2 */
 353                         break;
 354                 default:
 355                         SPD_ERR("SDRAM - unsupported mode\n");
 356                 }
 357                 break;
 358         case 13:
 359                 switch (col) {
 360                 case 8:
 361                         mode=5; /* mode 6 */
 362                         break;
 363                 case 9:
 364                 case 10:
 365                         if (read_spd(17) == 2)
 366                                 mode = 6; /* mode 7 */
 367                         else
 368                                 mode = 2; /* mode 3 */
 369                         break;
 370                 case 11:
 371                         mode = 2; /* mode 3 */
 372                         break;
 373                 default:
 374                         SPD_ERR("SDRAM - unsupported mode\n");
 375                 }
 376                 break;
 377         default:
 378                 SPD_ERR("SDRAM - unsupported mode\n");
 379         }
 380
 381         /*------------------------------------------------------------------
 382          * using the calculated values, compute the bank
 383          * config register values.
 384          * -------------------------------------------------------------------*/
 385         sdram0_b1cr = 0;
 386         sdram0_b2cr = 0;
 387         sdram0_b3cr = 0;
 388
 389         /* compute the size of each bank */
 390         bank_size = total_size / bank_cnt;
 391         /* convert bank size to bank size code for ppc4xx
 392            by takeing log2(bank_size) - 22 */
 393         tmp = bank_size;                /* start with tmp = bank_size */
 394         bank_code = 0;                  /* and bank_code = 0 */
 395         while (tmp > 1) {               /* this takes log2 of tmp */
 396                 bank_code++;            /* and stores result in bank_code */
 397                 tmp = tmp >> 1;
 398         }                               /* bank_code is now log2(bank_size) */
 399         bank_code -= 22;                /* subtract 22 to get the code */
 400
 401         tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
 402         sdram0_b0cr = (bank_size * 0) | tmp;
 403 #ifndef CONFIG_405EP /* not on PPC405EP */
 404         if (bank_cnt > 1)
 405                 sdram0_b2cr = (bank_size * 1) | tmp;
 406         if (bank_cnt > 2)
 407                 sdram0_b1cr = (bank_size * 2) | tmp;
 408         if (bank_cnt > 3)
 409                 sdram0_b3cr = (bank_size * 3) | tmp;
 410 #else
 411         /* PPC405EP chip only supports two SDRAM banks */
 412         if (bank_cnt > 1)
 413                 sdram0_b1cr = (bank_size * 1) | tmp;
 414         if (bank_cnt > 2)
 415                 total_size = 2 * bank_size;
 416 #endif
 417
 418         /*
 419          *   enable sdram controller DCE=1
 420          *  enable burst read prefetch to 32 bytes BRPF=2
 421          *  leave other functions off
 422          */
 423
 424         /*------------------------------------------------------------------
 425          * now that we've done our calculations, we are ready to
 426          * program all the registers.
 427          * -------------------------------------------------------------------*/
 428
 429 #define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
 430         /* disable memcontroller so updates work */
 431         mtsdram0( mem_mcopt1, 0 );
 432
 433 #ifndef CONFIG_405EP /* not on PPC405EP */
 434         mtsdram0( mem_besra , sdram0_besr0 );
 435         mtsdram0( mem_besrb , sdram0_besr1 );
 436         mtsdram0( mem_ecccf , sdram0_ecccfg );
 437         mtsdram0( mem_eccerr, sdram0_eccesr );
 438 #endif
 439         mtsdram0( mem_rtr   , sdram0_rtr );
 440         mtsdram0( mem_pmit  , sdram0_pmit );
 441         mtsdram0( mem_mb0cf , sdram0_b0cr );
 442         mtsdram0( mem_mb1cf , sdram0_b1cr );
 443 #ifndef CONFIG_405EP /* not on PPC405EP */
 444         mtsdram0( mem_mb2cf , sdram0_b2cr );
 445         mtsdram0( mem_mb3cf , sdram0_b3cr );
 446 #endif
 447         mtsdram0( mem_sdtr1 , sdram0_tr );
 448
 449         /* SDRAM have a power on delay,  500 micro should do */
 450         udelay(500);
 451         sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
 452         if (ecc_on)
 453                 sdram0_cfg |= SDRAM0_CFG_MEMCHK;
 454         mtsdram0(mem_mcopt1, sdram0_cfg);
 455
 456         return (total_size);
 457 }
 458
 459 int spd_read(uint addr)
 460 {
 461         uchar data[2];
 462
 463         if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
 464                 return (int)data[0];
 465         else
 466                 return 0;
 467 }
 468
 469 #endif /* CONFIG_SPD_EEPROM */