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[people/ms/u-boot.git] / cpu / ppc4xx / 44x_spd_ddr2.c
1 /*
2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
5 *
6 * 405: 405EX(r)
7 * 440/460: 440SP/440SPe/460EX/460GT
8 *
9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
11
12 * (C) Copyright 2007-2008
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
14 *
15 * COPYRIGHT AMCC CORPORATION 2004
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 *
35 */
36
37 /* define DEBUG for debugging output (obviously ;-)) */
38 #if 0
39 #define DEBUG
40 #endif
41
42 #include <common.h>
43 #include <command.h>
44 #include <ppc4xx.h>
45 #include <i2c.h>
46 #include <asm/io.h>
47 #include <asm/processor.h>
48 #include <asm/mmu.h>
49 #include <asm/cache.h>
50
51 #include "ecc.h"
52
53 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
54
55 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
56 do { \
57 u32 data; \
58 mfsdram(SDRAM_##mnemonic, data); \
59 printf("%20s[%02x] = 0x%08X\n", \
60 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
61 } while (0)
62
63 static inline void ppc4xx_ibm_ddr2_register_dump(void);
64
65 #if defined(CONFIG_SPD_EEPROM)
66
67 /*-----------------------------------------------------------------------------+
68 * Defines
69 *-----------------------------------------------------------------------------*/
70 #ifndef TRUE
71 #define TRUE 1
72 #endif
73 #ifndef FALSE
74 #define FALSE 0
75 #endif
76
77 #define SDRAM_DDR1 1
78 #define SDRAM_DDR2 2
79 #define SDRAM_NONE 0
80
81 #define MAXDIMMS 2
82 #define MAXRANKS 4
83 #define MAXBXCF 4
84 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
85
86 #define ONE_BILLION 1000000000
87
88 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
89
90 #define CMD_NOP (7 << 19)
91 #define CMD_PRECHARGE (2 << 19)
92 #define CMD_REFRESH (1 << 19)
93 #define CMD_EMR (0 << 19)
94 #define CMD_READ (5 << 19)
95 #define CMD_WRITE (4 << 19)
96
97 #define SELECT_MR (0 << 16)
98 #define SELECT_EMR (1 << 16)
99 #define SELECT_EMR2 (2 << 16)
100 #define SELECT_EMR3 (3 << 16)
101
102 /* MR */
103 #define DLL_RESET 0x00000100
104
105 #define WRITE_RECOV_2 (1 << 9)
106 #define WRITE_RECOV_3 (2 << 9)
107 #define WRITE_RECOV_4 (3 << 9)
108 #define WRITE_RECOV_5 (4 << 9)
109 #define WRITE_RECOV_6 (5 << 9)
110
111 #define BURST_LEN_4 0x00000002
112
113 /* EMR */
114 #define ODT_0_OHM 0x00000000
115 #define ODT_50_OHM 0x00000044
116 #define ODT_75_OHM 0x00000004
117 #define ODT_150_OHM 0x00000040
118
119 #define ODS_FULL 0x00000000
120 #define ODS_REDUCED 0x00000002
121
122 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
123 #define ODT_EB0R (0x80000000 >> 8)
124 #define ODT_EB0W (0x80000000 >> 7)
125 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
126 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
127 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
128
129 /* Defines for the Read Cycle Delay test */
130 #define NUMMEMTESTS 8
131 #define NUMMEMWORDS 8
132 #define NUMLOOPS 64 /* memory test loops */
133
134 /*
135 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
136 * region. Right now the cache should still be disabled in U-Boot because of the
137 * EMAC driver, that need it's buffer descriptor to be located in non cached
138 * memory.
139 *
140 * If at some time this restriction doesn't apply anymore, just define
141 * CONFIG_4xx_DCACHE in the board config file and this code should setup
142 * everything correctly.
143 */
144 #ifdef CONFIG_4xx_DCACHE
145 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
146 #else
147 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
148 #endif
149
150 /*
151 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
152 * To support such configurations, we "only" map the first 2GB via the TLB's. We
153 * need some free virtual address space for the remaining peripherals like, SoC
154 * devices, FLASH etc.
155 *
156 * Note that ECC is currently not supported on configurations with more than 2GB
157 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
158 * the ECC parity byte of the remaining area can't be written.
159 */
160 #ifndef CONFIG_MAX_MEM_MAPPED
161 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
162 #endif
163
164 /*
165 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
166 */
167 void __spd_ddr_init_hang (void)
168 {
169 hang ();
170 }
171 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
172
173 /*
174 * To provide an interface for board specific config values in this common
175 * DDR setup code, we implement he "weak" default functions here. They return
176 * the default value back to the caller.
177 *
178 * Please see include/configs/yucca.h for an example fora board specific
179 * implementation.
180 */
181 u32 __ddr_wrdtr(u32 default_val)
182 {
183 return default_val;
184 }
185 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
186
187 u32 __ddr_clktr(u32 default_val)
188 {
189 return default_val;
190 }
191 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
192
193
194 /* Private Structure Definitions */
195
196 /* enum only to ease code for cas latency setting */
197 typedef enum ddr_cas_id {
198 DDR_CAS_2 = 20,
199 DDR_CAS_2_5 = 25,
200 DDR_CAS_3 = 30,
201 DDR_CAS_4 = 40,
202 DDR_CAS_5 = 50
203 } ddr_cas_id_t;
204
205 /*-----------------------------------------------------------------------------+
206 * Prototypes
207 *-----------------------------------------------------------------------------*/
208 static phys_size_t sdram_memsize(void);
209 static void get_spd_info(unsigned long *dimm_populated,
210 unsigned char *iic0_dimm_addr,
211 unsigned long num_dimm_banks);
212 static void check_mem_type(unsigned long *dimm_populated,
213 unsigned char *iic0_dimm_addr,
214 unsigned long num_dimm_banks);
215 static void check_frequency(unsigned long *dimm_populated,
216 unsigned char *iic0_dimm_addr,
217 unsigned long num_dimm_banks);
218 static void check_rank_number(unsigned long *dimm_populated,
219 unsigned char *iic0_dimm_addr,
220 unsigned long num_dimm_banks);
221 static void check_voltage_type(unsigned long *dimm_populated,
222 unsigned char *iic0_dimm_addr,
223 unsigned long num_dimm_banks);
224 static void program_memory_queue(unsigned long *dimm_populated,
225 unsigned char *iic0_dimm_addr,
226 unsigned long num_dimm_banks);
227 static void program_codt(unsigned long *dimm_populated,
228 unsigned char *iic0_dimm_addr,
229 unsigned long num_dimm_banks);
230 static void program_mode(unsigned long *dimm_populated,
231 unsigned char *iic0_dimm_addr,
232 unsigned long num_dimm_banks,
233 ddr_cas_id_t *selected_cas,
234 int *write_recovery);
235 static void program_tr(unsigned long *dimm_populated,
236 unsigned char *iic0_dimm_addr,
237 unsigned long num_dimm_banks);
238 static void program_rtr(unsigned long *dimm_populated,
239 unsigned char *iic0_dimm_addr,
240 unsigned long num_dimm_banks);
241 static void program_bxcf(unsigned long *dimm_populated,
242 unsigned char *iic0_dimm_addr,
243 unsigned long num_dimm_banks);
244 static void program_copt1(unsigned long *dimm_populated,
245 unsigned char *iic0_dimm_addr,
246 unsigned long num_dimm_banks);
247 static void program_initplr(unsigned long *dimm_populated,
248 unsigned char *iic0_dimm_addr,
249 unsigned long num_dimm_banks,
250 ddr_cas_id_t selected_cas,
251 int write_recovery);
252 static unsigned long is_ecc_enabled(void);
253 #ifdef CONFIG_DDR_ECC
254 static void program_ecc(unsigned long *dimm_populated,
255 unsigned char *iic0_dimm_addr,
256 unsigned long num_dimm_banks,
257 unsigned long tlb_word2_i_value);
258 static void program_ecc_addr(unsigned long start_address,
259 unsigned long num_bytes,
260 unsigned long tlb_word2_i_value);
261 #endif
262 static void program_DQS_calibration(unsigned long *dimm_populated,
263 unsigned char *iic0_dimm_addr,
264 unsigned long num_dimm_banks);
265 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
266 static void test(void);
267 #else
268 static void DQS_calibration_process(void);
269 #endif
270 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
271 void dcbz_area(u32 start_address, u32 num_bytes);
272
273 static u32 mfdcr_any(u32 dcr)
274 {
275 u32 val;
276
277 switch (dcr) {
278 case SDRAM_R0BAS + 0:
279 val = mfdcr(SDRAM_R0BAS + 0);
280 break;
281 case SDRAM_R0BAS + 1:
282 val = mfdcr(SDRAM_R0BAS + 1);
283 break;
284 case SDRAM_R0BAS + 2:
285 val = mfdcr(SDRAM_R0BAS + 2);
286 break;
287 case SDRAM_R0BAS + 3:
288 val = mfdcr(SDRAM_R0BAS + 3);
289 break;
290 default:
291 printf("DCR %d not defined in case statement!!!\n", dcr);
292 val = 0; /* just to satisfy the compiler */
293 }
294
295 return val;
296 }
297
298 static void mtdcr_any(u32 dcr, u32 val)
299 {
300 switch (dcr) {
301 case SDRAM_R0BAS + 0:
302 mtdcr(SDRAM_R0BAS + 0, val);
303 break;
304 case SDRAM_R0BAS + 1:
305 mtdcr(SDRAM_R0BAS + 1, val);
306 break;
307 case SDRAM_R0BAS + 2:
308 mtdcr(SDRAM_R0BAS + 2, val);
309 break;
310 case SDRAM_R0BAS + 3:
311 mtdcr(SDRAM_R0BAS + 3, val);
312 break;
313 default:
314 printf("DCR %d not defined in case statement!!!\n", dcr);
315 }
316 }
317
318 static unsigned char spd_read(uchar chip, uint addr)
319 {
320 unsigned char data[2];
321
322 if (i2c_probe(chip) == 0)
323 if (i2c_read(chip, addr, 1, data, 1) == 0)
324 return data[0];
325
326 return 0;
327 }
328
329 /*-----------------------------------------------------------------------------+
330 * sdram_memsize
331 *-----------------------------------------------------------------------------*/
332 static phys_size_t sdram_memsize(void)
333 {
334 phys_size_t mem_size;
335 unsigned long mcopt2;
336 unsigned long mcstat;
337 unsigned long mb0cf;
338 unsigned long sdsz;
339 unsigned long i;
340
341 mem_size = 0;
342
343 mfsdram(SDRAM_MCOPT2, mcopt2);
344 mfsdram(SDRAM_MCSTAT, mcstat);
345
346 /* DDR controller must be enabled and not in self-refresh. */
347 /* Otherwise memsize is zero. */
348 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
349 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
350 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
351 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
352 for (i = 0; i < MAXBXCF; i++) {
353 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
354 /* Banks enabled */
355 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
356 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
357
358 switch(sdsz) {
359 case SDRAM_RXBAS_SDSZ_8:
360 mem_size+=8;
361 break;
362 case SDRAM_RXBAS_SDSZ_16:
363 mem_size+=16;
364 break;
365 case SDRAM_RXBAS_SDSZ_32:
366 mem_size+=32;
367 break;
368 case SDRAM_RXBAS_SDSZ_64:
369 mem_size+=64;
370 break;
371 case SDRAM_RXBAS_SDSZ_128:
372 mem_size+=128;
373 break;
374 case SDRAM_RXBAS_SDSZ_256:
375 mem_size+=256;
376 break;
377 case SDRAM_RXBAS_SDSZ_512:
378 mem_size+=512;
379 break;
380 case SDRAM_RXBAS_SDSZ_1024:
381 mem_size+=1024;
382 break;
383 case SDRAM_RXBAS_SDSZ_2048:
384 mem_size+=2048;
385 break;
386 case SDRAM_RXBAS_SDSZ_4096:
387 mem_size+=4096;
388 break;
389 default:
390 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
391 , sdsz);
392 mem_size=0;
393 break;
394 }
395 }
396 }
397 }
398
399 return mem_size << 20;
400 }
401
402 /*-----------------------------------------------------------------------------+
403 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
404 * Note: This routine runs from flash with a stack set up in the chip's
405 * sram space. It is important that the routine does not require .sbss, .bss or
406 * .data sections. It also cannot call routines that require these sections.
407 *-----------------------------------------------------------------------------*/
408 /*-----------------------------------------------------------------------------
409 * Function: initdram
410 * Description: Configures SDRAM memory banks for DDR operation.
411 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
412 * via the IIC bus and then configures the DDR SDRAM memory
413 * banks appropriately. If Auto Memory Configuration is
414 * not used, it is assumed that no DIMM is plugged
415 *-----------------------------------------------------------------------------*/
416 phys_size_t initdram(int board_type)
417 {
418 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
419 unsigned char spd0[MAX_SPD_BYTES];
420 unsigned char spd1[MAX_SPD_BYTES];
421 unsigned char *dimm_spd[MAXDIMMS];
422 unsigned long dimm_populated[MAXDIMMS];
423 unsigned long num_dimm_banks; /* on board dimm banks */
424 unsigned long val;
425 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
426 int write_recovery;
427 phys_size_t dram_size = 0;
428
429 num_dimm_banks = sizeof(iic0_dimm_addr);
430
431 /*------------------------------------------------------------------
432 * Set up an array of SPD matrixes.
433 *-----------------------------------------------------------------*/
434 dimm_spd[0] = spd0;
435 dimm_spd[1] = spd1;
436
437 /*------------------------------------------------------------------
438 * Reset the DDR-SDRAM controller.
439 *-----------------------------------------------------------------*/
440 mtsdr(SDR0_SRST, (0x80000000 >> 10));
441 mtsdr(SDR0_SRST, 0x00000000);
442
443 /*
444 * Make sure I2C controller is initialized
445 * before continuing.
446 */
447
448 /* switch to correct I2C bus */
449 I2C_SET_BUS(CFG_SPD_BUS_NUM);
450 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
451
452 /*------------------------------------------------------------------
453 * Clear out the serial presence detect buffers.
454 * Perform IIC reads from the dimm. Fill in the spds.
455 * Check to see if the dimm slots are populated
456 *-----------------------------------------------------------------*/
457 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
458
459 /*------------------------------------------------------------------
460 * Check the memory type for the dimms plugged.
461 *-----------------------------------------------------------------*/
462 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
463
464 /*------------------------------------------------------------------
465 * Check the frequency supported for the dimms plugged.
466 *-----------------------------------------------------------------*/
467 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
468
469 /*------------------------------------------------------------------
470 * Check the total rank number.
471 *-----------------------------------------------------------------*/
472 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
473
474 /*------------------------------------------------------------------
475 * Check the voltage type for the dimms plugged.
476 *-----------------------------------------------------------------*/
477 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
478
479 /*------------------------------------------------------------------
480 * Program SDRAM controller options 2 register
481 * Except Enabling of the memory controller.
482 *-----------------------------------------------------------------*/
483 mfsdram(SDRAM_MCOPT2, val);
484 mtsdram(SDRAM_MCOPT2,
485 (val &
486 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
487 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
488 SDRAM_MCOPT2_ISIE_MASK))
489 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
490 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
491 SDRAM_MCOPT2_ISIE_ENABLE));
492
493 /*------------------------------------------------------------------
494 * Program SDRAM controller options 1 register
495 * Note: Does not enable the memory controller.
496 *-----------------------------------------------------------------*/
497 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
498
499 /*------------------------------------------------------------------
500 * Set the SDRAM Controller On Die Termination Register
501 *-----------------------------------------------------------------*/
502 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
503
504 /*------------------------------------------------------------------
505 * Program SDRAM refresh register.
506 *-----------------------------------------------------------------*/
507 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
508
509 /*------------------------------------------------------------------
510 * Program SDRAM mode register.
511 *-----------------------------------------------------------------*/
512 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
513 &selected_cas, &write_recovery);
514
515 /*------------------------------------------------------------------
516 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
517 *-----------------------------------------------------------------*/
518 mfsdram(SDRAM_WRDTR, val);
519 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
520 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
521
522 /*------------------------------------------------------------------
523 * Set the SDRAM Clock Timing Register
524 *-----------------------------------------------------------------*/
525 mfsdram(SDRAM_CLKTR, val);
526 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
527 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
528
529 /*------------------------------------------------------------------
530 * Program the BxCF registers.
531 *-----------------------------------------------------------------*/
532 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
533
534 /*------------------------------------------------------------------
535 * Program SDRAM timing registers.
536 *-----------------------------------------------------------------*/
537 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
538
539 /*------------------------------------------------------------------
540 * Set the Extended Mode register
541 *-----------------------------------------------------------------*/
542 mfsdram(SDRAM_MEMODE, val);
543 mtsdram(SDRAM_MEMODE,
544 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
545 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
546 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
547 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
548
549 /*------------------------------------------------------------------
550 * Program Initialization preload registers.
551 *-----------------------------------------------------------------*/
552 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
553 selected_cas, write_recovery);
554
555 /*------------------------------------------------------------------
556 * Delay to ensure 200usec have elapsed since reset.
557 *-----------------------------------------------------------------*/
558 udelay(400);
559
560 /*------------------------------------------------------------------
561 * Set the memory queue core base addr.
562 *-----------------------------------------------------------------*/
563 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
564
565 /*------------------------------------------------------------------
566 * Program SDRAM controller options 2 register
567 * Enable the memory controller.
568 *-----------------------------------------------------------------*/
569 mfsdram(SDRAM_MCOPT2, val);
570 mtsdram(SDRAM_MCOPT2,
571 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
572 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
573 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
574
575 /*------------------------------------------------------------------
576 * Wait for SDRAM_CFG0_DC_EN to complete.
577 *-----------------------------------------------------------------*/
578 do {
579 mfsdram(SDRAM_MCSTAT, val);
580 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
581
582 /* get installed memory size */
583 dram_size = sdram_memsize();
584
585 /*
586 * Limit size to 2GB
587 */
588 if (dram_size > CONFIG_MAX_MEM_MAPPED)
589 dram_size = CONFIG_MAX_MEM_MAPPED;
590
591 /* and program tlb entries for this size (dynamic) */
592
593 /*
594 * Program TLB entries with caches enabled, for best performace
595 * while auto-calibrating and ECC generation
596 */
597 program_tlb(0, 0, dram_size, 0);
598
599 /*------------------------------------------------------------------
600 * DQS calibration.
601 *-----------------------------------------------------------------*/
602 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
603
604 #ifdef CONFIG_DDR_ECC
605 /*------------------------------------------------------------------
606 * If ecc is enabled, initialize the parity bits.
607 *-----------------------------------------------------------------*/
608 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
609 #endif
610
611 /*
612 * Now after initialization (auto-calibration and ECC generation)
613 * remove the TLB entries with caches enabled and program again with
614 * desired cache functionality
615 */
616 remove_tlb(0, dram_size);
617 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
618
619 ppc4xx_ibm_ddr2_register_dump();
620
621 /*
622 * Clear potential errors resulting from auto-calibration.
623 * If not done, then we could get an interrupt later on when
624 * exceptions are enabled.
625 */
626 set_mcsr(get_mcsr());
627
628 return sdram_memsize();
629 }
630
631 static void get_spd_info(unsigned long *dimm_populated,
632 unsigned char *iic0_dimm_addr,
633 unsigned long num_dimm_banks)
634 {
635 unsigned long dimm_num;
636 unsigned long dimm_found;
637 unsigned char num_of_bytes;
638 unsigned char total_size;
639
640 dimm_found = FALSE;
641 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
642 num_of_bytes = 0;
643 total_size = 0;
644
645 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
646 debug("\nspd_read(0x%x) returned %d\n",
647 iic0_dimm_addr[dimm_num], num_of_bytes);
648 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
649 debug("spd_read(0x%x) returned %d\n",
650 iic0_dimm_addr[dimm_num], total_size);
651
652 if ((num_of_bytes != 0) && (total_size != 0)) {
653 dimm_populated[dimm_num] = TRUE;
654 dimm_found = TRUE;
655 debug("DIMM slot %lu: populated\n", dimm_num);
656 } else {
657 dimm_populated[dimm_num] = FALSE;
658 debug("DIMM slot %lu: Not populated\n", dimm_num);
659 }
660 }
661
662 if (dimm_found == FALSE) {
663 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
664 spd_ddr_init_hang ();
665 }
666 }
667
668 void board_add_ram_info(int use_default)
669 {
670 PPC4xx_SYS_INFO board_cfg;
671 u32 val;
672
673 if (is_ecc_enabled())
674 puts(" (ECC");
675 else
676 puts(" (ECC not");
677
678 get_sys_info(&board_cfg);
679
680 mfsdr(SDR0_DDR0, val);
681 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
682 printf(" enabled, %d MHz", (val * 2) / 1000000);
683
684 mfsdram(SDRAM_MMODE, val);
685 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
686 printf(", CL%d)", val);
687 }
688
689 /*------------------------------------------------------------------
690 * For the memory DIMMs installed, this routine verifies that they
691 * really are DDR specific DIMMs.
692 *-----------------------------------------------------------------*/
693 static void check_mem_type(unsigned long *dimm_populated,
694 unsigned char *iic0_dimm_addr,
695 unsigned long num_dimm_banks)
696 {
697 unsigned long dimm_num;
698 unsigned long dimm_type;
699
700 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
701 if (dimm_populated[dimm_num] == TRUE) {
702 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
703 switch (dimm_type) {
704 case 1:
705 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
706 "slot %d.\n", (unsigned int)dimm_num);
707 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
708 printf("Replace the DIMM module with a supported DIMM.\n\n");
709 spd_ddr_init_hang ();
710 break;
711 case 2:
712 printf("ERROR: EDO DIMM detected in slot %d.\n",
713 (unsigned int)dimm_num);
714 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
715 printf("Replace the DIMM module with a supported DIMM.\n\n");
716 spd_ddr_init_hang ();
717 break;
718 case 3:
719 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
720 (unsigned int)dimm_num);
721 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
722 printf("Replace the DIMM module with a supported DIMM.\n\n");
723 spd_ddr_init_hang ();
724 break;
725 case 4:
726 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
727 (unsigned int)dimm_num);
728 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
729 printf("Replace the DIMM module with a supported DIMM.\n\n");
730 spd_ddr_init_hang ();
731 break;
732 case 5:
733 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
734 (unsigned int)dimm_num);
735 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
736 printf("Replace the DIMM module with a supported DIMM.\n\n");
737 spd_ddr_init_hang ();
738 break;
739 case 6:
740 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
741 (unsigned int)dimm_num);
742 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
743 printf("Replace the DIMM module with a supported DIMM.\n\n");
744 spd_ddr_init_hang ();
745 break;
746 case 7:
747 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
748 dimm_populated[dimm_num] = SDRAM_DDR1;
749 break;
750 case 8:
751 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
752 dimm_populated[dimm_num] = SDRAM_DDR2;
753 break;
754 default:
755 printf("ERROR: Unknown DIMM detected in slot %d.\n",
756 (unsigned int)dimm_num);
757 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
758 printf("Replace the DIMM module with a supported DIMM.\n\n");
759 spd_ddr_init_hang ();
760 break;
761 }
762 }
763 }
764 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
765 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
766 && (dimm_populated[dimm_num] != SDRAM_NONE)
767 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
768 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
769 spd_ddr_init_hang ();
770 }
771 }
772 }
773
774 /*------------------------------------------------------------------
775 * For the memory DIMMs installed, this routine verifies that
776 * frequency previously calculated is supported.
777 *-----------------------------------------------------------------*/
778 static void check_frequency(unsigned long *dimm_populated,
779 unsigned char *iic0_dimm_addr,
780 unsigned long num_dimm_banks)
781 {
782 unsigned long dimm_num;
783 unsigned long tcyc_reg;
784 unsigned long cycle_time;
785 unsigned long calc_cycle_time;
786 unsigned long sdram_freq;
787 unsigned long sdr_ddrpll;
788 PPC4xx_SYS_INFO board_cfg;
789
790 /*------------------------------------------------------------------
791 * Get the board configuration info.
792 *-----------------------------------------------------------------*/
793 get_sys_info(&board_cfg);
794
795 mfsdr(SDR0_DDR0, sdr_ddrpll);
796 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
797
798 /*
799 * calc_cycle_time is calculated from DDR frequency set by board/chip
800 * and is expressed in multiple of 10 picoseconds
801 * to match the way DIMM cycle time is calculated below.
802 */
803 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
804
805 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
806 if (dimm_populated[dimm_num] != SDRAM_NONE) {
807 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
808 /*
809 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
810 * the higher order nibble (bits 4-7) designates the cycle time
811 * to a granularity of 1ns;
812 * the value presented by the lower order nibble (bits 0-3)
813 * has a granularity of .1ns and is added to the value designated
814 * by the higher nibble. In addition, four lines of the lower order
815 * nibble are assigned to support +.25,+.33, +.66 and +.75.
816 */
817 /* Convert from hex to decimal */
818 if ((tcyc_reg & 0x0F) == 0x0D)
819 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
820 else if ((tcyc_reg & 0x0F) == 0x0C)
821 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
822 else if ((tcyc_reg & 0x0F) == 0x0B)
823 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
824 else if ((tcyc_reg & 0x0F) == 0x0A)
825 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
826 else
827 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
828 ((tcyc_reg & 0x0F)*10);
829 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
830
831 if (cycle_time > (calc_cycle_time + 10)) {
832 /*
833 * the provided sdram cycle_time is too small
834 * for the available DIMM cycle_time.
835 * The additionnal 100ps is here to accept a small incertainty.
836 */
837 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
838 "slot %d \n while calculated cycle time is %d ps.\n",
839 (unsigned int)(cycle_time*10),
840 (unsigned int)dimm_num,
841 (unsigned int)(calc_cycle_time*10));
842 printf("Replace the DIMM, or change DDR frequency via "
843 "strapping bits.\n\n");
844 spd_ddr_init_hang ();
845 }
846 }
847 }
848 }
849
850 /*------------------------------------------------------------------
851 * For the memory DIMMs installed, this routine verifies two
852 * ranks/banks maximum are availables.
853 *-----------------------------------------------------------------*/
854 static void check_rank_number(unsigned long *dimm_populated,
855 unsigned char *iic0_dimm_addr,
856 unsigned long num_dimm_banks)
857 {
858 unsigned long dimm_num;
859 unsigned long dimm_rank;
860 unsigned long total_rank = 0;
861
862 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
863 if (dimm_populated[dimm_num] != SDRAM_NONE) {
864 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
865 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
866 dimm_rank = (dimm_rank & 0x0F) +1;
867 else
868 dimm_rank = dimm_rank & 0x0F;
869
870
871 if (dimm_rank > MAXRANKS) {
872 printf("ERROR: DRAM DIMM detected with %lu ranks in "
873 "slot %lu is not supported.\n", dimm_rank, dimm_num);
874 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
875 printf("Replace the DIMM module with a supported DIMM.\n\n");
876 spd_ddr_init_hang ();
877 } else
878 total_rank += dimm_rank;
879 }
880 if (total_rank > MAXRANKS) {
881 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
882 "for all slots.\n", (unsigned int)total_rank);
883 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
884 printf("Remove one of the DIMM modules.\n\n");
885 spd_ddr_init_hang ();
886 }
887 }
888 }
889
890 /*------------------------------------------------------------------
891 * only support 2.5V modules.
892 * This routine verifies this.
893 *-----------------------------------------------------------------*/
894 static void check_voltage_type(unsigned long *dimm_populated,
895 unsigned char *iic0_dimm_addr,
896 unsigned long num_dimm_banks)
897 {
898 unsigned long dimm_num;
899 unsigned long voltage_type;
900
901 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
902 if (dimm_populated[dimm_num] != SDRAM_NONE) {
903 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
904 switch (voltage_type) {
905 case 0x00:
906 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
907 printf("This DIMM is 5.0 Volt/TTL.\n");
908 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
909 (unsigned int)dimm_num);
910 spd_ddr_init_hang ();
911 break;
912 case 0x01:
913 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
914 printf("This DIMM is LVTTL.\n");
915 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
916 (unsigned int)dimm_num);
917 spd_ddr_init_hang ();
918 break;
919 case 0x02:
920 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
921 printf("This DIMM is 1.5 Volt.\n");
922 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
923 (unsigned int)dimm_num);
924 spd_ddr_init_hang ();
925 break;
926 case 0x03:
927 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
928 printf("This DIMM is 3.3 Volt/TTL.\n");
929 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
930 (unsigned int)dimm_num);
931 spd_ddr_init_hang ();
932 break;
933 case 0x04:
934 /* 2.5 Voltage only for DDR1 */
935 break;
936 case 0x05:
937 /* 1.8 Voltage only for DDR2 */
938 break;
939 default:
940 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
941 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
942 (unsigned int)dimm_num);
943 spd_ddr_init_hang ();
944 break;
945 }
946 }
947 }
948 }
949
950 /*-----------------------------------------------------------------------------+
951 * program_copt1.
952 *-----------------------------------------------------------------------------*/
953 static void program_copt1(unsigned long *dimm_populated,
954 unsigned char *iic0_dimm_addr,
955 unsigned long num_dimm_banks)
956 {
957 unsigned long dimm_num;
958 unsigned long mcopt1;
959 unsigned long ecc_enabled;
960 unsigned long ecc = 0;
961 unsigned long data_width = 0;
962 unsigned long dimm_32bit;
963 unsigned long dimm_64bit;
964 unsigned long registered = 0;
965 unsigned long attribute = 0;
966 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
967 unsigned long bankcount;
968 unsigned long ddrtype;
969 unsigned long val;
970
971 #ifdef CONFIG_DDR_ECC
972 ecc_enabled = TRUE;
973 #else
974 ecc_enabled = FALSE;
975 #endif
976 dimm_32bit = FALSE;
977 dimm_64bit = FALSE;
978 buf0 = FALSE;
979 buf1 = FALSE;
980
981 /*------------------------------------------------------------------
982 * Set memory controller options reg 1, SDRAM_MCOPT1.
983 *-----------------------------------------------------------------*/
984 mfsdram(SDRAM_MCOPT1, val);
985 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
986 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
987 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
988 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
989 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
990 SDRAM_MCOPT1_DREF_MASK);
991
992 mcopt1 |= SDRAM_MCOPT1_QDEP;
993 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
994 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
995 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
996 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
997 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
998
999 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1000 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1001 /* test ecc support */
1002 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1003 if (ecc != 0x02) /* ecc not supported */
1004 ecc_enabled = FALSE;
1005
1006 /* test bank count */
1007 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1008 if (bankcount == 0x04) /* bank count = 4 */
1009 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1010 else /* bank count = 8 */
1011 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1012
1013 /* test DDR type */
1014 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1015 /* test for buffered/unbuffered, registered, differential clocks */
1016 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1017 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1018
1019 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1020 if (dimm_num == 0) {
1021 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1022 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1023 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1024 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1025 if (registered == 1) { /* DDR2 always buffered */
1026 /* TODO: what about above comments ? */
1027 mcopt1 |= SDRAM_MCOPT1_RDEN;
1028 buf0 = TRUE;
1029 } else {
1030 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1031 if ((attribute & 0x02) == 0x00) {
1032 /* buffered not supported */
1033 buf0 = FALSE;
1034 } else {
1035 mcopt1 |= SDRAM_MCOPT1_RDEN;
1036 buf0 = TRUE;
1037 }
1038 }
1039 }
1040 else if (dimm_num == 1) {
1041 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1042 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1043 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1044 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1045 if (registered == 1) {
1046 /* DDR2 always buffered */
1047 mcopt1 |= SDRAM_MCOPT1_RDEN;
1048 buf1 = TRUE;
1049 } else {
1050 if ((attribute & 0x02) == 0x00) {
1051 /* buffered not supported */
1052 buf1 = FALSE;
1053 } else {
1054 mcopt1 |= SDRAM_MCOPT1_RDEN;
1055 buf1 = TRUE;
1056 }
1057 }
1058 }
1059
1060 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1061 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1062 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1063
1064 switch (data_width) {
1065 case 72:
1066 case 64:
1067 dimm_64bit = TRUE;
1068 break;
1069 case 40:
1070 case 32:
1071 dimm_32bit = TRUE;
1072 break;
1073 default:
1074 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1075 data_width);
1076 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1077 break;
1078 }
1079 }
1080 }
1081
1082 /* verify matching properties */
1083 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1084 if (buf0 != buf1) {
1085 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1086 spd_ddr_init_hang ();
1087 }
1088 }
1089
1090 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1091 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1092 spd_ddr_init_hang ();
1093 }
1094 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1095 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1096 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1097 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1098 } else {
1099 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1100 spd_ddr_init_hang ();
1101 }
1102
1103 if (ecc_enabled == TRUE)
1104 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1105 else
1106 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1107
1108 mtsdram(SDRAM_MCOPT1, mcopt1);
1109 }
1110
1111 /*-----------------------------------------------------------------------------+
1112 * program_codt.
1113 *-----------------------------------------------------------------------------*/
1114 static void program_codt(unsigned long *dimm_populated,
1115 unsigned char *iic0_dimm_addr,
1116 unsigned long num_dimm_banks)
1117 {
1118 unsigned long codt;
1119 unsigned long modt0 = 0;
1120 unsigned long modt1 = 0;
1121 unsigned long modt2 = 0;
1122 unsigned long modt3 = 0;
1123 unsigned char dimm_num;
1124 unsigned char dimm_rank;
1125 unsigned char total_rank = 0;
1126 unsigned char total_dimm = 0;
1127 unsigned char dimm_type = 0;
1128 unsigned char firstSlot = 0;
1129
1130 /*------------------------------------------------------------------
1131 * Set the SDRAM Controller On Die Termination Register
1132 *-----------------------------------------------------------------*/
1133 mfsdram(SDRAM_CODT, codt);
1134 codt |= (SDRAM_CODT_IO_NMODE
1135 & (~SDRAM_CODT_DQS_SINGLE_END
1136 & ~SDRAM_CODT_CKSE_SINGLE_END
1137 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1138 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1139
1140 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1141 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1142 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1143 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1144 dimm_rank = (dimm_rank & 0x0F) + 1;
1145 dimm_type = SDRAM_DDR2;
1146 } else {
1147 dimm_rank = dimm_rank & 0x0F;
1148 dimm_type = SDRAM_DDR1;
1149 }
1150
1151 total_rank += dimm_rank;
1152 total_dimm++;
1153 if ((dimm_num == 0) && (total_dimm == 1))
1154 firstSlot = TRUE;
1155 else
1156 firstSlot = FALSE;
1157 }
1158 }
1159 if (dimm_type == SDRAM_DDR2) {
1160 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1161 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1162 if (total_rank == 1) {
1163 codt |= CALC_ODT_R(0);
1164 modt0 = CALC_ODT_W(0);
1165 modt1 = 0x00000000;
1166 modt2 = 0x00000000;
1167 modt3 = 0x00000000;
1168 }
1169 if (total_rank == 2) {
1170 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1171 modt0 = CALC_ODT_W(0);
1172 modt1 = CALC_ODT_W(0);
1173 modt2 = 0x00000000;
1174 modt3 = 0x00000000;
1175 }
1176 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1177 if (total_rank == 1) {
1178 codt |= CALC_ODT_R(2);
1179 modt0 = 0x00000000;
1180 modt1 = 0x00000000;
1181 modt2 = CALC_ODT_W(2);
1182 modt3 = 0x00000000;
1183 }
1184 if (total_rank == 2) {
1185 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1186 modt0 = 0x00000000;
1187 modt1 = 0x00000000;
1188 modt2 = CALC_ODT_W(2);
1189 modt3 = CALC_ODT_W(2);
1190 }
1191 }
1192 if (total_dimm == 2) {
1193 if (total_rank == 2) {
1194 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1195 modt0 = CALC_ODT_RW(2);
1196 modt1 = 0x00000000;
1197 modt2 = CALC_ODT_RW(0);
1198 modt3 = 0x00000000;
1199 }
1200 if (total_rank == 4) {
1201 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1202 CALC_ODT_R(2) | CALC_ODT_R(3);
1203 modt0 = CALC_ODT_RW(2);
1204 modt1 = 0x00000000;
1205 modt2 = CALC_ODT_RW(0);
1206 modt3 = 0x00000000;
1207 }
1208 }
1209 } else {
1210 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1211 modt0 = 0x00000000;
1212 modt1 = 0x00000000;
1213 modt2 = 0x00000000;
1214 modt3 = 0x00000000;
1215
1216 if (total_dimm == 1) {
1217 if (total_rank == 1)
1218 codt |= 0x00800000;
1219 if (total_rank == 2)
1220 codt |= 0x02800000;
1221 }
1222 if (total_dimm == 2) {
1223 if (total_rank == 2)
1224 codt |= 0x08800000;
1225 if (total_rank == 4)
1226 codt |= 0x2a800000;
1227 }
1228 }
1229
1230 debug("nb of dimm %d\n", total_dimm);
1231 debug("nb of rank %d\n", total_rank);
1232 if (total_dimm == 1)
1233 debug("dimm in slot %d\n", firstSlot);
1234
1235 mtsdram(SDRAM_CODT, codt);
1236 mtsdram(SDRAM_MODT0, modt0);
1237 mtsdram(SDRAM_MODT1, modt1);
1238 mtsdram(SDRAM_MODT2, modt2);
1239 mtsdram(SDRAM_MODT3, modt3);
1240 }
1241
1242 /*-----------------------------------------------------------------------------+
1243 * program_initplr.
1244 *-----------------------------------------------------------------------------*/
1245 static void program_initplr(unsigned long *dimm_populated,
1246 unsigned char *iic0_dimm_addr,
1247 unsigned long num_dimm_banks,
1248 ddr_cas_id_t selected_cas,
1249 int write_recovery)
1250 {
1251 u32 cas = 0;
1252 u32 odt = 0;
1253 u32 ods = 0;
1254 u32 mr;
1255 u32 wr;
1256 u32 emr;
1257 u32 emr2;
1258 u32 emr3;
1259 int dimm_num;
1260 int total_dimm = 0;
1261
1262 /******************************************************
1263 ** Assumption: if more than one DIMM, all DIMMs are the same
1264 ** as already checked in check_memory_type
1265 ******************************************************/
1266
1267 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1268 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1269 mtsdram(SDRAM_INITPLR1, 0x81900400);
1270 mtsdram(SDRAM_INITPLR2, 0x81810000);
1271 mtsdram(SDRAM_INITPLR3, 0xff800162);
1272 mtsdram(SDRAM_INITPLR4, 0x81900400);
1273 mtsdram(SDRAM_INITPLR5, 0x86080000);
1274 mtsdram(SDRAM_INITPLR6, 0x86080000);
1275 mtsdram(SDRAM_INITPLR7, 0x81000062);
1276 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1277 switch (selected_cas) {
1278 case DDR_CAS_3:
1279 cas = 3 << 4;
1280 break;
1281 case DDR_CAS_4:
1282 cas = 4 << 4;
1283 break;
1284 case DDR_CAS_5:
1285 cas = 5 << 4;
1286 break;
1287 default:
1288 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1289 spd_ddr_init_hang ();
1290 break;
1291 }
1292
1293 #if 0
1294 /*
1295 * ToDo - Still a problem with the write recovery:
1296 * On the Corsair CM2X512-5400C4 module, setting write recovery
1297 * in the INITPLR reg to the value calculated in program_mode()
1298 * results in not correctly working DDR2 memory (crash after
1299 * relocation).
1300 *
1301 * So for now, set the write recovery to 3. This seems to work
1302 * on the Corair module too.
1303 *
1304 * 2007-03-01, sr
1305 */
1306 switch (write_recovery) {
1307 case 3:
1308 wr = WRITE_RECOV_3;
1309 break;
1310 case 4:
1311 wr = WRITE_RECOV_4;
1312 break;
1313 case 5:
1314 wr = WRITE_RECOV_5;
1315 break;
1316 case 6:
1317 wr = WRITE_RECOV_6;
1318 break;
1319 default:
1320 printf("ERROR: write recovery not support (%d)", write_recovery);
1321 spd_ddr_init_hang ();
1322 break;
1323 }
1324 #else
1325 wr = WRITE_RECOV_3; /* test-only, see description above */
1326 #endif
1327
1328 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1329 if (dimm_populated[dimm_num] != SDRAM_NONE)
1330 total_dimm++;
1331 if (total_dimm == 1) {
1332 odt = ODT_150_OHM;
1333 ods = ODS_FULL;
1334 } else if (total_dimm == 2) {
1335 odt = ODT_75_OHM;
1336 ods = ODS_REDUCED;
1337 } else {
1338 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1339 spd_ddr_init_hang ();
1340 }
1341
1342 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1343 emr = CMD_EMR | SELECT_EMR | odt | ods;
1344 emr2 = CMD_EMR | SELECT_EMR2;
1345 emr3 = CMD_EMR | SELECT_EMR3;
1346 mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
1347 udelay(1000);
1348 mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1349 mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
1350 mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
1351 mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
1352 mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
1353 udelay(1000);
1354 mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1355 mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1356 mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1357 mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1358 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1359 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
1360 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
1361 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
1362 } else {
1363 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1364 spd_ddr_init_hang ();
1365 }
1366 }
1367
1368 /*------------------------------------------------------------------
1369 * This routine programs the SDRAM_MMODE register.
1370 * the selected_cas is an output parameter, that will be passed
1371 * by caller to call the above program_initplr( )
1372 *-----------------------------------------------------------------*/
1373 static void program_mode(unsigned long *dimm_populated,
1374 unsigned char *iic0_dimm_addr,
1375 unsigned long num_dimm_banks,
1376 ddr_cas_id_t *selected_cas,
1377 int *write_recovery)
1378 {
1379 unsigned long dimm_num;
1380 unsigned long sdram_ddr1;
1381 unsigned long t_wr_ns;
1382 unsigned long t_wr_clk;
1383 unsigned long cas_bit;
1384 unsigned long cas_index;
1385 unsigned long sdram_freq;
1386 unsigned long ddr_check;
1387 unsigned long mmode;
1388 unsigned long tcyc_reg;
1389 unsigned long cycle_2_0_clk;
1390 unsigned long cycle_2_5_clk;
1391 unsigned long cycle_3_0_clk;
1392 unsigned long cycle_4_0_clk;
1393 unsigned long cycle_5_0_clk;
1394 unsigned long max_2_0_tcyc_ns_x_100;
1395 unsigned long max_2_5_tcyc_ns_x_100;
1396 unsigned long max_3_0_tcyc_ns_x_100;
1397 unsigned long max_4_0_tcyc_ns_x_100;
1398 unsigned long max_5_0_tcyc_ns_x_100;
1399 unsigned long cycle_time_ns_x_100[3];
1400 PPC4xx_SYS_INFO board_cfg;
1401 unsigned char cas_2_0_available;
1402 unsigned char cas_2_5_available;
1403 unsigned char cas_3_0_available;
1404 unsigned char cas_4_0_available;
1405 unsigned char cas_5_0_available;
1406 unsigned long sdr_ddrpll;
1407
1408 /*------------------------------------------------------------------
1409 * Get the board configuration info.
1410 *-----------------------------------------------------------------*/
1411 get_sys_info(&board_cfg);
1412
1413 mfsdr(SDR0_DDR0, sdr_ddrpll);
1414 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1415 debug("sdram_freq=%d\n", sdram_freq);
1416
1417 /*------------------------------------------------------------------
1418 * Handle the timing. We need to find the worst case timing of all
1419 * the dimm modules installed.
1420 *-----------------------------------------------------------------*/
1421 t_wr_ns = 0;
1422 cas_2_0_available = TRUE;
1423 cas_2_5_available = TRUE;
1424 cas_3_0_available = TRUE;
1425 cas_4_0_available = TRUE;
1426 cas_5_0_available = TRUE;
1427 max_2_0_tcyc_ns_x_100 = 10;
1428 max_2_5_tcyc_ns_x_100 = 10;
1429 max_3_0_tcyc_ns_x_100 = 10;
1430 max_4_0_tcyc_ns_x_100 = 10;
1431 max_5_0_tcyc_ns_x_100 = 10;
1432 sdram_ddr1 = TRUE;
1433
1434 /* loop through all the DIMM slots on the board */
1435 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1436 /* If a dimm is installed in a particular slot ... */
1437 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1438 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1439 sdram_ddr1 = TRUE;
1440 else
1441 sdram_ddr1 = FALSE;
1442
1443 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1444 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1445 debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1446
1447 /* For a particular DIMM, grab the three CAS values it supports */
1448 for (cas_index = 0; cas_index < 3; cas_index++) {
1449 switch (cas_index) {
1450 case 0:
1451 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1452 break;
1453 case 1:
1454 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1455 break;
1456 default:
1457 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1458 break;
1459 }
1460
1461 if ((tcyc_reg & 0x0F) >= 10) {
1462 if ((tcyc_reg & 0x0F) == 0x0D) {
1463 /* Convert from hex to decimal */
1464 cycle_time_ns_x_100[cas_index] =
1465 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1466 } else {
1467 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1468 "in slot %d\n", (unsigned int)dimm_num);
1469 spd_ddr_init_hang ();
1470 }
1471 } else {
1472 /* Convert from hex to decimal */
1473 cycle_time_ns_x_100[cas_index] =
1474 (((tcyc_reg & 0xF0) >> 4) * 100) +
1475 ((tcyc_reg & 0x0F)*10);
1476 }
1477 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1478 cycle_time_ns_x_100[cas_index]);
1479 }
1480
1481 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1482 /* supported for a particular DIMM. */
1483 cas_index = 0;
1484
1485 if (sdram_ddr1) {
1486 /*
1487 * DDR devices use the following bitmask for CAS latency:
1488 * Bit 7 6 5 4 3 2 1 0
1489 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1490 */
1491 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1492 (cycle_time_ns_x_100[cas_index] != 0)) {
1493 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1494 cycle_time_ns_x_100[cas_index]);
1495 cas_index++;
1496 } else {
1497 if (cas_index != 0)
1498 cas_index++;
1499 cas_4_0_available = FALSE;
1500 }
1501
1502 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1503 (cycle_time_ns_x_100[cas_index] != 0)) {
1504 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1505 cycle_time_ns_x_100[cas_index]);
1506 cas_index++;
1507 } else {
1508 if (cas_index != 0)
1509 cas_index++;
1510 cas_3_0_available = FALSE;
1511 }
1512
1513 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1514 (cycle_time_ns_x_100[cas_index] != 0)) {
1515 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1516 cycle_time_ns_x_100[cas_index]);
1517 cas_index++;
1518 } else {
1519 if (cas_index != 0)
1520 cas_index++;
1521 cas_2_5_available = FALSE;
1522 }
1523
1524 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1525 (cycle_time_ns_x_100[cas_index] != 0)) {
1526 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1527 cycle_time_ns_x_100[cas_index]);
1528 cas_index++;
1529 } else {
1530 if (cas_index != 0)
1531 cas_index++;
1532 cas_2_0_available = FALSE;
1533 }
1534 } else {
1535 /*
1536 * DDR2 devices use the following bitmask for CAS latency:
1537 * Bit 7 6 5 4 3 2 1 0
1538 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1539 */
1540 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1541 (cycle_time_ns_x_100[cas_index] != 0)) {
1542 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1543 cycle_time_ns_x_100[cas_index]);
1544 cas_index++;
1545 } else {
1546 if (cas_index != 0)
1547 cas_index++;
1548 cas_5_0_available = FALSE;
1549 }
1550
1551 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1552 (cycle_time_ns_x_100[cas_index] != 0)) {
1553 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1554 cycle_time_ns_x_100[cas_index]);
1555 cas_index++;
1556 } else {
1557 if (cas_index != 0)
1558 cas_index++;
1559 cas_4_0_available = FALSE;
1560 }
1561
1562 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1563 (cycle_time_ns_x_100[cas_index] != 0)) {
1564 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1565 cycle_time_ns_x_100[cas_index]);
1566 cas_index++;
1567 } else {
1568 if (cas_index != 0)
1569 cas_index++;
1570 cas_3_0_available = FALSE;
1571 }
1572 }
1573 }
1574 }
1575
1576 /*------------------------------------------------------------------
1577 * Set the SDRAM mode, SDRAM_MMODE
1578 *-----------------------------------------------------------------*/
1579 mfsdram(SDRAM_MMODE, mmode);
1580 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1581
1582 /* add 10 here because of rounding problems */
1583 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1584 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1585 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1586 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1587 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1588 debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1589 debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1590 debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1591
1592 if (sdram_ddr1 == TRUE) { /* DDR1 */
1593 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1594 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1595 *selected_cas = DDR_CAS_2;
1596 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1597 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1598 *selected_cas = DDR_CAS_2_5;
1599 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1600 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1601 *selected_cas = DDR_CAS_3;
1602 } else {
1603 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1604 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1605 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1606 spd_ddr_init_hang ();
1607 }
1608 } else { /* DDR2 */
1609 debug("cas_3_0_available=%d\n", cas_3_0_available);
1610 debug("cas_4_0_available=%d\n", cas_4_0_available);
1611 debug("cas_5_0_available=%d\n", cas_5_0_available);
1612 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1613 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1614 *selected_cas = DDR_CAS_3;
1615 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1616 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1617 *selected_cas = DDR_CAS_4;
1618 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1619 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1620 *selected_cas = DDR_CAS_5;
1621 } else {
1622 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1623 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1624 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1625 printf("cas3=%d cas4=%d cas5=%d\n",
1626 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1627 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1628 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1629 spd_ddr_init_hang ();
1630 }
1631 }
1632
1633 if (sdram_ddr1 == TRUE)
1634 mmode |= SDRAM_MMODE_WR_DDR1;
1635 else {
1636
1637 /* loop through all the DIMM slots on the board */
1638 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1639 /* If a dimm is installed in a particular slot ... */
1640 if (dimm_populated[dimm_num] != SDRAM_NONE)
1641 t_wr_ns = max(t_wr_ns,
1642 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1643 }
1644
1645 /*
1646 * convert from nanoseconds to ddr clocks
1647 * round up if necessary
1648 */
1649 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1650 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1651 if (sdram_freq != ddr_check)
1652 t_wr_clk++;
1653
1654 switch (t_wr_clk) {
1655 case 0:
1656 case 1:
1657 case 2:
1658 case 3:
1659 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1660 break;
1661 case 4:
1662 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1663 break;
1664 case 5:
1665 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1666 break;
1667 default:
1668 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1669 break;
1670 }
1671 *write_recovery = t_wr_clk;
1672 }
1673
1674 debug("CAS latency = %d\n", *selected_cas);
1675 debug("Write recovery = %d\n", *write_recovery);
1676
1677 mtsdram(SDRAM_MMODE, mmode);
1678 }
1679
1680 /*-----------------------------------------------------------------------------+
1681 * program_rtr.
1682 *-----------------------------------------------------------------------------*/
1683 static void program_rtr(unsigned long *dimm_populated,
1684 unsigned char *iic0_dimm_addr,
1685 unsigned long num_dimm_banks)
1686 {
1687 PPC4xx_SYS_INFO board_cfg;
1688 unsigned long max_refresh_rate;
1689 unsigned long dimm_num;
1690 unsigned long refresh_rate_type;
1691 unsigned long refresh_rate;
1692 unsigned long rint;
1693 unsigned long sdram_freq;
1694 unsigned long sdr_ddrpll;
1695 unsigned long val;
1696
1697 /*------------------------------------------------------------------
1698 * Get the board configuration info.
1699 *-----------------------------------------------------------------*/
1700 get_sys_info(&board_cfg);
1701
1702 /*------------------------------------------------------------------
1703 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1704 *-----------------------------------------------------------------*/
1705 mfsdr(SDR0_DDR0, sdr_ddrpll);
1706 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1707
1708 max_refresh_rate = 0;
1709 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1710 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1711
1712 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1713 refresh_rate_type &= 0x7F;
1714 switch (refresh_rate_type) {
1715 case 0:
1716 refresh_rate = 15625;
1717 break;
1718 case 1:
1719 refresh_rate = 3906;
1720 break;
1721 case 2:
1722 refresh_rate = 7812;
1723 break;
1724 case 3:
1725 refresh_rate = 31250;
1726 break;
1727 case 4:
1728 refresh_rate = 62500;
1729 break;
1730 case 5:
1731 refresh_rate = 125000;
1732 break;
1733 default:
1734 refresh_rate = 0;
1735 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1736 (unsigned int)dimm_num);
1737 printf("Replace the DIMM module with a supported DIMM.\n\n");
1738 spd_ddr_init_hang ();
1739 break;
1740 }
1741
1742 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1743 }
1744 }
1745
1746 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1747 mfsdram(SDRAM_RTR, val);
1748 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1749 (SDRAM_RTR_RINT_ENCODE(rint)));
1750 }
1751
1752 /*------------------------------------------------------------------
1753 * This routine programs the SDRAM_TRx registers.
1754 *-----------------------------------------------------------------*/
1755 static void program_tr(unsigned long *dimm_populated,
1756 unsigned char *iic0_dimm_addr,
1757 unsigned long num_dimm_banks)
1758 {
1759 unsigned long dimm_num;
1760 unsigned long sdram_ddr1;
1761 unsigned long t_rp_ns;
1762 unsigned long t_rcd_ns;
1763 unsigned long t_rrd_ns;
1764 unsigned long t_ras_ns;
1765 unsigned long t_rc_ns;
1766 unsigned long t_rfc_ns;
1767 unsigned long t_wpc_ns;
1768 unsigned long t_wtr_ns;
1769 unsigned long t_rpc_ns;
1770 unsigned long t_rp_clk;
1771 unsigned long t_rcd_clk;
1772 unsigned long t_rrd_clk;
1773 unsigned long t_ras_clk;
1774 unsigned long t_rc_clk;
1775 unsigned long t_rfc_clk;
1776 unsigned long t_wpc_clk;
1777 unsigned long t_wtr_clk;
1778 unsigned long t_rpc_clk;
1779 unsigned long sdtr1, sdtr2, sdtr3;
1780 unsigned long ddr_check;
1781 unsigned long sdram_freq;
1782 unsigned long sdr_ddrpll;
1783
1784 PPC4xx_SYS_INFO board_cfg;
1785
1786 /*------------------------------------------------------------------
1787 * Get the board configuration info.
1788 *-----------------------------------------------------------------*/
1789 get_sys_info(&board_cfg);
1790
1791 mfsdr(SDR0_DDR0, sdr_ddrpll);
1792 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1793
1794 /*------------------------------------------------------------------
1795 * Handle the timing. We need to find the worst case timing of all
1796 * the dimm modules installed.
1797 *-----------------------------------------------------------------*/
1798 t_rp_ns = 0;
1799 t_rrd_ns = 0;
1800 t_rcd_ns = 0;
1801 t_ras_ns = 0;
1802 t_rc_ns = 0;
1803 t_rfc_ns = 0;
1804 t_wpc_ns = 0;
1805 t_wtr_ns = 0;
1806 t_rpc_ns = 0;
1807 sdram_ddr1 = TRUE;
1808
1809 /* loop through all the DIMM slots on the board */
1810 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1811 /* If a dimm is installed in a particular slot ... */
1812 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1813 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1814 sdram_ddr1 = TRUE;
1815 else
1816 sdram_ddr1 = FALSE;
1817
1818 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1819 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1820 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1821 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1822 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1823 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1824 }
1825 }
1826
1827 /*------------------------------------------------------------------
1828 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1829 *-----------------------------------------------------------------*/
1830 mfsdram(SDRAM_SDTR1, sdtr1);
1831 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1832 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1833
1834 /* default values */
1835 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1836 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1837
1838 /* normal operations */
1839 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1840 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1841
1842 mtsdram(SDRAM_SDTR1, sdtr1);
1843
1844 /*------------------------------------------------------------------
1845 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1846 *-----------------------------------------------------------------*/
1847 mfsdram(SDRAM_SDTR2, sdtr2);
1848 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1849 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1850 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1851 SDRAM_SDTR2_RRD_MASK);
1852
1853 /*
1854 * convert t_rcd from nanoseconds to ddr clocks
1855 * round up if necessary
1856 */
1857 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1858 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1859 if (sdram_freq != ddr_check)
1860 t_rcd_clk++;
1861
1862 switch (t_rcd_clk) {
1863 case 0:
1864 case 1:
1865 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1866 break;
1867 case 2:
1868 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1869 break;
1870 case 3:
1871 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1872 break;
1873 case 4:
1874 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1875 break;
1876 default:
1877 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1878 break;
1879 }
1880
1881 if (sdram_ddr1 == TRUE) { /* DDR1 */
1882 if (sdram_freq < 200000000) {
1883 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1884 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1885 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1886 } else {
1887 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1888 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1889 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1890 }
1891 } else { /* DDR2 */
1892 /* loop through all the DIMM slots on the board */
1893 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1894 /* If a dimm is installed in a particular slot ... */
1895 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1896 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1897 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1898 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1899 }
1900 }
1901
1902 /*
1903 * convert from nanoseconds to ddr clocks
1904 * round up if necessary
1905 */
1906 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1907 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1908 if (sdram_freq != ddr_check)
1909 t_wpc_clk++;
1910
1911 switch (t_wpc_clk) {
1912 case 0:
1913 case 1:
1914 case 2:
1915 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1916 break;
1917 case 3:
1918 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1919 break;
1920 case 4:
1921 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1922 break;
1923 case 5:
1924 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1925 break;
1926 default:
1927 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1928 break;
1929 }
1930
1931 /*
1932 * convert from nanoseconds to ddr clocks
1933 * round up if necessary
1934 */
1935 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1936 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1937 if (sdram_freq != ddr_check)
1938 t_wtr_clk++;
1939
1940 switch (t_wtr_clk) {
1941 case 0:
1942 case 1:
1943 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1944 break;
1945 case 2:
1946 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1947 break;
1948 case 3:
1949 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1950 break;
1951 default:
1952 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1953 break;
1954 }
1955
1956 /*
1957 * convert from nanoseconds to ddr clocks
1958 * round up if necessary
1959 */
1960 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1961 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1962 if (sdram_freq != ddr_check)
1963 t_rpc_clk++;
1964
1965 switch (t_rpc_clk) {
1966 case 0:
1967 case 1:
1968 case 2:
1969 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1970 break;
1971 case 3:
1972 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1973 break;
1974 default:
1975 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1976 break;
1977 }
1978 }
1979
1980 /* default value */
1981 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1982
1983 /*
1984 * convert t_rrd from nanoseconds to ddr clocks
1985 * round up if necessary
1986 */
1987 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1988 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1989 if (sdram_freq != ddr_check)
1990 t_rrd_clk++;
1991
1992 if (t_rrd_clk == 3)
1993 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1994 else
1995 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1996
1997 /*
1998 * convert t_rp from nanoseconds to ddr clocks
1999 * round up if necessary
2000 */
2001 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2002 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2003 if (sdram_freq != ddr_check)
2004 t_rp_clk++;
2005
2006 switch (t_rp_clk) {
2007 case 0:
2008 case 1:
2009 case 2:
2010 case 3:
2011 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2012 break;
2013 case 4:
2014 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2015 break;
2016 case 5:
2017 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2018 break;
2019 case 6:
2020 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2021 break;
2022 default:
2023 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2024 break;
2025 }
2026
2027 mtsdram(SDRAM_SDTR2, sdtr2);
2028
2029 /*------------------------------------------------------------------
2030 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2031 *-----------------------------------------------------------------*/
2032 mfsdram(SDRAM_SDTR3, sdtr3);
2033 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2034 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2035
2036 /*
2037 * convert t_ras from nanoseconds to ddr clocks
2038 * round up if necessary
2039 */
2040 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2041 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2042 if (sdram_freq != ddr_check)
2043 t_ras_clk++;
2044
2045 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2046
2047 /*
2048 * convert t_rc from nanoseconds to ddr clocks
2049 * round up if necessary
2050 */
2051 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2052 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2053 if (sdram_freq != ddr_check)
2054 t_rc_clk++;
2055
2056 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2057
2058 /* default xcs value */
2059 sdtr3 |= SDRAM_SDTR3_XCS;
2060
2061 /*
2062 * convert t_rfc from nanoseconds to ddr clocks
2063 * round up if necessary
2064 */
2065 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2066 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2067 if (sdram_freq != ddr_check)
2068 t_rfc_clk++;
2069
2070 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2071
2072 mtsdram(SDRAM_SDTR3, sdtr3);
2073 }
2074
2075 /*-----------------------------------------------------------------------------+
2076 * program_bxcf.
2077 *-----------------------------------------------------------------------------*/
2078 static void program_bxcf(unsigned long *dimm_populated,
2079 unsigned char *iic0_dimm_addr,
2080 unsigned long num_dimm_banks)
2081 {
2082 unsigned long dimm_num;
2083 unsigned long num_col_addr;
2084 unsigned long num_ranks;
2085 unsigned long num_banks;
2086 unsigned long mode;
2087 unsigned long ind_rank;
2088 unsigned long ind;
2089 unsigned long ind_bank;
2090 unsigned long bank_0_populated;
2091
2092 /*------------------------------------------------------------------
2093 * Set the BxCF regs. First, wipe out the bank config registers.
2094 *-----------------------------------------------------------------*/
2095 mtsdram(SDRAM_MB0CF, 0x00000000);
2096 mtsdram(SDRAM_MB1CF, 0x00000000);
2097 mtsdram(SDRAM_MB2CF, 0x00000000);
2098 mtsdram(SDRAM_MB3CF, 0x00000000);
2099
2100 mode = SDRAM_BXCF_M_BE_ENABLE;
2101
2102 bank_0_populated = 0;
2103
2104 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2105 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2106 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2107 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2108 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2109 num_ranks = (num_ranks & 0x0F) +1;
2110 else
2111 num_ranks = num_ranks & 0x0F;
2112
2113 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2114
2115 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2116 if (num_banks == 4)
2117 ind = 0;
2118 else
2119 ind = 5 << 8;
2120 switch (num_col_addr) {
2121 case 0x08:
2122 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2123 break;
2124 case 0x09:
2125 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2126 break;
2127 case 0x0A:
2128 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2129 break;
2130 case 0x0B:
2131 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2132 break;
2133 case 0x0C:
2134 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2135 break;
2136 default:
2137 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2138 (unsigned int)dimm_num);
2139 printf("ERROR: Unsupported value for number of "
2140 "column addresses: %d.\n", (unsigned int)num_col_addr);
2141 printf("Replace the DIMM module with a supported DIMM.\n\n");
2142 spd_ddr_init_hang ();
2143 }
2144 }
2145
2146 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2147 bank_0_populated = 1;
2148
2149 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2150 mtsdram(SDRAM_MB0CF +
2151 ((dimm_num + bank_0_populated + ind_rank) << 2),
2152 mode);
2153 }
2154 }
2155 }
2156 }
2157
2158 /*------------------------------------------------------------------
2159 * program memory queue.
2160 *-----------------------------------------------------------------*/
2161 static void program_memory_queue(unsigned long *dimm_populated,
2162 unsigned char *iic0_dimm_addr,
2163 unsigned long num_dimm_banks)
2164 {
2165 unsigned long dimm_num;
2166 phys_size_t rank_base_addr;
2167 unsigned long rank_reg;
2168 phys_size_t rank_size_bytes;
2169 unsigned long rank_size_id;
2170 unsigned long num_ranks;
2171 unsigned long baseadd_size;
2172 unsigned long i;
2173 unsigned long bank_0_populated = 0;
2174 phys_size_t total_size = 0;
2175
2176 /*------------------------------------------------------------------
2177 * Reset the rank_base_address.
2178 *-----------------------------------------------------------------*/
2179 rank_reg = SDRAM_R0BAS;
2180
2181 rank_base_addr = 0x00000000;
2182
2183 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2184 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2185 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2186 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2187 num_ranks = (num_ranks & 0x0F) + 1;
2188 else
2189 num_ranks = num_ranks & 0x0F;
2190
2191 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2192
2193 /*------------------------------------------------------------------
2194 * Set the sizes
2195 *-----------------------------------------------------------------*/
2196 baseadd_size = 0;
2197 switch (rank_size_id) {
2198 case 0x01:
2199 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2200 total_size = 1024;
2201 break;
2202 case 0x02:
2203 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2204 total_size = 2048;
2205 break;
2206 case 0x04:
2207 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2208 total_size = 4096;
2209 break;
2210 case 0x08:
2211 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2212 total_size = 32;
2213 break;
2214 case 0x10:
2215 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2216 total_size = 64;
2217 break;
2218 case 0x20:
2219 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2220 total_size = 128;
2221 break;
2222 case 0x40:
2223 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2224 total_size = 256;
2225 break;
2226 case 0x80:
2227 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2228 total_size = 512;
2229 break;
2230 default:
2231 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2232 (unsigned int)dimm_num);
2233 printf("ERROR: Unsupported value for the banksize: %d.\n",
2234 (unsigned int)rank_size_id);
2235 printf("Replace the DIMM module with a supported DIMM.\n\n");
2236 spd_ddr_init_hang ();
2237 }
2238 rank_size_bytes = total_size << 20;
2239
2240 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2241 bank_0_populated = 1;
2242
2243 for (i = 0; i < num_ranks; i++) {
2244 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2245 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2246 baseadd_size));
2247 rank_base_addr += rank_size_bytes;
2248 }
2249 }
2250 }
2251
2252 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
2253 /*
2254 * Enable high bandwidth access on 460EX/GT.
2255 * This should/could probably be done on other
2256 * PPC's too, like 440SPe.
2257 * This is currently not used, but with this setup
2258 * it is possible to use it later on in e.g. the Linux
2259 * EMAC driver for performance gain.
2260 */
2261 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2262 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2263 #endif
2264 }
2265
2266 /*-----------------------------------------------------------------------------+
2267 * is_ecc_enabled.
2268 *-----------------------------------------------------------------------------*/
2269 static unsigned long is_ecc_enabled(void)
2270 {
2271 unsigned long dimm_num;
2272 unsigned long ecc;
2273 unsigned long val;
2274
2275 ecc = 0;
2276 /* loop through all the DIMM slots on the board */
2277 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2278 mfsdram(SDRAM_MCOPT1, val);
2279 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2280 }
2281
2282 return ecc;
2283 }
2284
2285 static void blank_string(int size)
2286 {
2287 int i;
2288
2289 for (i=0; i<size; i++)
2290 putc('\b');
2291 for (i=0; i<size; i++)
2292 putc(' ');
2293 for (i=0; i<size; i++)
2294 putc('\b');
2295 }
2296
2297 #ifdef CONFIG_DDR_ECC
2298 /*-----------------------------------------------------------------------------+
2299 * program_ecc.
2300 *-----------------------------------------------------------------------------*/
2301 static void program_ecc(unsigned long *dimm_populated,
2302 unsigned char *iic0_dimm_addr,
2303 unsigned long num_dimm_banks,
2304 unsigned long tlb_word2_i_value)
2305 {
2306 unsigned long mcopt1;
2307 unsigned long mcopt2;
2308 unsigned long mcstat;
2309 unsigned long dimm_num;
2310 unsigned long ecc;
2311
2312 ecc = 0;
2313 /* loop through all the DIMM slots on the board */
2314 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2315 /* If a dimm is installed in a particular slot ... */
2316 if (dimm_populated[dimm_num] != SDRAM_NONE)
2317 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2318 }
2319 if (ecc == 0)
2320 return;
2321
2322 if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2323 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2324 return;
2325 }
2326
2327 mfsdram(SDRAM_MCOPT1, mcopt1);
2328 mfsdram(SDRAM_MCOPT2, mcopt2);
2329
2330 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2331 /* DDR controller must be enabled and not in self-refresh. */
2332 mfsdram(SDRAM_MCSTAT, mcstat);
2333 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2334 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2335 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2336 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2337
2338 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2339 }
2340 }
2341
2342 return;
2343 }
2344
2345 static void wait_ddr_idle(void)
2346 {
2347 u32 val;
2348
2349 do {
2350 mfsdram(SDRAM_MCSTAT, val);
2351 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2352 }
2353
2354 /*-----------------------------------------------------------------------------+
2355 * program_ecc_addr.
2356 *-----------------------------------------------------------------------------*/
2357 static void program_ecc_addr(unsigned long start_address,
2358 unsigned long num_bytes,
2359 unsigned long tlb_word2_i_value)
2360 {
2361 unsigned long current_address;
2362 unsigned long end_address;
2363 unsigned long address_increment;
2364 unsigned long mcopt1;
2365 char str[] = "ECC generation -";
2366 char slash[] = "\\|/-\\|/-";
2367 int loop = 0;
2368 int loopi = 0;
2369
2370 current_address = start_address;
2371 mfsdram(SDRAM_MCOPT1, mcopt1);
2372 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2373 mtsdram(SDRAM_MCOPT1,
2374 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2375 sync();
2376 eieio();
2377 wait_ddr_idle();
2378
2379 puts(str);
2380 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2381 /* ECC bit set method for non-cached memory */
2382 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2383 address_increment = 4;
2384 else
2385 address_increment = 8;
2386 end_address = current_address + num_bytes;
2387
2388 while (current_address < end_address) {
2389 *((unsigned long *)current_address) = 0x00000000;
2390 current_address += address_increment;
2391
2392 if ((loop++ % (2 << 20)) == 0) {
2393 putc('\b');
2394 putc(slash[loopi++ % 8]);
2395 }
2396 }
2397
2398 } else {
2399 /* ECC bit set method for cached memory */
2400 dcbz_area(start_address, num_bytes);
2401 /* Write modified dcache lines back to memory */
2402 clean_dcache_range(start_address, start_address + num_bytes);
2403 }
2404
2405 blank_string(strlen(str));
2406
2407 sync();
2408 eieio();
2409 wait_ddr_idle();
2410
2411 /* clear ECC error repoting registers */
2412 mtsdram(SDRAM_ECCCR, 0xffffffff);
2413 mtdcr(0x4c, 0xffffffff);
2414
2415 mtsdram(SDRAM_MCOPT1,
2416 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2417 sync();
2418 eieio();
2419 wait_ddr_idle();
2420 }
2421 }
2422 #endif
2423
2424 /*-----------------------------------------------------------------------------+
2425 * program_DQS_calibration.
2426 *-----------------------------------------------------------------------------*/
2427 static void program_DQS_calibration(unsigned long *dimm_populated,
2428 unsigned char *iic0_dimm_addr,
2429 unsigned long num_dimm_banks)
2430 {
2431 unsigned long val;
2432
2433 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2434 mtsdram(SDRAM_RQDC, 0x80000037);
2435 mtsdram(SDRAM_RDCC, 0x40000000);
2436 mtsdram(SDRAM_RFDC, 0x000001DF);
2437
2438 test();
2439 #else
2440 /*------------------------------------------------------------------
2441 * Program RDCC register
2442 * Read sample cycle auto-update enable
2443 *-----------------------------------------------------------------*/
2444
2445 mfsdram(SDRAM_RDCC, val);
2446 mtsdram(SDRAM_RDCC,
2447 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2448 | SDRAM_RDCC_RSAE_ENABLE);
2449
2450 /*------------------------------------------------------------------
2451 * Program RQDC register
2452 * Internal DQS delay mechanism enable
2453 *-----------------------------------------------------------------*/
2454 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2455
2456 /*------------------------------------------------------------------
2457 * Program RFDC register
2458 * Set Feedback Fractional Oversample
2459 * Auto-detect read sample cycle enable
2460 *-----------------------------------------------------------------*/
2461 mfsdram(SDRAM_RFDC, val);
2462 mtsdram(SDRAM_RFDC,
2463 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2464 SDRAM_RFDC_RFFD_MASK))
2465 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2466 SDRAM_RFDC_RFFD_ENCODE(0)));
2467
2468 DQS_calibration_process();
2469 #endif
2470 }
2471
2472 static int short_mem_test(void)
2473 {
2474 u32 *membase;
2475 u32 bxcr_num;
2476 u32 bxcf;
2477 int i;
2478 int j;
2479 phys_size_t base_addr;
2480 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2481 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2482 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2483 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2484 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2485 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2486 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2487 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2488 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2489 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2490 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2491 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2492 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2493 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2494 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2495 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2496 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2497 int l;
2498
2499 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2500 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2501
2502 /* Banks enabled */
2503 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2504 /* Bank is enabled */
2505
2506 /*
2507 * Only run test on accessable memory (below 2GB)
2508 */
2509 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2510 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2511 continue;
2512
2513 /*------------------------------------------------------------------
2514 * Run the short memory test.
2515 *-----------------------------------------------------------------*/
2516 membase = (u32 *)(u32)base_addr;
2517
2518 for (i = 0; i < NUMMEMTESTS; i++) {
2519 for (j = 0; j < NUMMEMWORDS; j++) {
2520 membase[j] = test[i][j];
2521 ppcDcbf((u32)&(membase[j]));
2522 }
2523 sync();
2524 for (l=0; l<NUMLOOPS; l++) {
2525 for (j = 0; j < NUMMEMWORDS; j++) {
2526 if (membase[j] != test[i][j]) {
2527 ppcDcbf((u32)&(membase[j]));
2528 return 0;
2529 }
2530 ppcDcbf((u32)&(membase[j]));
2531 }
2532 sync();
2533 }
2534 }
2535 } /* if bank enabled */
2536 } /* for bxcf_num */
2537
2538 return 1;
2539 }
2540
2541 #ifndef HARD_CODED_DQS
2542 /*-----------------------------------------------------------------------------+
2543 * DQS_calibration_process.
2544 *-----------------------------------------------------------------------------*/
2545 static void DQS_calibration_process(void)
2546 {
2547 unsigned long rfdc_reg;
2548 unsigned long rffd;
2549 unsigned long val;
2550 long rffd_average;
2551 long max_start;
2552 long min_end;
2553 unsigned long begin_rqfd[MAXRANKS];
2554 unsigned long begin_rffd[MAXRANKS];
2555 unsigned long end_rqfd[MAXRANKS];
2556 unsigned long end_rffd[MAXRANKS];
2557 char window_found;
2558 unsigned long dlycal;
2559 unsigned long dly_val;
2560 unsigned long max_pass_length;
2561 unsigned long current_pass_length;
2562 unsigned long current_fail_length;
2563 unsigned long current_start;
2564 long max_end;
2565 unsigned char fail_found;
2566 unsigned char pass_found;
2567 #if !defined(CONFIG_DDR_RQDC_FIXED)
2568 u32 rqdc_reg;
2569 u32 rqfd;
2570 u32 rqfd_start;
2571 u32 rqfd_average;
2572 int loopi = 0;
2573 char str[] = "Auto calibration -";
2574 char slash[] = "\\|/-\\|/-";
2575
2576 /*------------------------------------------------------------------
2577 * Test to determine the best read clock delay tuning bits.
2578 *
2579 * Before the DDR controller can be used, the read clock delay needs to be
2580 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2581 * This value cannot be hardcoded into the program because it changes
2582 * depending on the board's setup and environment.
2583 * To do this, all delay values are tested to see if they
2584 * work or not. By doing this, you get groups of fails with groups of
2585 * passing values. The idea is to find the start and end of a passing
2586 * window and take the center of it to use as the read clock delay.
2587 *
2588 * A failure has to be seen first so that when we hit a pass, we know
2589 * that it is truely the start of the window. If we get passing values
2590 * to start off with, we don't know if we are at the start of the window.
2591 *
2592 * The code assumes that a failure will always be found.
2593 * If a failure is not found, there is no easy way to get the middle
2594 * of the passing window. I guess we can pretty much pick any value
2595 * but some values will be better than others. Since the lowest speed
2596 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2597 * from experimentation it is safe to say you will always have a failure.
2598 *-----------------------------------------------------------------*/
2599
2600 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2601 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2602
2603 puts(str);
2604
2605 calibration_loop:
2606 mfsdram(SDRAM_RQDC, rqdc_reg);
2607 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2608 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2609 #else /* CONFIG_DDR_RQDC_FIXED */
2610 /*
2611 * On Katmai the complete auto-calibration somehow doesn't seem to
2612 * produce the best results, meaning optimal values for RQFD/RFFD.
2613 * This was discovered by GDA using a high bandwidth scope,
2614 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2615 * so now on Katmai "only" RFFD is auto-calibrated.
2616 */
2617 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2618 #endif /* CONFIG_DDR_RQDC_FIXED */
2619
2620 max_start = 0;
2621 min_end = 0;
2622 begin_rqfd[0] = 0;
2623 begin_rffd[0] = 0;
2624 begin_rqfd[1] = 0;
2625 begin_rffd[1] = 0;
2626 end_rqfd[0] = 0;
2627 end_rffd[0] = 0;
2628 end_rqfd[1] = 0;
2629 end_rffd[1] = 0;
2630 window_found = FALSE;
2631
2632 max_pass_length = 0;
2633 max_start = 0;
2634 max_end = 0;
2635 current_pass_length = 0;
2636 current_fail_length = 0;
2637 current_start = 0;
2638 window_found = FALSE;
2639 fail_found = FALSE;
2640 pass_found = FALSE;
2641
2642 /*
2643 * get the delay line calibration register value
2644 */
2645 mfsdram(SDRAM_DLCR, dlycal);
2646 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2647
2648 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2649 mfsdram(SDRAM_RFDC, rfdc_reg);
2650 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2651
2652 /*------------------------------------------------------------------
2653 * Set the timing reg for the test.
2654 *-----------------------------------------------------------------*/
2655 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2656
2657 /*------------------------------------------------------------------
2658 * See if the rffd value passed.
2659 *-----------------------------------------------------------------*/
2660 if (short_mem_test()) {
2661 if (fail_found == TRUE) {
2662 pass_found = TRUE;
2663 if (current_pass_length == 0)
2664 current_start = rffd;
2665
2666 current_fail_length = 0;
2667 current_pass_length++;
2668
2669 if (current_pass_length > max_pass_length) {
2670 max_pass_length = current_pass_length;
2671 max_start = current_start;
2672 max_end = rffd;
2673 }
2674 }
2675 } else {
2676 current_pass_length = 0;
2677 current_fail_length++;
2678
2679 if (current_fail_length >= (dly_val >> 2)) {
2680 if (fail_found == FALSE) {
2681 fail_found = TRUE;
2682 } else if (pass_found == TRUE) {
2683 window_found = TRUE;
2684 break;
2685 }
2686 }
2687 }
2688 } /* for rffd */
2689
2690 /*------------------------------------------------------------------
2691 * Set the average RFFD value
2692 *-----------------------------------------------------------------*/
2693 rffd_average = ((max_start + max_end) >> 1);
2694
2695 if (rffd_average < 0)
2696 rffd_average = 0;
2697
2698 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2699 rffd_average = SDRAM_RFDC_RFFD_MAX;
2700 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2701 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2702
2703 #if !defined(CONFIG_DDR_RQDC_FIXED)
2704 max_pass_length = 0;
2705 max_start = 0;
2706 max_end = 0;
2707 current_pass_length = 0;
2708 current_fail_length = 0;
2709 current_start = 0;
2710 window_found = FALSE;
2711 fail_found = FALSE;
2712 pass_found = FALSE;
2713
2714 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2715 mfsdram(SDRAM_RQDC, rqdc_reg);
2716 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2717
2718 /*------------------------------------------------------------------
2719 * Set the timing reg for the test.
2720 *-----------------------------------------------------------------*/
2721 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2722
2723 /*------------------------------------------------------------------
2724 * See if the rffd value passed.
2725 *-----------------------------------------------------------------*/
2726 if (short_mem_test()) {
2727 if (fail_found == TRUE) {
2728 pass_found = TRUE;
2729 if (current_pass_length == 0)
2730 current_start = rqfd;
2731
2732 current_fail_length = 0;
2733 current_pass_length++;
2734
2735 if (current_pass_length > max_pass_length) {
2736 max_pass_length = current_pass_length;
2737 max_start = current_start;
2738 max_end = rqfd;
2739 }
2740 }
2741 } else {
2742 current_pass_length = 0;
2743 current_fail_length++;
2744
2745 if (fail_found == FALSE) {
2746 fail_found = TRUE;
2747 } else if (pass_found == TRUE) {
2748 window_found = TRUE;
2749 break;
2750 }
2751 }
2752 }
2753
2754 rqfd_average = ((max_start + max_end) >> 1);
2755
2756 /*------------------------------------------------------------------
2757 * Make sure we found the valid read passing window. Halt if not
2758 *-----------------------------------------------------------------*/
2759 if (window_found == FALSE) {
2760 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2761 putc('\b');
2762 putc(slash[loopi++ % 8]);
2763
2764 /* try again from with a different RQFD start value */
2765 rqfd_start++;
2766 goto calibration_loop;
2767 }
2768
2769 printf("\nERROR: Cannot determine a common read delay for the "
2770 "DIMM(s) installed.\n");
2771 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2772 ppc4xx_ibm_ddr2_register_dump();
2773 spd_ddr_init_hang ();
2774 }
2775
2776 if (rqfd_average < 0)
2777 rqfd_average = 0;
2778
2779 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2780 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2781
2782 mtsdram(SDRAM_RQDC,
2783 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2784 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2785
2786 blank_string(strlen(str));
2787 #endif /* CONFIG_DDR_RQDC_FIXED */
2788
2789 /*
2790 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2791 * PowerPC440SP/SPe DDR2 application note:
2792 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2793 */
2794 mfsdram(SDRAM_RTSR, val);
2795 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2796 mfsdram(SDRAM_RDCC, val);
2797 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2798 val += 0x40000000;
2799 mtsdram(SDRAM_RDCC, val);
2800 }
2801 }
2802
2803 mfsdram(SDRAM_DLCR, val);
2804 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2805 mfsdram(SDRAM_RQDC, val);
2806 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2807 mfsdram(SDRAM_RFDC, val);
2808 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2809 mfsdram(SDRAM_RDCC, val);
2810 debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2811 }
2812 #else /* calibration test with hardvalues */
2813 /*-----------------------------------------------------------------------------+
2814 * DQS_calibration_process.
2815 *-----------------------------------------------------------------------------*/
2816 static void test(void)
2817 {
2818 unsigned long dimm_num;
2819 unsigned long ecc_temp;
2820 unsigned long i, j;
2821 unsigned long *membase;
2822 unsigned long bxcf[MAXRANKS];
2823 unsigned long val;
2824 char window_found;
2825 char begin_found[MAXDIMMS];
2826 char end_found[MAXDIMMS];
2827 char search_end[MAXDIMMS];
2828 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2829 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2830 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2831 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2832 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2833 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2834 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2835 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2836 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2837 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2838 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2839 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2840 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2841 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2842 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2843 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2844 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2845
2846 /*------------------------------------------------------------------
2847 * Test to determine the best read clock delay tuning bits.
2848 *
2849 * Before the DDR controller can be used, the read clock delay needs to be
2850 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2851 * This value cannot be hardcoded into the program because it changes
2852 * depending on the board's setup and environment.
2853 * To do this, all delay values are tested to see if they
2854 * work or not. By doing this, you get groups of fails with groups of
2855 * passing values. The idea is to find the start and end of a passing
2856 * window and take the center of it to use as the read clock delay.
2857 *
2858 * A failure has to be seen first so that when we hit a pass, we know
2859 * that it is truely the start of the window. If we get passing values
2860 * to start off with, we don't know if we are at the start of the window.
2861 *
2862 * The code assumes that a failure will always be found.
2863 * If a failure is not found, there is no easy way to get the middle
2864 * of the passing window. I guess we can pretty much pick any value
2865 * but some values will be better than others. Since the lowest speed
2866 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2867 * from experimentation it is safe to say you will always have a failure.
2868 *-----------------------------------------------------------------*/
2869 mfsdram(SDRAM_MCOPT1, ecc_temp);
2870 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2871 mfsdram(SDRAM_MCOPT1, val);
2872 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2873 SDRAM_MCOPT1_MCHK_NON);
2874
2875 window_found = FALSE;
2876 begin_found[0] = FALSE;
2877 end_found[0] = FALSE;
2878 search_end[0] = FALSE;
2879 begin_found[1] = FALSE;
2880 end_found[1] = FALSE;
2881 search_end[1] = FALSE;
2882
2883 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2884 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2885
2886 /* Banks enabled */
2887 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2888
2889 /* Bank is enabled */
2890 membase =
2891 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2892
2893 /*------------------------------------------------------------------
2894 * Run the short memory test.
2895 *-----------------------------------------------------------------*/
2896 for (i = 0; i < NUMMEMTESTS; i++) {
2897 for (j = 0; j < NUMMEMWORDS; j++) {
2898 membase[j] = test[i][j];
2899 ppcDcbf((u32)&(membase[j]));
2900 }
2901 sync();
2902 for (j = 0; j < NUMMEMWORDS; j++) {
2903 if (membase[j] != test[i][j]) {
2904 ppcDcbf((u32)&(membase[j]));
2905 break;
2906 }
2907 ppcDcbf((u32)&(membase[j]));
2908 }
2909 sync();
2910 if (j < NUMMEMWORDS)
2911 break;
2912 }
2913
2914 /*------------------------------------------------------------------
2915 * See if the rffd value passed.
2916 *-----------------------------------------------------------------*/
2917 if (i < NUMMEMTESTS) {
2918 if ((end_found[dimm_num] == FALSE) &&
2919 (search_end[dimm_num] == TRUE)) {
2920 end_found[dimm_num] = TRUE;
2921 }
2922 if ((end_found[0] == TRUE) &&
2923 (end_found[1] == TRUE))
2924 break;
2925 } else {
2926 if (begin_found[dimm_num] == FALSE) {
2927 begin_found[dimm_num] = TRUE;
2928 search_end[dimm_num] = TRUE;
2929 }
2930 }
2931 } else {
2932 begin_found[dimm_num] = TRUE;
2933 end_found[dimm_num] = TRUE;
2934 }
2935 }
2936
2937 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2938 window_found = TRUE;
2939
2940 /*------------------------------------------------------------------
2941 * Make sure we found the valid read passing window. Halt if not
2942 *-----------------------------------------------------------------*/
2943 if (window_found == FALSE) {
2944 printf("ERROR: Cannot determine a common read delay for the "
2945 "DIMM(s) installed.\n");
2946 spd_ddr_init_hang ();
2947 }
2948
2949 /*------------------------------------------------------------------
2950 * Restore the ECC variable to what it originally was
2951 *-----------------------------------------------------------------*/
2952 mtsdram(SDRAM_MCOPT1,
2953 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2954 | ecc_temp);
2955 }
2956 #endif
2957
2958 #else /* CONFIG_SPD_EEPROM */
2959
2960 /*-----------------------------------------------------------------------------
2961 * Function: initdram
2962 * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
2963 * banks. The configuration is performed using static, compile-
2964 * time parameters.
2965 *---------------------------------------------------------------------------*/
2966 phys_size_t initdram(int board_type)
2967 {
2968 /*
2969 * Only run this SDRAM init code once. For NAND booting
2970 * targets like Kilauea, we call initdram() early from the
2971 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2972 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2973 * which calls initdram() again. This time the controller
2974 * mustn't be reconfigured again since we're already running
2975 * from SDRAM.
2976 */
2977 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2978 unsigned long val;
2979
2980 /* Set Memory Bank Configuration Registers */
2981
2982 mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
2983 mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
2984 mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
2985 mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
2986
2987 /* Set Memory Clock Timing Register */
2988
2989 mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
2990
2991 /* Set Refresh Time Register */
2992
2993 mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
2994
2995 /* Set SDRAM Timing Registers */
2996
2997 mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
2998 mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
2999 mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
3000
3001 /* Set Mode and Extended Mode Registers */
3002
3003 mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
3004 mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
3005
3006 /* Set Memory Controller Options 1 Register */
3007
3008 mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
3009
3010 /* Set Manual Initialization Control Registers */
3011
3012 mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
3013 mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
3014 mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
3015 mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
3016 mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
3017 mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
3018 mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
3019 mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
3020 mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
3021 mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
3022 mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
3023 mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
3024 mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
3025 mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
3026 mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
3027 mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
3028
3029 /* Set On-Die Termination Registers */
3030
3031 mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
3032 mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
3033 mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
3034
3035 /* Set Write Timing Register */
3036
3037 mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
3038
3039 /*
3040 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3041 * SDRAM0_MCOPT2[IPTR] = 1
3042 */
3043
3044 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3045 SDRAM_MCOPT2_IPTR_EXECUTE));
3046
3047 /*
3048 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3049 * completion of initialization.
3050 */
3051
3052 do {
3053 mfsdram(SDRAM_MCSTAT, val);
3054 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3055
3056 /* Set Delay Control Registers */
3057
3058 mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
3059 mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
3060 mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
3061 mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
3062
3063 /*
3064 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3065 */
3066
3067 mfsdram(SDRAM_MCOPT2, val);
3068 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3069
3070 #if defined(CONFIG_DDR_ECC)
3071 ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
3072 #endif /* defined(CONFIG_DDR_ECC) */
3073
3074 ppc4xx_ibm_ddr2_register_dump();
3075 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3076
3077 return (CFG_MBYTES_SDRAM << 20);
3078 }
3079 #endif /* CONFIG_SPD_EEPROM */
3080
3081 static inline void ppc4xx_ibm_ddr2_register_dump(void)
3082 {
3083 #if defined(DEBUG)
3084 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3085
3086 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3087 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3088 PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
3089 PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
3090 PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
3091 PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
3092 #endif /* (defined(CONFIG_440SP) || ... */
3093 #if defined(CONFIG_405EX)
3094 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3095 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3096 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3097 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3098 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3099 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3100 #endif /* defined(CONFIG_405EX) */
3101 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3102 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3103 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3104 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3105 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3106 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3107 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3108 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3109 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3110 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3111 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3112 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3113 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3114 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3115 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3116 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3117 /*
3118 * OPART is only used as a trigger register.
3119 *
3120 * No data is contained in this register, and reading or writing
3121 * to is can cause bad things to happen (hangs). Just skip it and
3122 * report "N/A".
3123 */
3124 printf("%20s = N/A\n", "SDRAM_OPART");
3125 #endif /* defined(CONFIG_440SP) || ... */
3126 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3127 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3128 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3129 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3130 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3131 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3132 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3133 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3134 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3135 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3136 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3137 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3138 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3139 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3140 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3141 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3142 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3143 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3144 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3145 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3146 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3147 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3148 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3149 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3150 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3151 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3152 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3153 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3154 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3155 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3156 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3157 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3158 #endif /* defined(CONFIG_440SP) || ... */
3159 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3160 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3161 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3162 #endif /* defined(DEBUG) */
3163 }
3164
3165 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
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