2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
7 * 440/460: 440SP/440SPe/460EX/460GT
9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
12 * (C) Copyright 2007-2009
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
15 * COPYRIGHT AMCC CORPORATION 2004
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /* define DEBUG for debugging output (obviously ;-)) */
47 #include <asm/processor.h>
49 #include <asm/cache.h>
53 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
55 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
58 mfsdram(SDRAM_##mnemonic, data); \
59 printf("%20s[%02x] = 0x%08X\n", \
60 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
63 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \
66 data = mfdcr(SDRAM_##mnemonic); \
67 printf("%20s[%02x] = 0x%08X\n", \
68 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
71 #if defined(CONFIG_440)
73 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
74 * memory region. Right now the cache should still be disabled in U-Boot
75 * because of the EMAC driver, that need its buffer descriptor to be located
76 * in non cached memory.
78 * If at some time this restriction doesn't apply anymore, just define
79 * CONFIG_4xx_DCACHE in the board config file and this code should setup
80 * everything correctly.
82 #ifdef CONFIG_4xx_DCACHE
83 /* enable caching on SDRAM */
84 #define MY_TLB_WORD2_I_ENABLE 0
86 /* disable caching on SDRAM */
87 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
88 #endif /* CONFIG_4xx_DCACHE */
90 void dcbz_area(u32 start_address
, u32 num_bytes
);
91 #endif /* CONFIG_440 */
96 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
98 #if !defined(CONFIG_NAND_SPL)
99 /*-----------------------------------------------------------------------------+
101 *-----------------------------------------------------------------------------*/
102 phys_size_t
sdram_memsize(void)
104 phys_size_t mem_size
;
105 unsigned long mcopt2
;
106 unsigned long mcstat
;
113 mfsdram(SDRAM_MCOPT2
, mcopt2
);
114 mfsdram(SDRAM_MCSTAT
, mcstat
);
116 /* DDR controller must be enabled and not in self-refresh. */
117 /* Otherwise memsize is zero. */
118 if (((mcopt2
& SDRAM_MCOPT2_DCEN_MASK
) == SDRAM_MCOPT2_DCEN_ENABLE
)
119 && ((mcopt2
& SDRAM_MCOPT2_SREN_MASK
) == SDRAM_MCOPT2_SREN_EXIT
)
120 && ((mcstat
& (SDRAM_MCSTAT_MIC_MASK
| SDRAM_MCSTAT_SRMS_MASK
))
121 == (SDRAM_MCSTAT_MIC_COMP
| SDRAM_MCSTAT_SRMS_NOT_SF
))) {
122 for (i
= 0; i
< MAXBXCF
; i
++) {
123 mfsdram(SDRAM_MB0CF
+ (i
<< 2), mb0cf
);
125 if ((mb0cf
& SDRAM_BXCF_M_BE_MASK
) == SDRAM_BXCF_M_BE_ENABLE
) {
126 #if defined(CONFIG_440)
127 sdsz
= mfdcr_any(SDRAM_R0BAS
+ i
) & SDRAM_RXBAS_SDSZ_MASK
;
129 sdsz
= mb0cf
& SDRAM_RXBAS_SDSZ_MASK
;
132 case SDRAM_RXBAS_SDSZ_8
:
135 case SDRAM_RXBAS_SDSZ_16
:
138 case SDRAM_RXBAS_SDSZ_32
:
141 case SDRAM_RXBAS_SDSZ_64
:
144 case SDRAM_RXBAS_SDSZ_128
:
147 case SDRAM_RXBAS_SDSZ_256
:
150 case SDRAM_RXBAS_SDSZ_512
:
153 case SDRAM_RXBAS_SDSZ_1024
:
156 case SDRAM_RXBAS_SDSZ_2048
:
159 case SDRAM_RXBAS_SDSZ_4096
:
163 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
172 return mem_size
<< 20;
175 /*-----------------------------------------------------------------------------+
177 *-----------------------------------------------------------------------------*/
178 static unsigned long is_ecc_enabled(void)
182 mfsdram(SDRAM_MCOPT1
, val
);
184 return SDRAM_MCOPT1_MCHK_CHK_DECODE(val
);
187 /*-----------------------------------------------------------------------------+
189 *-----------------------------------------------------------------------------*/
190 void board_add_ram_info(int use_default
)
192 PPC4xx_SYS_INFO board_cfg
;
195 if (is_ecc_enabled())
200 get_sys_info(&board_cfg
);
202 #if defined(CONFIG_405EX)
203 val
= board_cfg
.freqPLB
;
205 mfsdr(SDR0_DDR0
, val
);
206 val
= MULDIV64((board_cfg
.freqPLB
), SDR0_DDR0_DDRM_DECODE(val
), 1);
208 printf(" enabled, %d MHz", (val
* 2) / 1000000);
210 mfsdram(SDRAM_MMODE
, val
);
211 val
= (val
& SDRAM_MMODE_DCL_MASK
) >> 4;
212 printf(", CL%d)", val
);
214 #endif /* !CONFIG_NAND_SPL */
216 #if defined(CONFIG_SPD_EEPROM)
218 /*-----------------------------------------------------------------------------+
220 *-----------------------------------------------------------------------------*/
233 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
235 #define ONE_BILLION 1000000000
237 #define CMD_NOP (7 << 19)
238 #define CMD_PRECHARGE (2 << 19)
239 #define CMD_REFRESH (1 << 19)
240 #define CMD_EMR (0 << 19)
241 #define CMD_READ (5 << 19)
242 #define CMD_WRITE (4 << 19)
244 #define SELECT_MR (0 << 16)
245 #define SELECT_EMR (1 << 16)
246 #define SELECT_EMR2 (2 << 16)
247 #define SELECT_EMR3 (3 << 16)
250 #define DLL_RESET 0x00000100
252 #define WRITE_RECOV_2 (1 << 9)
253 #define WRITE_RECOV_3 (2 << 9)
254 #define WRITE_RECOV_4 (3 << 9)
255 #define WRITE_RECOV_5 (4 << 9)
256 #define WRITE_RECOV_6 (5 << 9)
258 #define BURST_LEN_4 0x00000002
261 #define ODT_0_OHM 0x00000000
262 #define ODT_50_OHM 0x00000044
263 #define ODT_75_OHM 0x00000004
264 #define ODT_150_OHM 0x00000040
266 #define ODS_FULL 0x00000000
267 #define ODS_REDUCED 0x00000002
268 #define OCD_CALIB_DEF 0x00000380
270 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
271 #define ODT_EB0R (0x80000000 >> 8)
272 #define ODT_EB0W (0x80000000 >> 7)
273 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
274 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
275 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
277 /* Defines for the Read Cycle Delay test */
278 #define NUMMEMTESTS 8
279 #define NUMMEMWORDS 8
280 #define NUMLOOPS 64 /* memory test loops */
283 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
284 * To support such configurations, we "only" map the first 2GB via the TLB's. We
285 * need some free virtual address space for the remaining peripherals like, SoC
286 * devices, FLASH etc.
288 * Note that ECC is currently not supported on configurations with more than 2GB
289 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
290 * the ECC parity byte of the remaining area can't be written.
294 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
296 void __spd_ddr_init_hang (void)
300 void spd_ddr_init_hang (void) __attribute__((weak
, alias("__spd_ddr_init_hang")));
303 * To provide an interface for board specific config values in this common
304 * DDR setup code, we implement he "weak" default functions here. They return
305 * the default value back to the caller.
307 * Please see include/configs/yucca.h for an example fora board specific
310 u32
__ddr_wrdtr(u32 default_val
)
314 u32
ddr_wrdtr(u32
) __attribute__((weak
, alias("__ddr_wrdtr")));
316 u32
__ddr_clktr(u32 default_val
)
320 u32
ddr_clktr(u32
) __attribute__((weak
, alias("__ddr_clktr")));
323 /* Private Structure Definitions */
325 /* enum only to ease code for cas latency setting */
326 typedef enum ddr_cas_id
{
334 /*-----------------------------------------------------------------------------+
336 *-----------------------------------------------------------------------------*/
337 static void get_spd_info(unsigned long *dimm_populated
,
338 unsigned char *iic0_dimm_addr
,
339 unsigned long num_dimm_banks
);
340 static void check_mem_type(unsigned long *dimm_populated
,
341 unsigned char *iic0_dimm_addr
,
342 unsigned long num_dimm_banks
);
343 static void check_frequency(unsigned long *dimm_populated
,
344 unsigned char *iic0_dimm_addr
,
345 unsigned long num_dimm_banks
);
346 static void check_rank_number(unsigned long *dimm_populated
,
347 unsigned char *iic0_dimm_addr
,
348 unsigned long num_dimm_banks
);
349 static void check_voltage_type(unsigned long *dimm_populated
,
350 unsigned char *iic0_dimm_addr
,
351 unsigned long num_dimm_banks
);
352 static void program_memory_queue(unsigned long *dimm_populated
,
353 unsigned char *iic0_dimm_addr
,
354 unsigned long num_dimm_banks
);
355 static void program_codt(unsigned long *dimm_populated
,
356 unsigned char *iic0_dimm_addr
,
357 unsigned long num_dimm_banks
);
358 static void program_mode(unsigned long *dimm_populated
,
359 unsigned char *iic0_dimm_addr
,
360 unsigned long num_dimm_banks
,
361 ddr_cas_id_t
*selected_cas
,
362 int *write_recovery
);
363 static void program_tr(unsigned long *dimm_populated
,
364 unsigned char *iic0_dimm_addr
,
365 unsigned long num_dimm_banks
);
366 static void program_rtr(unsigned long *dimm_populated
,
367 unsigned char *iic0_dimm_addr
,
368 unsigned long num_dimm_banks
);
369 static void program_bxcf(unsigned long *dimm_populated
,
370 unsigned char *iic0_dimm_addr
,
371 unsigned long num_dimm_banks
);
372 static void program_copt1(unsigned long *dimm_populated
,
373 unsigned char *iic0_dimm_addr
,
374 unsigned long num_dimm_banks
);
375 static void program_initplr(unsigned long *dimm_populated
,
376 unsigned char *iic0_dimm_addr
,
377 unsigned long num_dimm_banks
,
378 ddr_cas_id_t selected_cas
,
380 #ifdef CONFIG_DDR_ECC
381 static void program_ecc(unsigned long *dimm_populated
,
382 unsigned char *iic0_dimm_addr
,
383 unsigned long num_dimm_banks
,
384 unsigned long tlb_word2_i_value
);
386 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
387 static void program_DQS_calibration(unsigned long *dimm_populated
,
388 unsigned char *iic0_dimm_addr
,
389 unsigned long num_dimm_banks
);
390 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
391 static void test(void);
393 static void DQS_calibration_process(void);
396 int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[]);
398 static unsigned char spd_read(uchar chip
, uint addr
)
400 unsigned char data
[2];
402 if (i2c_probe(chip
) == 0)
403 if (i2c_read(chip
, addr
, 1, data
, 1) == 0)
409 /*-----------------------------------------------------------------------------+
410 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
411 * Note: This routine runs from flash with a stack set up in the chip's
412 * sram space. It is important that the routine does not require .sbss, .bss or
413 * .data sections. It also cannot call routines that require these sections.
414 *-----------------------------------------------------------------------------*/
415 /*-----------------------------------------------------------------------------
417 * Description: Configures SDRAM memory banks for DDR operation.
418 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
419 * via the IIC bus and then configures the DDR SDRAM memory
420 * banks appropriately. If Auto Memory Configuration is
421 * not used, it is assumed that no DIMM is plugged
422 *-----------------------------------------------------------------------------*/
423 phys_size_t
initdram(int board_type
)
425 unsigned char iic0_dimm_addr
[] = SPD_EEPROM_ADDRESS
;
426 unsigned char spd0
[MAX_SPD_BYTES
];
427 unsigned char spd1
[MAX_SPD_BYTES
];
428 unsigned char *dimm_spd
[MAXDIMMS
];
429 unsigned long dimm_populated
[MAXDIMMS
];
430 unsigned long num_dimm_banks
; /* on board dimm banks */
432 ddr_cas_id_t selected_cas
= DDR_CAS_5
; /* preset to silence compiler */
434 phys_size_t dram_size
= 0;
436 num_dimm_banks
= sizeof(iic0_dimm_addr
);
438 /*------------------------------------------------------------------
439 * Set up an array of SPD matrixes.
440 *-----------------------------------------------------------------*/
444 /*------------------------------------------------------------------
445 * Reset the DDR-SDRAM controller.
446 *-----------------------------------------------------------------*/
447 mtsdr(SDR0_SRST
, (0x80000000 >> 10));
448 mtsdr(SDR0_SRST
, 0x00000000);
451 * Make sure I2C controller is initialized
455 /* switch to correct I2C bus */
456 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM
);
457 i2c_init(CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
459 /*------------------------------------------------------------------
460 * Clear out the serial presence detect buffers.
461 * Perform IIC reads from the dimm. Fill in the spds.
462 * Check to see if the dimm slots are populated
463 *-----------------------------------------------------------------*/
464 get_spd_info(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
466 /*------------------------------------------------------------------
467 * Check the memory type for the dimms plugged.
468 *-----------------------------------------------------------------*/
469 check_mem_type(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
471 /*------------------------------------------------------------------
472 * Check the frequency supported for the dimms plugged.
473 *-----------------------------------------------------------------*/
474 check_frequency(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
476 /*------------------------------------------------------------------
477 * Check the total rank number.
478 *-----------------------------------------------------------------*/
479 check_rank_number(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
481 /*------------------------------------------------------------------
482 * Check the voltage type for the dimms plugged.
483 *-----------------------------------------------------------------*/
484 check_voltage_type(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
486 /*------------------------------------------------------------------
487 * Program SDRAM controller options 2 register
488 * Except Enabling of the memory controller.
489 *-----------------------------------------------------------------*/
490 mfsdram(SDRAM_MCOPT2
, val
);
491 mtsdram(SDRAM_MCOPT2
,
493 ~(SDRAM_MCOPT2_SREN_MASK
| SDRAM_MCOPT2_PMEN_MASK
|
494 SDRAM_MCOPT2_IPTR_MASK
| SDRAM_MCOPT2_XSRP_MASK
|
495 SDRAM_MCOPT2_ISIE_MASK
))
496 | (SDRAM_MCOPT2_SREN_ENTER
| SDRAM_MCOPT2_PMEN_DISABLE
|
497 SDRAM_MCOPT2_IPTR_IDLE
| SDRAM_MCOPT2_XSRP_ALLOW
|
498 SDRAM_MCOPT2_ISIE_ENABLE
));
500 /*------------------------------------------------------------------
501 * Program SDRAM controller options 1 register
502 * Note: Does not enable the memory controller.
503 *-----------------------------------------------------------------*/
504 program_copt1(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
506 /*------------------------------------------------------------------
507 * Set the SDRAM Controller On Die Termination Register
508 *-----------------------------------------------------------------*/
509 program_codt(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
511 /*------------------------------------------------------------------
512 * Program SDRAM refresh register.
513 *-----------------------------------------------------------------*/
514 program_rtr(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
516 /*------------------------------------------------------------------
517 * Program SDRAM mode register.
518 *-----------------------------------------------------------------*/
519 program_mode(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
,
520 &selected_cas
, &write_recovery
);
522 /*------------------------------------------------------------------
523 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
524 *-----------------------------------------------------------------*/
525 mfsdram(SDRAM_WRDTR
, val
);
526 mtsdram(SDRAM_WRDTR
, (val
& ~(SDRAM_WRDTR_LLWP_MASK
| SDRAM_WRDTR_WTR_MASK
)) |
527 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC
| SDRAM_WRDTR_WTR_90_DEG_ADV
));
529 /*------------------------------------------------------------------
530 * Set the SDRAM Clock Timing Register
531 *-----------------------------------------------------------------*/
532 mfsdram(SDRAM_CLKTR
, val
);
533 mtsdram(SDRAM_CLKTR
, (val
& ~SDRAM_CLKTR_CLKP_MASK
) |
534 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG
));
536 /*------------------------------------------------------------------
537 * Program the BxCF registers.
538 *-----------------------------------------------------------------*/
539 program_bxcf(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
541 /*------------------------------------------------------------------
542 * Program SDRAM timing registers.
543 *-----------------------------------------------------------------*/
544 program_tr(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
546 /*------------------------------------------------------------------
547 * Set the Extended Mode register
548 *-----------------------------------------------------------------*/
549 mfsdram(SDRAM_MEMODE
, val
);
550 mtsdram(SDRAM_MEMODE
,
551 (val
& ~(SDRAM_MEMODE_DIC_MASK
| SDRAM_MEMODE_DLL_MASK
|
552 SDRAM_MEMODE_RTT_MASK
| SDRAM_MEMODE_DQS_MASK
)) |
553 (SDRAM_MEMODE_DIC_NORMAL
| SDRAM_MEMODE_DLL_ENABLE
554 | SDRAM_MEMODE_RTT_150OHM
| SDRAM_MEMODE_DQS_ENABLE
));
556 /*------------------------------------------------------------------
557 * Program Initialization preload registers.
558 *-----------------------------------------------------------------*/
559 program_initplr(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
,
560 selected_cas
, write_recovery
);
562 /*------------------------------------------------------------------
563 * Delay to ensure 200usec have elapsed since reset.
564 *-----------------------------------------------------------------*/
567 /*------------------------------------------------------------------
568 * Set the memory queue core base addr.
569 *-----------------------------------------------------------------*/
570 program_memory_queue(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
572 /*------------------------------------------------------------------
573 * Program SDRAM controller options 2 register
574 * Enable the memory controller.
575 *-----------------------------------------------------------------*/
576 mfsdram(SDRAM_MCOPT2
, val
);
577 mtsdram(SDRAM_MCOPT2
,
578 (val
& ~(SDRAM_MCOPT2_SREN_MASK
| SDRAM_MCOPT2_DCEN_MASK
|
579 SDRAM_MCOPT2_IPTR_MASK
| SDRAM_MCOPT2_ISIE_MASK
)) |
580 SDRAM_MCOPT2_IPTR_EXECUTE
);
582 /*------------------------------------------------------------------
583 * Wait for IPTR_EXECUTE init sequence to complete.
584 *-----------------------------------------------------------------*/
586 mfsdram(SDRAM_MCSTAT
, val
);
587 } while ((val
& SDRAM_MCSTAT_MIC_MASK
) == SDRAM_MCSTAT_MIC_NOTCOMP
);
589 /* enable the controller only after init sequence completes */
590 mfsdram(SDRAM_MCOPT2
, val
);
591 mtsdram(SDRAM_MCOPT2
, (val
| SDRAM_MCOPT2_DCEN_ENABLE
));
593 /* Make sure delay-line calibration is done before proceeding */
595 mfsdram(SDRAM_DLCR
, val
);
596 } while (!(val
& SDRAM_DLCR_DLCS_COMPLETE
));
598 /* get installed memory size */
599 dram_size
= sdram_memsize();
604 if (dram_size
> CONFIG_MAX_MEM_MAPPED
)
605 dram_size
= CONFIG_MAX_MEM_MAPPED
;
607 /* and program tlb entries for this size (dynamic) */
610 * Program TLB entries with caches enabled, for best performace
611 * while auto-calibrating and ECC generation
613 program_tlb(0, 0, dram_size
, 0);
615 /*------------------------------------------------------------------
617 *-----------------------------------------------------------------*/
618 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
619 DQS_autocalibration();
621 program_DQS_calibration(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
);
624 #ifdef CONFIG_DDR_ECC
625 /*------------------------------------------------------------------
626 * If ecc is enabled, initialize the parity bits.
627 *-----------------------------------------------------------------*/
628 program_ecc(dimm_populated
, iic0_dimm_addr
, num_dimm_banks
, 0);
632 * Now after initialization (auto-calibration and ECC generation)
633 * remove the TLB entries with caches enabled and program again with
634 * desired cache functionality
636 remove_tlb(0, dram_size
);
637 program_tlb(0, 0, dram_size
, MY_TLB_WORD2_I_ENABLE
);
639 ppc4xx_ibm_ddr2_register_dump();
642 * Clear potential errors resulting from auto-calibration.
643 * If not done, then we could get an interrupt later on when
644 * exceptions are enabled.
646 set_mcsr(get_mcsr());
648 return sdram_memsize();
651 static void get_spd_info(unsigned long *dimm_populated
,
652 unsigned char *iic0_dimm_addr
,
653 unsigned long num_dimm_banks
)
655 unsigned long dimm_num
;
656 unsigned long dimm_found
;
657 unsigned char num_of_bytes
;
658 unsigned char total_size
;
661 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
665 num_of_bytes
= spd_read(iic0_dimm_addr
[dimm_num
], 0);
666 debug("\nspd_read(0x%x) returned %d\n",
667 iic0_dimm_addr
[dimm_num
], num_of_bytes
);
668 total_size
= spd_read(iic0_dimm_addr
[dimm_num
], 1);
669 debug("spd_read(0x%x) returned %d\n",
670 iic0_dimm_addr
[dimm_num
], total_size
);
672 if ((num_of_bytes
!= 0) && (total_size
!= 0)) {
673 dimm_populated
[dimm_num
] = TRUE
;
675 debug("DIMM slot %lu: populated\n", dimm_num
);
677 dimm_populated
[dimm_num
] = FALSE
;
678 debug("DIMM slot %lu: Not populated\n", dimm_num
);
682 if (dimm_found
== FALSE
) {
683 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
684 spd_ddr_init_hang ();
689 /*------------------------------------------------------------------
690 * For the memory DIMMs installed, this routine verifies that they
691 * really are DDR specific DIMMs.
692 *-----------------------------------------------------------------*/
693 static void check_mem_type(unsigned long *dimm_populated
,
694 unsigned char *iic0_dimm_addr
,
695 unsigned long num_dimm_banks
)
697 unsigned long dimm_num
;
698 unsigned long dimm_type
;
700 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
701 if (dimm_populated
[dimm_num
] == TRUE
) {
702 dimm_type
= spd_read(iic0_dimm_addr
[dimm_num
], 2);
705 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
706 "slot %d.\n", (unsigned int)dimm_num
);
707 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
708 printf("Replace the DIMM module with a supported DIMM.\n\n");
709 spd_ddr_init_hang ();
712 printf("ERROR: EDO DIMM detected in slot %d.\n",
713 (unsigned int)dimm_num
);
714 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
715 printf("Replace the DIMM module with a supported DIMM.\n\n");
716 spd_ddr_init_hang ();
719 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
720 (unsigned int)dimm_num
);
721 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
722 printf("Replace the DIMM module with a supported DIMM.\n\n");
723 spd_ddr_init_hang ();
726 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
727 (unsigned int)dimm_num
);
728 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
729 printf("Replace the DIMM module with a supported DIMM.\n\n");
730 spd_ddr_init_hang ();
733 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
734 (unsigned int)dimm_num
);
735 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
736 printf("Replace the DIMM module with a supported DIMM.\n\n");
737 spd_ddr_init_hang ();
740 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
741 (unsigned int)dimm_num
);
742 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
743 printf("Replace the DIMM module with a supported DIMM.\n\n");
744 spd_ddr_init_hang ();
747 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num
);
748 dimm_populated
[dimm_num
] = SDRAM_DDR1
;
751 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num
);
752 dimm_populated
[dimm_num
] = SDRAM_DDR2
;
755 printf("ERROR: Unknown DIMM detected in slot %d.\n",
756 (unsigned int)dimm_num
);
757 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
758 printf("Replace the DIMM module with a supported DIMM.\n\n");
759 spd_ddr_init_hang ();
764 for (dimm_num
= 1; dimm_num
< num_dimm_banks
; dimm_num
++) {
765 if ((dimm_populated
[dimm_num
-1] != SDRAM_NONE
)
766 && (dimm_populated
[dimm_num
] != SDRAM_NONE
)
767 && (dimm_populated
[dimm_num
-1] != dimm_populated
[dimm_num
])) {
768 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
769 spd_ddr_init_hang ();
774 /*------------------------------------------------------------------
775 * For the memory DIMMs installed, this routine verifies that
776 * frequency previously calculated is supported.
777 *-----------------------------------------------------------------*/
778 static void check_frequency(unsigned long *dimm_populated
,
779 unsigned char *iic0_dimm_addr
,
780 unsigned long num_dimm_banks
)
782 unsigned long dimm_num
;
783 unsigned long tcyc_reg
;
784 unsigned long cycle_time
;
785 unsigned long calc_cycle_time
;
786 unsigned long sdram_freq
;
787 unsigned long sdr_ddrpll
;
788 PPC4xx_SYS_INFO board_cfg
;
790 /*------------------------------------------------------------------
791 * Get the board configuration info.
792 *-----------------------------------------------------------------*/
793 get_sys_info(&board_cfg
);
795 mfsdr(SDR0_DDR0
, sdr_ddrpll
);
796 sdram_freq
= ((board_cfg
.freqPLB
) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll
));
799 * calc_cycle_time is calculated from DDR frequency set by board/chip
800 * and is expressed in multiple of 10 picoseconds
801 * to match the way DIMM cycle time is calculated below.
803 calc_cycle_time
= MULDIV64(ONE_BILLION
, 100, sdram_freq
);
805 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
806 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
807 tcyc_reg
= spd_read(iic0_dimm_addr
[dimm_num
], 9);
809 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
810 * the higher order nibble (bits 4-7) designates the cycle time
811 * to a granularity of 1ns;
812 * the value presented by the lower order nibble (bits 0-3)
813 * has a granularity of .1ns and is added to the value designated
814 * by the higher nibble. In addition, four lines of the lower order
815 * nibble are assigned to support +.25,+.33, +.66 and +.75.
817 /* Convert from hex to decimal */
818 if ((tcyc_reg
& 0x0F) == 0x0D)
819 cycle_time
= (((tcyc_reg
& 0xF0) >> 4) * 100) + 75;
820 else if ((tcyc_reg
& 0x0F) == 0x0C)
821 cycle_time
= (((tcyc_reg
& 0xF0) >> 4) * 100) + 66;
822 else if ((tcyc_reg
& 0x0F) == 0x0B)
823 cycle_time
= (((tcyc_reg
& 0xF0) >> 4) * 100) + 33;
824 else if ((tcyc_reg
& 0x0F) == 0x0A)
825 cycle_time
= (((tcyc_reg
& 0xF0) >> 4) * 100) + 25;
827 cycle_time
= (((tcyc_reg
& 0xF0) >> 4) * 100) +
828 ((tcyc_reg
& 0x0F)*10);
829 debug("cycle_time=%lu [10 picoseconds]\n", cycle_time
);
831 if (cycle_time
> (calc_cycle_time
+ 10)) {
833 * the provided sdram cycle_time is too small
834 * for the available DIMM cycle_time.
835 * The additionnal 100ps is here to accept a small incertainty.
837 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
838 "slot %d \n while calculated cycle time is %d ps.\n",
839 (unsigned int)(cycle_time
*10),
840 (unsigned int)dimm_num
,
841 (unsigned int)(calc_cycle_time
*10));
842 printf("Replace the DIMM, or change DDR frequency via "
843 "strapping bits.\n\n");
844 spd_ddr_init_hang ();
850 /*------------------------------------------------------------------
851 * For the memory DIMMs installed, this routine verifies two
852 * ranks/banks maximum are availables.
853 *-----------------------------------------------------------------*/
854 static void check_rank_number(unsigned long *dimm_populated
,
855 unsigned char *iic0_dimm_addr
,
856 unsigned long num_dimm_banks
)
858 unsigned long dimm_num
;
859 unsigned long dimm_rank
;
860 unsigned long total_rank
= 0;
862 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
863 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
864 dimm_rank
= spd_read(iic0_dimm_addr
[dimm_num
], 5);
865 if (((unsigned long)spd_read(iic0_dimm_addr
[dimm_num
], 2)) == 0x08)
866 dimm_rank
= (dimm_rank
& 0x0F) +1;
868 dimm_rank
= dimm_rank
& 0x0F;
871 if (dimm_rank
> MAXRANKS
) {
872 printf("ERROR: DRAM DIMM detected with %lu ranks in "
873 "slot %lu is not supported.\n", dimm_rank
, dimm_num
);
874 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS
);
875 printf("Replace the DIMM module with a supported DIMM.\n\n");
876 spd_ddr_init_hang ();
878 total_rank
+= dimm_rank
;
880 if (total_rank
> MAXRANKS
) {
881 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
882 "for all slots.\n", (unsigned int)total_rank
);
883 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS
);
884 printf("Remove one of the DIMM modules.\n\n");
885 spd_ddr_init_hang ();
890 /*------------------------------------------------------------------
891 * only support 2.5V modules.
892 * This routine verifies this.
893 *-----------------------------------------------------------------*/
894 static void check_voltage_type(unsigned long *dimm_populated
,
895 unsigned char *iic0_dimm_addr
,
896 unsigned long num_dimm_banks
)
898 unsigned long dimm_num
;
899 unsigned long voltage_type
;
901 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
902 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
903 voltage_type
= spd_read(iic0_dimm_addr
[dimm_num
], 8);
904 switch (voltage_type
) {
906 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
907 printf("This DIMM is 5.0 Volt/TTL.\n");
908 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
909 (unsigned int)dimm_num
);
910 spd_ddr_init_hang ();
913 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
914 printf("This DIMM is LVTTL.\n");
915 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
916 (unsigned int)dimm_num
);
917 spd_ddr_init_hang ();
920 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
921 printf("This DIMM is 1.5 Volt.\n");
922 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
923 (unsigned int)dimm_num
);
924 spd_ddr_init_hang ();
927 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
928 printf("This DIMM is 3.3 Volt/TTL.\n");
929 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
930 (unsigned int)dimm_num
);
931 spd_ddr_init_hang ();
934 /* 2.5 Voltage only for DDR1 */
937 /* 1.8 Voltage only for DDR2 */
940 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
941 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
942 (unsigned int)dimm_num
);
943 spd_ddr_init_hang ();
950 /*-----------------------------------------------------------------------------+
952 *-----------------------------------------------------------------------------*/
953 static void program_copt1(unsigned long *dimm_populated
,
954 unsigned char *iic0_dimm_addr
,
955 unsigned long num_dimm_banks
)
957 unsigned long dimm_num
;
958 unsigned long mcopt1
;
959 unsigned long ecc_enabled
;
960 unsigned long ecc
= 0;
961 unsigned long data_width
= 0;
962 unsigned long dimm_32bit
;
963 unsigned long dimm_64bit
;
964 unsigned long registered
= 0;
965 unsigned long attribute
= 0;
966 unsigned long buf0
, buf1
; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
967 unsigned long bankcount
;
968 unsigned long ddrtype
;
971 #ifdef CONFIG_DDR_ECC
981 /*------------------------------------------------------------------
982 * Set memory controller options reg 1, SDRAM_MCOPT1.
983 *-----------------------------------------------------------------*/
984 mfsdram(SDRAM_MCOPT1
, val
);
985 mcopt1
= val
& ~(SDRAM_MCOPT1_MCHK_MASK
| SDRAM_MCOPT1_RDEN_MASK
|
986 SDRAM_MCOPT1_PMU_MASK
| SDRAM_MCOPT1_DMWD_MASK
|
987 SDRAM_MCOPT1_UIOS_MASK
| SDRAM_MCOPT1_BCNT_MASK
|
988 SDRAM_MCOPT1_DDR_TYPE_MASK
| SDRAM_MCOPT1_RWOO_MASK
|
989 SDRAM_MCOPT1_WOOO_MASK
| SDRAM_MCOPT1_DCOO_MASK
|
990 SDRAM_MCOPT1_DREF_MASK
);
992 mcopt1
|= SDRAM_MCOPT1_QDEP
;
993 mcopt1
|= SDRAM_MCOPT1_PMU_OPEN
;
994 mcopt1
|= SDRAM_MCOPT1_RWOO_DISABLED
;
995 mcopt1
|= SDRAM_MCOPT1_WOOO_DISABLED
;
996 mcopt1
|= SDRAM_MCOPT1_DCOO_DISABLED
;
997 mcopt1
|= SDRAM_MCOPT1_DREF_NORMAL
;
999 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
1000 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
1001 /* test ecc support */
1002 ecc
= (unsigned long)spd_read(iic0_dimm_addr
[dimm_num
], 11);
1003 if (ecc
!= 0x02) /* ecc not supported */
1004 ecc_enabled
= FALSE
;
1006 /* test bank count */
1007 bankcount
= (unsigned long)spd_read(iic0_dimm_addr
[dimm_num
], 17);
1008 if (bankcount
== 0x04) /* bank count = 4 */
1009 mcopt1
|= SDRAM_MCOPT1_4_BANKS
;
1010 else /* bank count = 8 */
1011 mcopt1
|= SDRAM_MCOPT1_8_BANKS
;
1014 ddrtype
= (unsigned long)spd_read(iic0_dimm_addr
[dimm_num
], 2);
1015 /* test for buffered/unbuffered, registered, differential clocks */
1016 registered
= (unsigned long)spd_read(iic0_dimm_addr
[dimm_num
], 20);
1017 attribute
= (unsigned long)spd_read(iic0_dimm_addr
[dimm_num
], 21);
1019 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1020 if (dimm_num
== 0) {
1021 if (dimm_populated
[dimm_num
] == SDRAM_DDR1
) /* DDR1 type */
1022 mcopt1
|= SDRAM_MCOPT1_DDR1_TYPE
;
1023 if (dimm_populated
[dimm_num
] == SDRAM_DDR2
) /* DDR2 type */
1024 mcopt1
|= SDRAM_MCOPT1_DDR2_TYPE
;
1025 if (registered
== 1) { /* DDR2 always buffered */
1026 /* TODO: what about above comments ? */
1027 mcopt1
|= SDRAM_MCOPT1_RDEN
;
1030 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1031 if ((attribute
& 0x02) == 0x00) {
1032 /* buffered not supported */
1035 mcopt1
|= SDRAM_MCOPT1_RDEN
;
1040 else if (dimm_num
== 1) {
1041 if (dimm_populated
[dimm_num
] == SDRAM_DDR1
) /* DDR1 type */
1042 mcopt1
|= SDRAM_MCOPT1_DDR1_TYPE
;
1043 if (dimm_populated
[dimm_num
] == SDRAM_DDR2
) /* DDR2 type */
1044 mcopt1
|= SDRAM_MCOPT1_DDR2_TYPE
;
1045 if (registered
== 1) {
1046 /* DDR2 always buffered */
1047 mcopt1
|= SDRAM_MCOPT1_RDEN
;
1050 if ((attribute
& 0x02) == 0x00) {
1051 /* buffered not supported */
1054 mcopt1
|= SDRAM_MCOPT1_RDEN
;
1060 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1061 data_width
= (unsigned long)spd_read(iic0_dimm_addr
[dimm_num
], 6) +
1062 (((unsigned long)spd_read(iic0_dimm_addr
[dimm_num
], 7)) << 8);
1064 switch (data_width
) {
1074 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1076 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1082 /* verify matching properties */
1083 if ((dimm_populated
[0] != SDRAM_NONE
) && (dimm_populated
[1] != SDRAM_NONE
)) {
1085 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1086 spd_ddr_init_hang ();
1090 if ((dimm_64bit
== TRUE
) && (dimm_32bit
== TRUE
)) {
1091 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1092 spd_ddr_init_hang ();
1094 else if ((dimm_64bit
== TRUE
) && (dimm_32bit
== FALSE
)) {
1095 mcopt1
|= SDRAM_MCOPT1_DMWD_64
;
1096 } else if ((dimm_64bit
== FALSE
) && (dimm_32bit
== TRUE
)) {
1097 mcopt1
|= SDRAM_MCOPT1_DMWD_32
;
1099 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1100 spd_ddr_init_hang ();
1103 if (ecc_enabled
== TRUE
)
1104 mcopt1
|= SDRAM_MCOPT1_MCHK_GEN
;
1106 mcopt1
|= SDRAM_MCOPT1_MCHK_NON
;
1108 mtsdram(SDRAM_MCOPT1
, mcopt1
);
1111 /*-----------------------------------------------------------------------------+
1113 *-----------------------------------------------------------------------------*/
1114 static void program_codt(unsigned long *dimm_populated
,
1115 unsigned char *iic0_dimm_addr
,
1116 unsigned long num_dimm_banks
)
1119 unsigned long modt0
= 0;
1120 unsigned long modt1
= 0;
1121 unsigned long modt2
= 0;
1122 unsigned long modt3
= 0;
1123 unsigned char dimm_num
;
1124 unsigned char dimm_rank
;
1125 unsigned char total_rank
= 0;
1126 unsigned char total_dimm
= 0;
1127 unsigned char dimm_type
= 0;
1128 unsigned char firstSlot
= 0;
1130 /*------------------------------------------------------------------
1131 * Set the SDRAM Controller On Die Termination Register
1132 *-----------------------------------------------------------------*/
1133 mfsdram(SDRAM_CODT
, codt
);
1134 codt
&= ~(SDRAM_CODT_DQS_SINGLE_END
| SDRAM_CODT_CKSE_SINGLE_END
);
1135 codt
|= SDRAM_CODT_IO_NMODE
;
1137 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
1138 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
1139 dimm_rank
= (unsigned long)spd_read(iic0_dimm_addr
[dimm_num
], 5);
1140 if (((unsigned long)spd_read(iic0_dimm_addr
[dimm_num
], 2)) == 0x08) {
1141 dimm_rank
= (dimm_rank
& 0x0F) + 1;
1142 dimm_type
= SDRAM_DDR2
;
1144 dimm_rank
= dimm_rank
& 0x0F;
1145 dimm_type
= SDRAM_DDR1
;
1148 total_rank
+= dimm_rank
;
1150 if ((dimm_num
== 0) && (total_dimm
== 1))
1156 if (dimm_type
== SDRAM_DDR2
) {
1157 codt
|= SDRAM_CODT_DQS_1_8_V_DDR2
;
1158 if ((total_dimm
== 1) && (firstSlot
== TRUE
)) {
1159 if (total_rank
== 1) { /* PUUU */
1160 codt
|= CALC_ODT_R(0);
1161 modt0
= CALC_ODT_W(0);
1166 if (total_rank
== 2) { /* PPUU */
1167 codt
|= CALC_ODT_R(0) | CALC_ODT_R(1);
1168 modt0
= CALC_ODT_W(0) | CALC_ODT_W(1);
1173 } else if ((total_dimm
== 1) && (firstSlot
!= TRUE
)) {
1174 if (total_rank
== 1) { /* UUPU */
1175 codt
|= CALC_ODT_R(2);
1178 modt2
= CALC_ODT_W(2);
1181 if (total_rank
== 2) { /* UUPP */
1182 codt
|= CALC_ODT_R(2) | CALC_ODT_R(3);
1185 modt2
= CALC_ODT_W(2) | CALC_ODT_W(3);
1189 if (total_dimm
== 2) {
1190 if (total_rank
== 2) { /* PUPU */
1191 codt
|= CALC_ODT_R(0) | CALC_ODT_R(2);
1192 modt0
= CALC_ODT_RW(2);
1194 modt2
= CALC_ODT_RW(0);
1197 if (total_rank
== 4) { /* PPPP */
1198 codt
|= CALC_ODT_R(0) | CALC_ODT_R(1) |
1199 CALC_ODT_R(2) | CALC_ODT_R(3);
1200 modt0
= CALC_ODT_RW(2) | CALC_ODT_RW(3);
1202 modt2
= CALC_ODT_RW(0) | CALC_ODT_RW(1);
1207 codt
|= SDRAM_CODT_DQS_2_5_V_DDR1
;
1213 if (total_dimm
== 1) {
1214 if (total_rank
== 1)
1216 if (total_rank
== 2)
1219 if (total_dimm
== 2) {
1220 if (total_rank
== 2)
1222 if (total_rank
== 4)
1227 debug("nb of dimm %d\n", total_dimm
);
1228 debug("nb of rank %d\n", total_rank
);
1229 if (total_dimm
== 1)
1230 debug("dimm in slot %d\n", firstSlot
);
1232 mtsdram(SDRAM_CODT
, codt
);
1233 mtsdram(SDRAM_MODT0
, modt0
);
1234 mtsdram(SDRAM_MODT1
, modt1
);
1235 mtsdram(SDRAM_MODT2
, modt2
);
1236 mtsdram(SDRAM_MODT3
, modt3
);
1239 /*-----------------------------------------------------------------------------+
1241 *-----------------------------------------------------------------------------*/
1242 static void program_initplr(unsigned long *dimm_populated
,
1243 unsigned char *iic0_dimm_addr
,
1244 unsigned long num_dimm_banks
,
1245 ddr_cas_id_t selected_cas
,
1259 /******************************************************
1260 ** Assumption: if more than one DIMM, all DIMMs are the same
1261 ** as already checked in check_memory_type
1262 ******************************************************/
1264 if ((dimm_populated
[0] == SDRAM_DDR1
) || (dimm_populated
[1] == SDRAM_DDR1
)) {
1265 mtsdram(SDRAM_INITPLR0
, 0x81B80000);
1266 mtsdram(SDRAM_INITPLR1
, 0x81900400);
1267 mtsdram(SDRAM_INITPLR2
, 0x81810000);
1268 mtsdram(SDRAM_INITPLR3
, 0xff800162);
1269 mtsdram(SDRAM_INITPLR4
, 0x81900400);
1270 mtsdram(SDRAM_INITPLR5
, 0x86080000);
1271 mtsdram(SDRAM_INITPLR6
, 0x86080000);
1272 mtsdram(SDRAM_INITPLR7
, 0x81000062);
1273 } else if ((dimm_populated
[0] == SDRAM_DDR2
) || (dimm_populated
[1] == SDRAM_DDR2
)) {
1274 switch (selected_cas
) {
1285 printf("ERROR: ucode error on selected_cas value %d", selected_cas
);
1286 spd_ddr_init_hang ();
1292 * ToDo - Still a problem with the write recovery:
1293 * On the Corsair CM2X512-5400C4 module, setting write recovery
1294 * in the INITPLR reg to the value calculated in program_mode()
1295 * results in not correctly working DDR2 memory (crash after
1298 * So for now, set the write recovery to 3. This seems to work
1299 * on the Corair module too.
1303 switch (write_recovery
) {
1317 printf("ERROR: write recovery not support (%d)", write_recovery
);
1318 spd_ddr_init_hang ();
1322 wr
= WRITE_RECOV_3
; /* test-only, see description above */
1325 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++)
1326 if (dimm_populated
[dimm_num
] != SDRAM_NONE
)
1328 if (total_dimm
== 1) {
1331 } else if (total_dimm
== 2) {
1335 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm
);
1336 spd_ddr_init_hang ();
1339 mr
= CMD_EMR
| SELECT_MR
| BURST_LEN_4
| wr
| cas
;
1340 emr
= CMD_EMR
| SELECT_EMR
| odt
| ods
;
1341 emr2
= CMD_EMR
| SELECT_EMR2
;
1342 emr3
= CMD_EMR
| SELECT_EMR3
;
1343 /* NOP - Wait 106 MemClk cycles */
1344 mtsdram(SDRAM_INITPLR0
, SDRAM_INITPLR_ENABLE
| CMD_NOP
|
1345 SDRAM_INITPLR_IMWT_ENCODE(106));
1347 /* precharge 4 MemClk cycles */
1348 mtsdram(SDRAM_INITPLR1
, SDRAM_INITPLR_ENABLE
| CMD_PRECHARGE
|
1349 SDRAM_INITPLR_IMWT_ENCODE(4));
1350 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1351 mtsdram(SDRAM_INITPLR2
, SDRAM_INITPLR_ENABLE
| emr2
|
1352 SDRAM_INITPLR_IMWT_ENCODE(2));
1353 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1354 mtsdram(SDRAM_INITPLR3
, SDRAM_INITPLR_ENABLE
| emr3
|
1355 SDRAM_INITPLR_IMWT_ENCODE(2));
1356 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1357 mtsdram(SDRAM_INITPLR4
, SDRAM_INITPLR_ENABLE
| emr
|
1358 SDRAM_INITPLR_IMWT_ENCODE(2));
1359 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1360 mtsdram(SDRAM_INITPLR5
, SDRAM_INITPLR_ENABLE
| mr
| DLL_RESET
|
1361 SDRAM_INITPLR_IMWT_ENCODE(200));
1363 /* precharge 4 MemClk cycles */
1364 mtsdram(SDRAM_INITPLR6
, SDRAM_INITPLR_ENABLE
| CMD_PRECHARGE
|
1365 SDRAM_INITPLR_IMWT_ENCODE(4));
1366 /* Refresh 25 MemClk cycles */
1367 mtsdram(SDRAM_INITPLR7
, SDRAM_INITPLR_ENABLE
| CMD_REFRESH
|
1368 SDRAM_INITPLR_IMWT_ENCODE(25));
1369 /* Refresh 25 MemClk cycles */
1370 mtsdram(SDRAM_INITPLR8
, SDRAM_INITPLR_ENABLE
| CMD_REFRESH
|
1371 SDRAM_INITPLR_IMWT_ENCODE(25));
1372 /* Refresh 25 MemClk cycles */
1373 mtsdram(SDRAM_INITPLR9
, SDRAM_INITPLR_ENABLE
| CMD_REFRESH
|
1374 SDRAM_INITPLR_IMWT_ENCODE(25));
1375 /* Refresh 25 MemClk cycles */
1376 mtsdram(SDRAM_INITPLR10
, SDRAM_INITPLR_ENABLE
| CMD_REFRESH
|
1377 SDRAM_INITPLR_IMWT_ENCODE(25));
1378 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1379 mtsdram(SDRAM_INITPLR11
, SDRAM_INITPLR_ENABLE
| mr
|
1380 SDRAM_INITPLR_IMWT_ENCODE(2));
1381 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1382 mtsdram(SDRAM_INITPLR12
, SDRAM_INITPLR_ENABLE
| OCD_CALIB_DEF
|
1383 SDRAM_INITPLR_IMWT_ENCODE(2) | emr
);
1385 mtsdram(SDRAM_INITPLR13
, SDRAM_INITPLR_ENABLE
| emr
|
1386 SDRAM_INITPLR_IMWT_ENCODE(2));
1388 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1389 spd_ddr_init_hang ();
1393 /*------------------------------------------------------------------
1394 * This routine programs the SDRAM_MMODE register.
1395 * the selected_cas is an output parameter, that will be passed
1396 * by caller to call the above program_initplr( )
1397 *-----------------------------------------------------------------*/
1398 static void program_mode(unsigned long *dimm_populated
,
1399 unsigned char *iic0_dimm_addr
,
1400 unsigned long num_dimm_banks
,
1401 ddr_cas_id_t
*selected_cas
,
1402 int *write_recovery
)
1404 unsigned long dimm_num
;
1405 unsigned long sdram_ddr1
;
1406 unsigned long t_wr_ns
;
1407 unsigned long t_wr_clk
;
1408 unsigned long cas_bit
;
1409 unsigned long cas_index
;
1410 unsigned long sdram_freq
;
1411 unsigned long ddr_check
;
1412 unsigned long mmode
;
1413 unsigned long tcyc_reg
;
1414 unsigned long cycle_2_0_clk
;
1415 unsigned long cycle_2_5_clk
;
1416 unsigned long cycle_3_0_clk
;
1417 unsigned long cycle_4_0_clk
;
1418 unsigned long cycle_5_0_clk
;
1419 unsigned long max_2_0_tcyc_ns_x_100
;
1420 unsigned long max_2_5_tcyc_ns_x_100
;
1421 unsigned long max_3_0_tcyc_ns_x_100
;
1422 unsigned long max_4_0_tcyc_ns_x_100
;
1423 unsigned long max_5_0_tcyc_ns_x_100
;
1424 unsigned long cycle_time_ns_x_100
[3];
1425 PPC4xx_SYS_INFO board_cfg
;
1426 unsigned char cas_2_0_available
;
1427 unsigned char cas_2_5_available
;
1428 unsigned char cas_3_0_available
;
1429 unsigned char cas_4_0_available
;
1430 unsigned char cas_5_0_available
;
1431 unsigned long sdr_ddrpll
;
1433 /*------------------------------------------------------------------
1434 * Get the board configuration info.
1435 *-----------------------------------------------------------------*/
1436 get_sys_info(&board_cfg
);
1438 mfsdr(SDR0_DDR0
, sdr_ddrpll
);
1439 sdram_freq
= MULDIV64((board_cfg
.freqPLB
), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll
), 1);
1440 debug("sdram_freq=%lu\n", sdram_freq
);
1442 /*------------------------------------------------------------------
1443 * Handle the timing. We need to find the worst case timing of all
1444 * the dimm modules installed.
1445 *-----------------------------------------------------------------*/
1447 cas_2_0_available
= TRUE
;
1448 cas_2_5_available
= TRUE
;
1449 cas_3_0_available
= TRUE
;
1450 cas_4_0_available
= TRUE
;
1451 cas_5_0_available
= TRUE
;
1452 max_2_0_tcyc_ns_x_100
= 10;
1453 max_2_5_tcyc_ns_x_100
= 10;
1454 max_3_0_tcyc_ns_x_100
= 10;
1455 max_4_0_tcyc_ns_x_100
= 10;
1456 max_5_0_tcyc_ns_x_100
= 10;
1459 /* loop through all the DIMM slots on the board */
1460 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
1461 /* If a dimm is installed in a particular slot ... */
1462 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
1463 if (dimm_populated
[dimm_num
] == SDRAM_DDR1
)
1468 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1469 cas_bit
= spd_read(iic0_dimm_addr
[dimm_num
], 18);
1470 debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit
);
1472 /* For a particular DIMM, grab the three CAS values it supports */
1473 for (cas_index
= 0; cas_index
< 3; cas_index
++) {
1474 switch (cas_index
) {
1476 tcyc_reg
= spd_read(iic0_dimm_addr
[dimm_num
], 9);
1479 tcyc_reg
= spd_read(iic0_dimm_addr
[dimm_num
], 23);
1482 tcyc_reg
= spd_read(iic0_dimm_addr
[dimm_num
], 25);
1486 if ((tcyc_reg
& 0x0F) >= 10) {
1487 if ((tcyc_reg
& 0x0F) == 0x0D) {
1488 /* Convert from hex to decimal */
1489 cycle_time_ns_x_100
[cas_index
] =
1490 (((tcyc_reg
& 0xF0) >> 4) * 100) + 75;
1492 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1493 "in slot %d\n", (unsigned int)dimm_num
);
1494 spd_ddr_init_hang ();
1497 /* Convert from hex to decimal */
1498 cycle_time_ns_x_100
[cas_index
] =
1499 (((tcyc_reg
& 0xF0) >> 4) * 100) +
1500 ((tcyc_reg
& 0x0F)*10);
1502 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index
,
1503 cycle_time_ns_x_100
[cas_index
]);
1506 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1507 /* supported for a particular DIMM. */
1512 * DDR devices use the following bitmask for CAS latency:
1513 * Bit 7 6 5 4 3 2 1 0
1514 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1516 if (((cas_bit
& 0x40) == 0x40) && (cas_index
< 3) &&
1517 (cycle_time_ns_x_100
[cas_index
] != 0)) {
1518 max_4_0_tcyc_ns_x_100
= max(max_4_0_tcyc_ns_x_100
,
1519 cycle_time_ns_x_100
[cas_index
]);
1524 cas_4_0_available
= FALSE
;
1527 if (((cas_bit
& 0x10) == 0x10) && (cas_index
< 3) &&
1528 (cycle_time_ns_x_100
[cas_index
] != 0)) {
1529 max_3_0_tcyc_ns_x_100
= max(max_3_0_tcyc_ns_x_100
,
1530 cycle_time_ns_x_100
[cas_index
]);
1535 cas_3_0_available
= FALSE
;
1538 if (((cas_bit
& 0x08) == 0x08) && (cas_index
< 3) &&
1539 (cycle_time_ns_x_100
[cas_index
] != 0)) {
1540 max_2_5_tcyc_ns_x_100
= max(max_2_5_tcyc_ns_x_100
,
1541 cycle_time_ns_x_100
[cas_index
]);
1546 cas_2_5_available
= FALSE
;
1549 if (((cas_bit
& 0x04) == 0x04) && (cas_index
< 3) &&
1550 (cycle_time_ns_x_100
[cas_index
] != 0)) {
1551 max_2_0_tcyc_ns_x_100
= max(max_2_0_tcyc_ns_x_100
,
1552 cycle_time_ns_x_100
[cas_index
]);
1557 cas_2_0_available
= FALSE
;
1561 * DDR2 devices use the following bitmask for CAS latency:
1562 * Bit 7 6 5 4 3 2 1 0
1563 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1565 if (((cas_bit
& 0x20) == 0x20) && (cas_index
< 3) &&
1566 (cycle_time_ns_x_100
[cas_index
] != 0)) {
1567 max_5_0_tcyc_ns_x_100
= max(max_5_0_tcyc_ns_x_100
,
1568 cycle_time_ns_x_100
[cas_index
]);
1573 cas_5_0_available
= FALSE
;
1576 if (((cas_bit
& 0x10) == 0x10) && (cas_index
< 3) &&
1577 (cycle_time_ns_x_100
[cas_index
] != 0)) {
1578 max_4_0_tcyc_ns_x_100
= max(max_4_0_tcyc_ns_x_100
,
1579 cycle_time_ns_x_100
[cas_index
]);
1584 cas_4_0_available
= FALSE
;
1587 if (((cas_bit
& 0x08) == 0x08) && (cas_index
< 3) &&
1588 (cycle_time_ns_x_100
[cas_index
] != 0)) {
1589 max_3_0_tcyc_ns_x_100
= max(max_3_0_tcyc_ns_x_100
,
1590 cycle_time_ns_x_100
[cas_index
]);
1595 cas_3_0_available
= FALSE
;
1601 /*------------------------------------------------------------------
1602 * Set the SDRAM mode, SDRAM_MMODE
1603 *-----------------------------------------------------------------*/
1604 mfsdram(SDRAM_MMODE
, mmode
);
1605 mmode
= mmode
& ~(SDRAM_MMODE_WR_MASK
| SDRAM_MMODE_DCL_MASK
);
1607 /* add 10 here because of rounding problems */
1608 cycle_2_0_clk
= MULDIV64(ONE_BILLION
, 100, max_2_0_tcyc_ns_x_100
) + 10;
1609 cycle_2_5_clk
= MULDIV64(ONE_BILLION
, 100, max_2_5_tcyc_ns_x_100
) + 10;
1610 cycle_3_0_clk
= MULDIV64(ONE_BILLION
, 100, max_3_0_tcyc_ns_x_100
) + 10;
1611 cycle_4_0_clk
= MULDIV64(ONE_BILLION
, 100, max_4_0_tcyc_ns_x_100
) + 10;
1612 cycle_5_0_clk
= MULDIV64(ONE_BILLION
, 100, max_5_0_tcyc_ns_x_100
) + 10;
1613 debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk
);
1614 debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk
);
1615 debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk
);
1617 if (sdram_ddr1
== TRUE
) { /* DDR1 */
1618 if ((cas_2_0_available
== TRUE
) && (sdram_freq
<= cycle_2_0_clk
)) {
1619 mmode
|= SDRAM_MMODE_DCL_DDR1_2_0_CLK
;
1620 *selected_cas
= DDR_CAS_2
;
1621 } else if ((cas_2_5_available
== TRUE
) && (sdram_freq
<= cycle_2_5_clk
)) {
1622 mmode
|= SDRAM_MMODE_DCL_DDR1_2_5_CLK
;
1623 *selected_cas
= DDR_CAS_2_5
;
1624 } else if ((cas_3_0_available
== TRUE
) && (sdram_freq
<= cycle_3_0_clk
)) {
1625 mmode
|= SDRAM_MMODE_DCL_DDR1_3_0_CLK
;
1626 *selected_cas
= DDR_CAS_3
;
1628 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1629 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1630 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1631 spd_ddr_init_hang ();
1634 debug("cas_3_0_available=%d\n", cas_3_0_available
);
1635 debug("cas_4_0_available=%d\n", cas_4_0_available
);
1636 debug("cas_5_0_available=%d\n", cas_5_0_available
);
1637 if ((cas_3_0_available
== TRUE
) && (sdram_freq
<= cycle_3_0_clk
)) {
1638 mmode
|= SDRAM_MMODE_DCL_DDR2_3_0_CLK
;
1639 *selected_cas
= DDR_CAS_3
;
1640 } else if ((cas_4_0_available
== TRUE
) && (sdram_freq
<= cycle_4_0_clk
)) {
1641 mmode
|= SDRAM_MMODE_DCL_DDR2_4_0_CLK
;
1642 *selected_cas
= DDR_CAS_4
;
1643 } else if ((cas_5_0_available
== TRUE
) && (sdram_freq
<= cycle_5_0_clk
)) {
1644 mmode
|= SDRAM_MMODE_DCL_DDR2_5_0_CLK
;
1645 *selected_cas
= DDR_CAS_5
;
1647 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1648 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1649 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1650 printf("cas3=%d cas4=%d cas5=%d\n",
1651 cas_3_0_available
, cas_4_0_available
, cas_5_0_available
);
1652 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1653 sdram_freq
, cycle_3_0_clk
, cycle_4_0_clk
, cycle_5_0_clk
);
1654 spd_ddr_init_hang ();
1658 if (sdram_ddr1
== TRUE
)
1659 mmode
|= SDRAM_MMODE_WR_DDR1
;
1662 /* loop through all the DIMM slots on the board */
1663 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
1664 /* If a dimm is installed in a particular slot ... */
1665 if (dimm_populated
[dimm_num
] != SDRAM_NONE
)
1666 t_wr_ns
= max(t_wr_ns
,
1667 spd_read(iic0_dimm_addr
[dimm_num
], 36) >> 2);
1671 * convert from nanoseconds to ddr clocks
1672 * round up if necessary
1674 t_wr_clk
= MULDIV64(sdram_freq
, t_wr_ns
, ONE_BILLION
);
1675 ddr_check
= MULDIV64(ONE_BILLION
, t_wr_clk
, t_wr_ns
);
1676 if (sdram_freq
!= ddr_check
)
1684 mmode
|= SDRAM_MMODE_WR_DDR2_3_CYC
;
1687 mmode
|= SDRAM_MMODE_WR_DDR2_4_CYC
;
1690 mmode
|= SDRAM_MMODE_WR_DDR2_5_CYC
;
1693 mmode
|= SDRAM_MMODE_WR_DDR2_6_CYC
;
1696 *write_recovery
= t_wr_clk
;
1699 debug("CAS latency = %d\n", *selected_cas
);
1700 debug("Write recovery = %d\n", *write_recovery
);
1702 mtsdram(SDRAM_MMODE
, mmode
);
1705 /*-----------------------------------------------------------------------------+
1707 *-----------------------------------------------------------------------------*/
1708 static void program_rtr(unsigned long *dimm_populated
,
1709 unsigned char *iic0_dimm_addr
,
1710 unsigned long num_dimm_banks
)
1712 PPC4xx_SYS_INFO board_cfg
;
1713 unsigned long max_refresh_rate
;
1714 unsigned long dimm_num
;
1715 unsigned long refresh_rate_type
;
1716 unsigned long refresh_rate
;
1718 unsigned long sdram_freq
;
1719 unsigned long sdr_ddrpll
;
1722 /*------------------------------------------------------------------
1723 * Get the board configuration info.
1724 *-----------------------------------------------------------------*/
1725 get_sys_info(&board_cfg
);
1727 /*------------------------------------------------------------------
1728 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1729 *-----------------------------------------------------------------*/
1730 mfsdr(SDR0_DDR0
, sdr_ddrpll
);
1731 sdram_freq
= ((board_cfg
.freqPLB
) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll
));
1733 max_refresh_rate
= 0;
1734 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
1735 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
1737 refresh_rate_type
= spd_read(iic0_dimm_addr
[dimm_num
], 12);
1738 refresh_rate_type
&= 0x7F;
1739 switch (refresh_rate_type
) {
1741 refresh_rate
= 15625;
1744 refresh_rate
= 3906;
1747 refresh_rate
= 7812;
1750 refresh_rate
= 31250;
1753 refresh_rate
= 62500;
1756 refresh_rate
= 125000;
1760 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1761 (unsigned int)dimm_num
);
1762 printf("Replace the DIMM module with a supported DIMM.\n\n");
1763 spd_ddr_init_hang ();
1767 max_refresh_rate
= max(max_refresh_rate
, refresh_rate
);
1771 rint
= MULDIV64(sdram_freq
, max_refresh_rate
, ONE_BILLION
);
1772 mfsdram(SDRAM_RTR
, val
);
1773 mtsdram(SDRAM_RTR
, (val
& ~SDRAM_RTR_RINT_MASK
) |
1774 (SDRAM_RTR_RINT_ENCODE(rint
)));
1777 /*------------------------------------------------------------------
1778 * This routine programs the SDRAM_TRx registers.
1779 *-----------------------------------------------------------------*/
1780 static void program_tr(unsigned long *dimm_populated
,
1781 unsigned char *iic0_dimm_addr
,
1782 unsigned long num_dimm_banks
)
1784 unsigned long dimm_num
;
1785 unsigned long sdram_ddr1
;
1786 unsigned long t_rp_ns
;
1787 unsigned long t_rcd_ns
;
1788 unsigned long t_rrd_ns
;
1789 unsigned long t_ras_ns
;
1790 unsigned long t_rc_ns
;
1791 unsigned long t_rfc_ns
;
1792 unsigned long t_wpc_ns
;
1793 unsigned long t_wtr_ns
;
1794 unsigned long t_rpc_ns
;
1795 unsigned long t_rp_clk
;
1796 unsigned long t_rcd_clk
;
1797 unsigned long t_rrd_clk
;
1798 unsigned long t_ras_clk
;
1799 unsigned long t_rc_clk
;
1800 unsigned long t_rfc_clk
;
1801 unsigned long t_wpc_clk
;
1802 unsigned long t_wtr_clk
;
1803 unsigned long t_rpc_clk
;
1804 unsigned long sdtr1
, sdtr2
, sdtr3
;
1805 unsigned long ddr_check
;
1806 unsigned long sdram_freq
;
1807 unsigned long sdr_ddrpll
;
1809 PPC4xx_SYS_INFO board_cfg
;
1811 /*------------------------------------------------------------------
1812 * Get the board configuration info.
1813 *-----------------------------------------------------------------*/
1814 get_sys_info(&board_cfg
);
1816 mfsdr(SDR0_DDR0
, sdr_ddrpll
);
1817 sdram_freq
= ((board_cfg
.freqPLB
) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll
));
1819 /*------------------------------------------------------------------
1820 * Handle the timing. We need to find the worst case timing of all
1821 * the dimm modules installed.
1822 *-----------------------------------------------------------------*/
1834 /* loop through all the DIMM slots on the board */
1835 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
1836 /* If a dimm is installed in a particular slot ... */
1837 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
1838 if (dimm_populated
[dimm_num
] == SDRAM_DDR2
)
1843 t_rcd_ns
= max(t_rcd_ns
, spd_read(iic0_dimm_addr
[dimm_num
], 29) >> 2);
1844 t_rrd_ns
= max(t_rrd_ns
, spd_read(iic0_dimm_addr
[dimm_num
], 28) >> 2);
1845 t_rp_ns
= max(t_rp_ns
, spd_read(iic0_dimm_addr
[dimm_num
], 27) >> 2);
1846 t_ras_ns
= max(t_ras_ns
, spd_read(iic0_dimm_addr
[dimm_num
], 30));
1847 t_rc_ns
= max(t_rc_ns
, spd_read(iic0_dimm_addr
[dimm_num
], 41));
1848 t_rfc_ns
= max(t_rfc_ns
, spd_read(iic0_dimm_addr
[dimm_num
], 42));
1852 /*------------------------------------------------------------------
1853 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1854 *-----------------------------------------------------------------*/
1855 mfsdram(SDRAM_SDTR1
, sdtr1
);
1856 sdtr1
&= ~(SDRAM_SDTR1_LDOF_MASK
| SDRAM_SDTR1_RTW_MASK
|
1857 SDRAM_SDTR1_WTWO_MASK
| SDRAM_SDTR1_RTRO_MASK
);
1859 /* default values */
1860 sdtr1
|= SDRAM_SDTR1_LDOF_2_CLK
;
1861 sdtr1
|= SDRAM_SDTR1_RTW_2_CLK
;
1863 /* normal operations */
1864 sdtr1
|= SDRAM_SDTR1_WTWO_0_CLK
;
1865 sdtr1
|= SDRAM_SDTR1_RTRO_1_CLK
;
1867 mtsdram(SDRAM_SDTR1
, sdtr1
);
1869 /*------------------------------------------------------------------
1870 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1871 *-----------------------------------------------------------------*/
1872 mfsdram(SDRAM_SDTR2
, sdtr2
);
1873 sdtr2
&= ~(SDRAM_SDTR2_RCD_MASK
| SDRAM_SDTR2_WTR_MASK
|
1874 SDRAM_SDTR2_XSNR_MASK
| SDRAM_SDTR2_WPC_MASK
|
1875 SDRAM_SDTR2_RPC_MASK
| SDRAM_SDTR2_RP_MASK
|
1876 SDRAM_SDTR2_RRD_MASK
);
1879 * convert t_rcd from nanoseconds to ddr clocks
1880 * round up if necessary
1882 t_rcd_clk
= MULDIV64(sdram_freq
, t_rcd_ns
, ONE_BILLION
);
1883 ddr_check
= MULDIV64(ONE_BILLION
, t_rcd_clk
, t_rcd_ns
);
1884 if (sdram_freq
!= ddr_check
)
1887 switch (t_rcd_clk
) {
1890 sdtr2
|= SDRAM_SDTR2_RCD_1_CLK
;
1893 sdtr2
|= SDRAM_SDTR2_RCD_2_CLK
;
1896 sdtr2
|= SDRAM_SDTR2_RCD_3_CLK
;
1899 sdtr2
|= SDRAM_SDTR2_RCD_4_CLK
;
1902 sdtr2
|= SDRAM_SDTR2_RCD_5_CLK
;
1906 if (sdram_ddr1
== TRUE
) { /* DDR1 */
1907 if (sdram_freq
< 200000000) {
1908 sdtr2
|= SDRAM_SDTR2_WTR_1_CLK
;
1909 sdtr2
|= SDRAM_SDTR2_WPC_2_CLK
;
1910 sdtr2
|= SDRAM_SDTR2_RPC_2_CLK
;
1912 sdtr2
|= SDRAM_SDTR2_WTR_2_CLK
;
1913 sdtr2
|= SDRAM_SDTR2_WPC_3_CLK
;
1914 sdtr2
|= SDRAM_SDTR2_RPC_2_CLK
;
1917 /* loop through all the DIMM slots on the board */
1918 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
1919 /* If a dimm is installed in a particular slot ... */
1920 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
1921 t_wpc_ns
= max(t_wtr_ns
, spd_read(iic0_dimm_addr
[dimm_num
], 36) >> 2);
1922 t_wtr_ns
= max(t_wtr_ns
, spd_read(iic0_dimm_addr
[dimm_num
], 37) >> 2);
1923 t_rpc_ns
= max(t_rpc_ns
, spd_read(iic0_dimm_addr
[dimm_num
], 38) >> 2);
1928 * convert from nanoseconds to ddr clocks
1929 * round up if necessary
1931 t_wpc_clk
= MULDIV64(sdram_freq
, t_wpc_ns
, ONE_BILLION
);
1932 ddr_check
= MULDIV64(ONE_BILLION
, t_wpc_clk
, t_wpc_ns
);
1933 if (sdram_freq
!= ddr_check
)
1936 switch (t_wpc_clk
) {
1940 sdtr2
|= SDRAM_SDTR2_WPC_2_CLK
;
1943 sdtr2
|= SDRAM_SDTR2_WPC_3_CLK
;
1946 sdtr2
|= SDRAM_SDTR2_WPC_4_CLK
;
1949 sdtr2
|= SDRAM_SDTR2_WPC_5_CLK
;
1952 sdtr2
|= SDRAM_SDTR2_WPC_6_CLK
;
1957 * convert from nanoseconds to ddr clocks
1958 * round up if necessary
1960 t_wtr_clk
= MULDIV64(sdram_freq
, t_wtr_ns
, ONE_BILLION
);
1961 ddr_check
= MULDIV64(ONE_BILLION
, t_wtr_clk
, t_wtr_ns
);
1962 if (sdram_freq
!= ddr_check
)
1965 switch (t_wtr_clk
) {
1968 sdtr2
|= SDRAM_SDTR2_WTR_1_CLK
;
1971 sdtr2
|= SDRAM_SDTR2_WTR_2_CLK
;
1974 sdtr2
|= SDRAM_SDTR2_WTR_3_CLK
;
1977 sdtr2
|= SDRAM_SDTR2_WTR_4_CLK
;
1982 * convert from nanoseconds to ddr clocks
1983 * round up if necessary
1985 t_rpc_clk
= MULDIV64(sdram_freq
, t_rpc_ns
, ONE_BILLION
);
1986 ddr_check
= MULDIV64(ONE_BILLION
, t_rpc_clk
, t_rpc_ns
);
1987 if (sdram_freq
!= ddr_check
)
1990 switch (t_rpc_clk
) {
1994 sdtr2
|= SDRAM_SDTR2_RPC_2_CLK
;
1997 sdtr2
|= SDRAM_SDTR2_RPC_3_CLK
;
2000 sdtr2
|= SDRAM_SDTR2_RPC_4_CLK
;
2006 sdtr2
|= SDRAM_SDTR2_XSNR_16_CLK
;
2009 * convert t_rrd from nanoseconds to ddr clocks
2010 * round up if necessary
2012 t_rrd_clk
= MULDIV64(sdram_freq
, t_rrd_ns
, ONE_BILLION
);
2013 ddr_check
= MULDIV64(ONE_BILLION
, t_rrd_clk
, t_rrd_ns
);
2014 if (sdram_freq
!= ddr_check
)
2018 sdtr2
|= SDRAM_SDTR2_RRD_3_CLK
;
2020 sdtr2
|= SDRAM_SDTR2_RRD_2_CLK
;
2023 * convert t_rp from nanoseconds to ddr clocks
2024 * round up if necessary
2026 t_rp_clk
= MULDIV64(sdram_freq
, t_rp_ns
, ONE_BILLION
);
2027 ddr_check
= MULDIV64(ONE_BILLION
, t_rp_clk
, t_rp_ns
);
2028 if (sdram_freq
!= ddr_check
)
2036 sdtr2
|= SDRAM_SDTR2_RP_3_CLK
;
2039 sdtr2
|= SDRAM_SDTR2_RP_4_CLK
;
2042 sdtr2
|= SDRAM_SDTR2_RP_5_CLK
;
2045 sdtr2
|= SDRAM_SDTR2_RP_6_CLK
;
2048 sdtr2
|= SDRAM_SDTR2_RP_7_CLK
;
2052 mtsdram(SDRAM_SDTR2
, sdtr2
);
2054 /*------------------------------------------------------------------
2055 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2056 *-----------------------------------------------------------------*/
2057 mfsdram(SDRAM_SDTR3
, sdtr3
);
2058 sdtr3
&= ~(SDRAM_SDTR3_RAS_MASK
| SDRAM_SDTR3_RC_MASK
|
2059 SDRAM_SDTR3_XCS_MASK
| SDRAM_SDTR3_RFC_MASK
);
2062 * convert t_ras from nanoseconds to ddr clocks
2063 * round up if necessary
2065 t_ras_clk
= MULDIV64(sdram_freq
, t_ras_ns
, ONE_BILLION
);
2066 ddr_check
= MULDIV64(ONE_BILLION
, t_ras_clk
, t_ras_ns
);
2067 if (sdram_freq
!= ddr_check
)
2070 sdtr3
|= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk
);
2073 * convert t_rc from nanoseconds to ddr clocks
2074 * round up if necessary
2076 t_rc_clk
= MULDIV64(sdram_freq
, t_rc_ns
, ONE_BILLION
);
2077 ddr_check
= MULDIV64(ONE_BILLION
, t_rc_clk
, t_rc_ns
);
2078 if (sdram_freq
!= ddr_check
)
2081 sdtr3
|= SDRAM_SDTR3_RC_ENCODE(t_rc_clk
);
2083 /* default xcs value */
2084 sdtr3
|= SDRAM_SDTR3_XCS
;
2087 * convert t_rfc from nanoseconds to ddr clocks
2088 * round up if necessary
2090 t_rfc_clk
= MULDIV64(sdram_freq
, t_rfc_ns
, ONE_BILLION
);
2091 ddr_check
= MULDIV64(ONE_BILLION
, t_rfc_clk
, t_rfc_ns
);
2092 if (sdram_freq
!= ddr_check
)
2095 sdtr3
|= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk
);
2097 mtsdram(SDRAM_SDTR3
, sdtr3
);
2100 /*-----------------------------------------------------------------------------+
2102 *-----------------------------------------------------------------------------*/
2103 static void program_bxcf(unsigned long *dimm_populated
,
2104 unsigned char *iic0_dimm_addr
,
2105 unsigned long num_dimm_banks
)
2107 unsigned long dimm_num
;
2108 unsigned long num_col_addr
;
2109 unsigned long num_ranks
;
2110 unsigned long num_banks
;
2112 unsigned long ind_rank
;
2114 unsigned long ind_bank
;
2115 unsigned long bank_0_populated
;
2117 /*------------------------------------------------------------------
2118 * Set the BxCF regs. First, wipe out the bank config registers.
2119 *-----------------------------------------------------------------*/
2120 mtsdram(SDRAM_MB0CF
, 0x00000000);
2121 mtsdram(SDRAM_MB1CF
, 0x00000000);
2122 mtsdram(SDRAM_MB2CF
, 0x00000000);
2123 mtsdram(SDRAM_MB3CF
, 0x00000000);
2125 mode
= SDRAM_BXCF_M_BE_ENABLE
;
2127 bank_0_populated
= 0;
2129 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
2130 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
2131 num_col_addr
= spd_read(iic0_dimm_addr
[dimm_num
], 4);
2132 num_ranks
= spd_read(iic0_dimm_addr
[dimm_num
], 5);
2133 if ((spd_read(iic0_dimm_addr
[dimm_num
], 2)) == 0x08)
2134 num_ranks
= (num_ranks
& 0x0F) +1;
2136 num_ranks
= num_ranks
& 0x0F;
2138 num_banks
= spd_read(iic0_dimm_addr
[dimm_num
], 17);
2140 for (ind_bank
= 0; ind_bank
< 2; ind_bank
++) {
2145 switch (num_col_addr
) {
2147 mode
|= (SDRAM_BXCF_M_AM_0
+ ind
);
2150 mode
|= (SDRAM_BXCF_M_AM_1
+ ind
);
2153 mode
|= (SDRAM_BXCF_M_AM_2
+ ind
);
2156 mode
|= (SDRAM_BXCF_M_AM_3
+ ind
);
2159 mode
|= (SDRAM_BXCF_M_AM_4
+ ind
);
2162 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2163 (unsigned int)dimm_num
);
2164 printf("ERROR: Unsupported value for number of "
2165 "column addresses: %d.\n", (unsigned int)num_col_addr
);
2166 printf("Replace the DIMM module with a supported DIMM.\n\n");
2167 spd_ddr_init_hang ();
2171 if ((dimm_populated
[dimm_num
] != SDRAM_NONE
)&& (dimm_num
==1))
2172 bank_0_populated
= 1;
2174 for (ind_rank
= 0; ind_rank
< num_ranks
; ind_rank
++) {
2175 mtsdram(SDRAM_MB0CF
+
2176 ((dimm_num
+ bank_0_populated
+ ind_rank
) << 2),
2183 /*------------------------------------------------------------------
2184 * program memory queue.
2185 *-----------------------------------------------------------------*/
2186 static void program_memory_queue(unsigned long *dimm_populated
,
2187 unsigned char *iic0_dimm_addr
,
2188 unsigned long num_dimm_banks
)
2190 unsigned long dimm_num
;
2191 phys_size_t rank_base_addr
;
2192 unsigned long rank_reg
;
2193 phys_size_t rank_size_bytes
;
2194 unsigned long rank_size_id
;
2195 unsigned long num_ranks
;
2196 unsigned long baseadd_size
;
2198 unsigned long bank_0_populated
= 0;
2199 phys_size_t total_size
= 0;
2201 /*------------------------------------------------------------------
2202 * Reset the rank_base_address.
2203 *-----------------------------------------------------------------*/
2204 rank_reg
= SDRAM_R0BAS
;
2206 rank_base_addr
= 0x00000000;
2208 for (dimm_num
= 0; dimm_num
< num_dimm_banks
; dimm_num
++) {
2209 if (dimm_populated
[dimm_num
] != SDRAM_NONE
) {
2210 num_ranks
= spd_read(iic0_dimm_addr
[dimm_num
], 5);
2211 if ((spd_read(iic0_dimm_addr
[dimm_num
], 2)) == 0x08)
2212 num_ranks
= (num_ranks
& 0x0F) + 1;
2214 num_ranks
= num_ranks
& 0x0F;
2216 rank_size_id
= spd_read(iic0_dimm_addr
[dimm_num
], 31);
2218 /*------------------------------------------------------------------
2220 *-----------------------------------------------------------------*/
2222 switch (rank_size_id
) {
2224 baseadd_size
|= SDRAM_RXBAS_SDSZ_1024
;
2228 baseadd_size
|= SDRAM_RXBAS_SDSZ_2048
;
2232 baseadd_size
|= SDRAM_RXBAS_SDSZ_4096
;
2236 baseadd_size
|= SDRAM_RXBAS_SDSZ_32
;
2240 baseadd_size
|= SDRAM_RXBAS_SDSZ_64
;
2244 baseadd_size
|= SDRAM_RXBAS_SDSZ_128
;
2248 baseadd_size
|= SDRAM_RXBAS_SDSZ_256
;
2252 baseadd_size
|= SDRAM_RXBAS_SDSZ_512
;
2256 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2257 (unsigned int)dimm_num
);
2258 printf("ERROR: Unsupported value for the banksize: %d.\n",
2259 (unsigned int)rank_size_id
);
2260 printf("Replace the DIMM module with a supported DIMM.\n\n");
2261 spd_ddr_init_hang ();
2263 rank_size_bytes
= total_size
<< 20;
2265 if ((dimm_populated
[dimm_num
] != SDRAM_NONE
) && (dimm_num
== 1))
2266 bank_0_populated
= 1;
2268 for (i
= 0; i
< num_ranks
; i
++) {
2269 mtdcr_any(rank_reg
+i
+dimm_num
+bank_0_populated
,
2270 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr
) |
2272 rank_base_addr
+= rank_size_bytes
;
2277 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2278 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2279 defined(CONFIG_460SX)
2281 * Enable high bandwidth access
2282 * This is currently not used, but with this setup
2283 * it is possible to use it later on in e.g. the Linux
2284 * EMAC driver for performance gain.
2286 mtdcr(SDRAM_PLBADDULL
, 0x00000000); /* MQ0_BAUL */
2287 mtdcr(SDRAM_PLBADDUHB
, 0x00000008); /* MQ0_BAUH */
2290 * Set optimal value for Memory Queue HB/LL Configuration registers
2292 mtdcr(SDRAM_CONF1HB
, (mfdcr(SDRAM_CONF1HB
) & ~SDRAM_CONF1HB_MASK
) |
2293 SDRAM_CONF1HB_AAFR
| SDRAM_CONF1HB_RPEN
| SDRAM_CONF1HB_RFTE
|
2294 SDRAM_CONF1HB_RPLM
| SDRAM_CONF1HB_WRCL
);
2295 mtdcr(SDRAM_CONF1LL
, (mfdcr(SDRAM_CONF1LL
) & ~SDRAM_CONF1LL_MASK
) |
2296 SDRAM_CONF1LL_AAFR
| SDRAM_CONF1LL_RPEN
| SDRAM_CONF1LL_RFTE
|
2297 SDRAM_CONF1LL_RPLM
);
2298 mtdcr(SDRAM_CONFPATHB
, mfdcr(SDRAM_CONFPATHB
) | SDRAM_CONFPATHB_TPEN
);
2302 #ifdef CONFIG_DDR_ECC
2303 /*-----------------------------------------------------------------------------+
2305 *-----------------------------------------------------------------------------*/
2306 static void program_ecc(unsigned long *dimm_populated
,
2307 unsigned char *iic0_dimm_addr
,
2308 unsigned long num_dimm_banks
,
2309 unsigned long tlb_word2_i_value
)
2311 unsigned long dimm_num
;
2315 /* loop through all the DIMM slots on the board */
2316 for (dimm_num
= 0; dimm_num
< MAXDIMMS
; dimm_num
++) {
2317 /* If a dimm is installed in a particular slot ... */
2318 if (dimm_populated
[dimm_num
] != SDRAM_NONE
)
2319 ecc
= max(ecc
, spd_read(iic0_dimm_addr
[dimm_num
], 11));
2324 do_program_ecc(tlb_word2_i_value
);
2328 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2329 /*-----------------------------------------------------------------------------+
2330 * program_DQS_calibration.
2331 *-----------------------------------------------------------------------------*/
2332 static void program_DQS_calibration(unsigned long *dimm_populated
,
2333 unsigned char *iic0_dimm_addr
,
2334 unsigned long num_dimm_banks
)
2338 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2339 mtsdram(SDRAM_RQDC
, 0x80000037);
2340 mtsdram(SDRAM_RDCC
, 0x40000000);
2341 mtsdram(SDRAM_RFDC
, 0x000001DF);
2345 /*------------------------------------------------------------------
2346 * Program RDCC register
2347 * Read sample cycle auto-update enable
2348 *-----------------------------------------------------------------*/
2350 mfsdram(SDRAM_RDCC
, val
);
2352 (val
& ~(SDRAM_RDCC_RDSS_MASK
| SDRAM_RDCC_RSAE_MASK
))
2353 | SDRAM_RDCC_RSAE_ENABLE
);
2355 /*------------------------------------------------------------------
2356 * Program RQDC register
2357 * Internal DQS delay mechanism enable
2358 *-----------------------------------------------------------------*/
2359 mtsdram(SDRAM_RQDC
, (SDRAM_RQDC_RQDE_ENABLE
|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2361 /*------------------------------------------------------------------
2362 * Program RFDC register
2363 * Set Feedback Fractional Oversample
2364 * Auto-detect read sample cycle enable
2365 * Set RFOS to 1/4 of memclk cycle (0x3f)
2366 *-----------------------------------------------------------------*/
2367 mfsdram(SDRAM_RFDC
, val
);
2369 (val
& ~(SDRAM_RFDC_ARSE_MASK
| SDRAM_RFDC_RFOS_MASK
|
2370 SDRAM_RFDC_RFFD_MASK
))
2371 | (SDRAM_RFDC_ARSE_ENABLE
| SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2372 SDRAM_RFDC_RFFD_ENCODE(0)));
2374 DQS_calibration_process();
2378 static int short_mem_test(void)
2385 phys_size_t base_addr
;
2386 u32 test
[NUMMEMTESTS
][NUMMEMWORDS
] = {
2387 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2388 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2389 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2390 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2391 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2392 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2393 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2394 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2395 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2396 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2397 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2398 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2399 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2400 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2401 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2402 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2405 for (bxcr_num
= 0; bxcr_num
< MAXBXCF
; bxcr_num
++) {
2406 mfsdram(SDRAM_MB0CF
+ (bxcr_num
<< 2), bxcf
);
2409 if ((bxcf
& SDRAM_BXCF_M_BE_MASK
) == SDRAM_BXCF_M_BE_ENABLE
) {
2410 /* Bank is enabled */
2413 * Only run test on accessable memory (below 2GB)
2415 base_addr
= SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS
+bxcr_num
));
2416 if (base_addr
>= CONFIG_MAX_MEM_MAPPED
)
2419 /*------------------------------------------------------------------
2420 * Run the short memory test.
2421 *-----------------------------------------------------------------*/
2422 membase
= (u32
*)(u32
)base_addr
;
2424 for (i
= 0; i
< NUMMEMTESTS
; i
++) {
2425 for (j
= 0; j
< NUMMEMWORDS
; j
++) {
2426 membase
[j
] = test
[i
][j
];
2427 ppcDcbf((u32
)&(membase
[j
]));
2430 for (l
=0; l
<NUMLOOPS
; l
++) {
2431 for (j
= 0; j
< NUMMEMWORDS
; j
++) {
2432 if (membase
[j
] != test
[i
][j
]) {
2433 ppcDcbf((u32
)&(membase
[j
]));
2436 ppcDcbf((u32
)&(membase
[j
]));
2441 } /* if bank enabled */
2442 } /* for bxcf_num */
2447 #ifndef HARD_CODED_DQS
2448 /*-----------------------------------------------------------------------------+
2449 * DQS_calibration_process.
2450 *-----------------------------------------------------------------------------*/
2451 static void DQS_calibration_process(void)
2453 unsigned long rfdc_reg
;
2459 unsigned long begin_rqfd
[MAXRANKS
];
2460 unsigned long begin_rffd
[MAXRANKS
];
2461 unsigned long end_rqfd
[MAXRANKS
];
2462 unsigned long end_rffd
[MAXRANKS
];
2464 unsigned long dlycal
;
2465 unsigned long dly_val
;
2466 unsigned long max_pass_length
;
2467 unsigned long current_pass_length
;
2468 unsigned long current_fail_length
;
2469 unsigned long current_start
;
2471 unsigned char fail_found
;
2472 unsigned char pass_found
;
2473 #if !defined(CONFIG_DDR_RQDC_FIXED)
2479 char str
[] = "Auto calibration -";
2480 char slash
[] = "\\|/-\\|/-";
2482 /*------------------------------------------------------------------
2483 * Test to determine the best read clock delay tuning bits.
2485 * Before the DDR controller can be used, the read clock delay needs to be
2486 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2487 * This value cannot be hardcoded into the program because it changes
2488 * depending on the board's setup and environment.
2489 * To do this, all delay values are tested to see if they
2490 * work or not. By doing this, you get groups of fails with groups of
2491 * passing values. The idea is to find the start and end of a passing
2492 * window and take the center of it to use as the read clock delay.
2494 * A failure has to be seen first so that when we hit a pass, we know
2495 * that it is truely the start of the window. If we get passing values
2496 * to start off with, we don't know if we are at the start of the window.
2498 * The code assumes that a failure will always be found.
2499 * If a failure is not found, there is no easy way to get the middle
2500 * of the passing window. I guess we can pretty much pick any value
2501 * but some values will be better than others. Since the lowest speed
2502 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2503 * from experimentation it is safe to say you will always have a failure.
2504 *-----------------------------------------------------------------*/
2506 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2507 rqfd_start
= 64; /* test-only: don't know if this is the _best_ start value */
2512 mfsdram(SDRAM_RQDC
, rqdc_reg
);
2513 mtsdram(SDRAM_RQDC
, (rqdc_reg
& ~SDRAM_RQDC_RQFD_MASK
) |
2514 SDRAM_RQDC_RQFD_ENCODE(rqfd_start
));
2515 #else /* CONFIG_DDR_RQDC_FIXED */
2517 * On Katmai the complete auto-calibration somehow doesn't seem to
2518 * produce the best results, meaning optimal values for RQFD/RFFD.
2519 * This was discovered by GDA using a high bandwidth scope,
2520 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2521 * so now on Katmai "only" RFFD is auto-calibrated.
2523 mtsdram(SDRAM_RQDC
, CONFIG_DDR_RQDC_FIXED
);
2524 #endif /* CONFIG_DDR_RQDC_FIXED */
2536 window_found
= FALSE
;
2538 max_pass_length
= 0;
2541 current_pass_length
= 0;
2542 current_fail_length
= 0;
2544 window_found
= FALSE
;
2549 * get the delay line calibration register value
2551 mfsdram(SDRAM_DLCR
, dlycal
);
2552 dly_val
= SDRAM_DLYCAL_DLCV_DECODE(dlycal
) << 2;
2554 for (rffd
= 0; rffd
<= SDRAM_RFDC_RFFD_MAX
; rffd
++) {
2555 mfsdram(SDRAM_RFDC
, rfdc_reg
);
2556 rfdc_reg
&= ~(SDRAM_RFDC_RFFD_MASK
);
2558 /*------------------------------------------------------------------
2559 * Set the timing reg for the test.
2560 *-----------------------------------------------------------------*/
2561 mtsdram(SDRAM_RFDC
, rfdc_reg
| SDRAM_RFDC_RFFD_ENCODE(rffd
));
2563 /*------------------------------------------------------------------
2564 * See if the rffd value passed.
2565 *-----------------------------------------------------------------*/
2566 if (short_mem_test()) {
2567 if (fail_found
== TRUE
) {
2569 if (current_pass_length
== 0)
2570 current_start
= rffd
;
2572 current_fail_length
= 0;
2573 current_pass_length
++;
2575 if (current_pass_length
> max_pass_length
) {
2576 max_pass_length
= current_pass_length
;
2577 max_start
= current_start
;
2582 current_pass_length
= 0;
2583 current_fail_length
++;
2585 if (current_fail_length
>= (dly_val
>> 2)) {
2586 if (fail_found
== FALSE
) {
2588 } else if (pass_found
== TRUE
) {
2589 window_found
= TRUE
;
2596 /*------------------------------------------------------------------
2597 * Set the average RFFD value
2598 *-----------------------------------------------------------------*/
2599 rffd_average
= ((max_start
+ max_end
) >> 1);
2601 if (rffd_average
< 0)
2604 if (rffd_average
> SDRAM_RFDC_RFFD_MAX
)
2605 rffd_average
= SDRAM_RFDC_RFFD_MAX
;
2606 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2607 mtsdram(SDRAM_RFDC
, rfdc_reg
| SDRAM_RFDC_RFFD_ENCODE(rffd_average
));
2609 #if !defined(CONFIG_DDR_RQDC_FIXED)
2610 max_pass_length
= 0;
2613 current_pass_length
= 0;
2614 current_fail_length
= 0;
2616 window_found
= FALSE
;
2620 for (rqfd
= 0; rqfd
<= SDRAM_RQDC_RQFD_MAX
; rqfd
++) {
2621 mfsdram(SDRAM_RQDC
, rqdc_reg
);
2622 rqdc_reg
&= ~(SDRAM_RQDC_RQFD_MASK
);
2624 /*------------------------------------------------------------------
2625 * Set the timing reg for the test.
2626 *-----------------------------------------------------------------*/
2627 mtsdram(SDRAM_RQDC
, rqdc_reg
| SDRAM_RQDC_RQFD_ENCODE(rqfd
));
2629 /*------------------------------------------------------------------
2630 * See if the rffd value passed.
2631 *-----------------------------------------------------------------*/
2632 if (short_mem_test()) {
2633 if (fail_found
== TRUE
) {
2635 if (current_pass_length
== 0)
2636 current_start
= rqfd
;
2638 current_fail_length
= 0;
2639 current_pass_length
++;
2641 if (current_pass_length
> max_pass_length
) {
2642 max_pass_length
= current_pass_length
;
2643 max_start
= current_start
;
2648 current_pass_length
= 0;
2649 current_fail_length
++;
2651 if (fail_found
== FALSE
) {
2653 } else if (pass_found
== TRUE
) {
2654 window_found
= TRUE
;
2660 rqfd_average
= ((max_start
+ max_end
) >> 1);
2662 /*------------------------------------------------------------------
2663 * Make sure we found the valid read passing window. Halt if not
2664 *-----------------------------------------------------------------*/
2665 if (window_found
== FALSE
) {
2666 if (rqfd_start
< SDRAM_RQDC_RQFD_MAX
) {
2668 putc(slash
[loopi
++ % 8]);
2670 /* try again from with a different RQFD start value */
2672 goto calibration_loop
;
2675 printf("\nERROR: Cannot determine a common read delay for the "
2676 "DIMM(s) installed.\n");
2677 debug("%s[%d] ERROR : \n", __FUNCTION__
,__LINE__
);
2678 ppc4xx_ibm_ddr2_register_dump();
2679 spd_ddr_init_hang ();
2682 if (rqfd_average
< 0)
2685 if (rqfd_average
> SDRAM_RQDC_RQFD_MAX
)
2686 rqfd_average
= SDRAM_RQDC_RQFD_MAX
;
2689 (rqdc_reg
& ~SDRAM_RQDC_RQFD_MASK
) |
2690 SDRAM_RQDC_RQFD_ENCODE(rqfd_average
));
2692 blank_string(strlen(str
));
2693 #endif /* CONFIG_DDR_RQDC_FIXED */
2696 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2697 * PowerPC440SP/SPe DDR2 application note:
2698 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2700 mfsdram(SDRAM_RTSR
, val
);
2701 if ((val
& SDRAM_RTSR_TRK1SM_MASK
) == SDRAM_RTSR_TRK1SM_ATPLS1
) {
2702 mfsdram(SDRAM_RDCC
, val
);
2703 if ((val
& SDRAM_RDCC_RDSS_MASK
) != SDRAM_RDCC_RDSS_T4
) {
2705 mtsdram(SDRAM_RDCC
, val
);
2709 mfsdram(SDRAM_DLCR
, val
);
2710 debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__
, __LINE__
, val
);
2711 mfsdram(SDRAM_RQDC
, val
);
2712 debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__
, __LINE__
, val
);
2713 mfsdram(SDRAM_RFDC
, val
);
2714 debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__
, __LINE__
, val
);
2715 mfsdram(SDRAM_RDCC
, val
);
2716 debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__
, __LINE__
, val
);
2718 #else /* calibration test with hardvalues */
2719 /*-----------------------------------------------------------------------------+
2720 * DQS_calibration_process.
2721 *-----------------------------------------------------------------------------*/
2722 static void test(void)
2724 unsigned long dimm_num
;
2725 unsigned long ecc_temp
;
2727 unsigned long *membase
;
2728 unsigned long bxcf
[MAXRANKS
];
2731 char begin_found
[MAXDIMMS
];
2732 char end_found
[MAXDIMMS
];
2733 char search_end
[MAXDIMMS
];
2734 unsigned long test
[NUMMEMTESTS
][NUMMEMWORDS
] = {
2735 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2736 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2737 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2738 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2739 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2740 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2741 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2742 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2743 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2744 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2745 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2746 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2747 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2748 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2749 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2750 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2752 /*------------------------------------------------------------------
2753 * Test to determine the best read clock delay tuning bits.
2755 * Before the DDR controller can be used, the read clock delay needs to be
2756 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2757 * This value cannot be hardcoded into the program because it changes
2758 * depending on the board's setup and environment.
2759 * To do this, all delay values are tested to see if they
2760 * work or not. By doing this, you get groups of fails with groups of
2761 * passing values. The idea is to find the start and end of a passing
2762 * window and take the center of it to use as the read clock delay.
2764 * A failure has to be seen first so that when we hit a pass, we know
2765 * that it is truely the start of the window. If we get passing values
2766 * to start off with, we don't know if we are at the start of the window.
2768 * The code assumes that a failure will always be found.
2769 * If a failure is not found, there is no easy way to get the middle
2770 * of the passing window. I guess we can pretty much pick any value
2771 * but some values will be better than others. Since the lowest speed
2772 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2773 * from experimentation it is safe to say you will always have a failure.
2774 *-----------------------------------------------------------------*/
2775 mfsdram(SDRAM_MCOPT1
, ecc_temp
);
2776 ecc_temp
&= SDRAM_MCOPT1_MCHK_MASK
;
2777 mfsdram(SDRAM_MCOPT1
, val
);
2778 mtsdram(SDRAM_MCOPT1
, (val
& ~SDRAM_MCOPT1_MCHK_MASK
) |
2779 SDRAM_MCOPT1_MCHK_NON
);
2781 window_found
= FALSE
;
2782 begin_found
[0] = FALSE
;
2783 end_found
[0] = FALSE
;
2784 search_end
[0] = FALSE
;
2785 begin_found
[1] = FALSE
;
2786 end_found
[1] = FALSE
;
2787 search_end
[1] = FALSE
;
2789 for (dimm_num
= 0; dimm_num
< MAXDIMMS
; dimm_num
++) {
2790 mfsdram(SDRAM_MB0CF
+ (bxcr_num
<< 2), bxcf
[bxcr_num
]);
2793 if ((bxcf
[dimm_num
] & SDRAM_BXCF_M_BE_MASK
) == SDRAM_BXCF_M_BE_ENABLE
) {
2795 /* Bank is enabled */
2797 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS
+dimm_num
)));
2799 /*------------------------------------------------------------------
2800 * Run the short memory test.
2801 *-----------------------------------------------------------------*/
2802 for (i
= 0; i
< NUMMEMTESTS
; i
++) {
2803 for (j
= 0; j
< NUMMEMWORDS
; j
++) {
2804 membase
[j
] = test
[i
][j
];
2805 ppcDcbf((u32
)&(membase
[j
]));
2808 for (j
= 0; j
< NUMMEMWORDS
; j
++) {
2809 if (membase
[j
] != test
[i
][j
]) {
2810 ppcDcbf((u32
)&(membase
[j
]));
2813 ppcDcbf((u32
)&(membase
[j
]));
2816 if (j
< NUMMEMWORDS
)
2820 /*------------------------------------------------------------------
2821 * See if the rffd value passed.
2822 *-----------------------------------------------------------------*/
2823 if (i
< NUMMEMTESTS
) {
2824 if ((end_found
[dimm_num
] == FALSE
) &&
2825 (search_end
[dimm_num
] == TRUE
)) {
2826 end_found
[dimm_num
] = TRUE
;
2828 if ((end_found
[0] == TRUE
) &&
2829 (end_found
[1] == TRUE
))
2832 if (begin_found
[dimm_num
] == FALSE
) {
2833 begin_found
[dimm_num
] = TRUE
;
2834 search_end
[dimm_num
] = TRUE
;
2838 begin_found
[dimm_num
] = TRUE
;
2839 end_found
[dimm_num
] = TRUE
;
2843 if ((begin_found
[0] == TRUE
) && (begin_found
[1] == TRUE
))
2844 window_found
= TRUE
;
2846 /*------------------------------------------------------------------
2847 * Make sure we found the valid read passing window. Halt if not
2848 *-----------------------------------------------------------------*/
2849 if (window_found
== FALSE
) {
2850 printf("ERROR: Cannot determine a common read delay for the "
2851 "DIMM(s) installed.\n");
2852 spd_ddr_init_hang ();
2855 /*------------------------------------------------------------------
2856 * Restore the ECC variable to what it originally was
2857 *-----------------------------------------------------------------*/
2858 mtsdram(SDRAM_MCOPT1
,
2859 (ppcMfdcr_sdram(SDRAM_MCOPT1
) & ~SDRAM_MCOPT1_MCHK_MASK
)
2862 #endif /* !HARD_CODED_DQS */
2863 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2865 #else /* CONFIG_SPD_EEPROM */
2867 /*-----------------------------------------------------------------------------
2868 * Function: initdram
2869 * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2870 * The configuration is performed using static, compile-
2872 * Configures the PPC405EX(r) and PPC460EX/GT
2873 *---------------------------------------------------------------------------*/
2874 phys_size_t
initdram(int board_type
)
2877 * Only run this SDRAM init code once. For NAND booting
2878 * targets like Kilauea, we call initdram() early from the
2879 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2880 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2881 * which calls initdram() again. This time the controller
2882 * mustn't be reconfigured again since we're already running
2885 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2888 #if defined(CONFIG_440)
2889 mtdcr(SDRAM_R0BAS
, CONFIG_SYS_SDRAM_R0BAS
);
2890 mtdcr(SDRAM_R1BAS
, CONFIG_SYS_SDRAM_R1BAS
);
2891 mtdcr(SDRAM_R2BAS
, CONFIG_SYS_SDRAM_R2BAS
);
2892 mtdcr(SDRAM_R3BAS
, CONFIG_SYS_SDRAM_R3BAS
);
2893 mtdcr(SDRAM_PLBADDULL
, CONFIG_SYS_SDRAM_PLBADDULL
); /* MQ0_BAUL */
2894 mtdcr(SDRAM_PLBADDUHB
, CONFIG_SYS_SDRAM_PLBADDUHB
); /* MQ0_BAUH */
2895 mtdcr(SDRAM_CONF1LL
, CONFIG_SYS_SDRAM_CONF1LL
);
2896 mtdcr(SDRAM_CONF1HB
, CONFIG_SYS_SDRAM_CONF1HB
);
2897 mtdcr(SDRAM_CONFPATHB
, CONFIG_SYS_SDRAM_CONFPATHB
);
2900 /* Set Memory Bank Configuration Registers */
2902 mtsdram(SDRAM_MB0CF
, CONFIG_SYS_SDRAM0_MB0CF
);
2903 mtsdram(SDRAM_MB1CF
, CONFIG_SYS_SDRAM0_MB1CF
);
2904 mtsdram(SDRAM_MB2CF
, CONFIG_SYS_SDRAM0_MB2CF
);
2905 mtsdram(SDRAM_MB3CF
, CONFIG_SYS_SDRAM0_MB3CF
);
2907 /* Set Memory Clock Timing Register */
2909 mtsdram(SDRAM_CLKTR
, CONFIG_SYS_SDRAM0_CLKTR
);
2911 /* Set Refresh Time Register */
2913 mtsdram(SDRAM_RTR
, CONFIG_SYS_SDRAM0_RTR
);
2915 /* Set SDRAM Timing Registers */
2917 mtsdram(SDRAM_SDTR1
, CONFIG_SYS_SDRAM0_SDTR1
);
2918 mtsdram(SDRAM_SDTR2
, CONFIG_SYS_SDRAM0_SDTR2
);
2919 mtsdram(SDRAM_SDTR3
, CONFIG_SYS_SDRAM0_SDTR3
);
2921 /* Set Mode and Extended Mode Registers */
2923 mtsdram(SDRAM_MMODE
, CONFIG_SYS_SDRAM0_MMODE
);
2924 mtsdram(SDRAM_MEMODE
, CONFIG_SYS_SDRAM0_MEMODE
);
2926 /* Set Memory Controller Options 1 Register */
2928 mtsdram(SDRAM_MCOPT1
, CONFIG_SYS_SDRAM0_MCOPT1
);
2930 /* Set Manual Initialization Control Registers */
2932 mtsdram(SDRAM_INITPLR0
, CONFIG_SYS_SDRAM0_INITPLR0
);
2933 mtsdram(SDRAM_INITPLR1
, CONFIG_SYS_SDRAM0_INITPLR1
);
2934 mtsdram(SDRAM_INITPLR2
, CONFIG_SYS_SDRAM0_INITPLR2
);
2935 mtsdram(SDRAM_INITPLR3
, CONFIG_SYS_SDRAM0_INITPLR3
);
2936 mtsdram(SDRAM_INITPLR4
, CONFIG_SYS_SDRAM0_INITPLR4
);
2937 mtsdram(SDRAM_INITPLR5
, CONFIG_SYS_SDRAM0_INITPLR5
);
2938 mtsdram(SDRAM_INITPLR6
, CONFIG_SYS_SDRAM0_INITPLR6
);
2939 mtsdram(SDRAM_INITPLR7
, CONFIG_SYS_SDRAM0_INITPLR7
);
2940 mtsdram(SDRAM_INITPLR8
, CONFIG_SYS_SDRAM0_INITPLR8
);
2941 mtsdram(SDRAM_INITPLR9
, CONFIG_SYS_SDRAM0_INITPLR9
);
2942 mtsdram(SDRAM_INITPLR10
, CONFIG_SYS_SDRAM0_INITPLR10
);
2943 mtsdram(SDRAM_INITPLR11
, CONFIG_SYS_SDRAM0_INITPLR11
);
2944 mtsdram(SDRAM_INITPLR12
, CONFIG_SYS_SDRAM0_INITPLR12
);
2945 mtsdram(SDRAM_INITPLR13
, CONFIG_SYS_SDRAM0_INITPLR13
);
2946 mtsdram(SDRAM_INITPLR14
, CONFIG_SYS_SDRAM0_INITPLR14
);
2947 mtsdram(SDRAM_INITPLR15
, CONFIG_SYS_SDRAM0_INITPLR15
);
2949 /* Set On-Die Termination Registers */
2951 mtsdram(SDRAM_CODT
, CONFIG_SYS_SDRAM0_CODT
);
2952 mtsdram(SDRAM_MODT0
, CONFIG_SYS_SDRAM0_MODT0
);
2953 mtsdram(SDRAM_MODT1
, CONFIG_SYS_SDRAM0_MODT1
);
2955 /* Set Write Timing Register */
2957 mtsdram(SDRAM_WRDTR
, CONFIG_SYS_SDRAM0_WRDTR
);
2960 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2961 * SDRAM0_MCOPT2[IPTR] = 1
2964 mtsdram(SDRAM_MCOPT2
, (SDRAM_MCOPT2_SREN_EXIT
|
2965 SDRAM_MCOPT2_IPTR_EXECUTE
));
2968 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2969 * completion of initialization.
2973 mfsdram(SDRAM_MCSTAT
, val
);
2974 } while ((val
& SDRAM_MCSTAT_MIC_MASK
) != SDRAM_MCSTAT_MIC_COMP
);
2976 /* Set Delay Control Registers */
2978 mtsdram(SDRAM_DLCR
, CONFIG_SYS_SDRAM0_DLCR
);
2980 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2981 mtsdram(SDRAM_RDCC
, CONFIG_SYS_SDRAM0_RDCC
);
2982 mtsdram(SDRAM_RQDC
, CONFIG_SYS_SDRAM0_RQDC
);
2983 mtsdram(SDRAM_RFDC
, CONFIG_SYS_SDRAM0_RFDC
);
2984 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2987 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
2990 mfsdram(SDRAM_MCOPT2
, val
);
2991 mtsdram(SDRAM_MCOPT2
, val
| SDRAM_MCOPT2_DCEN_ENABLE
);
2993 #if defined(CONFIG_440)
2995 * Program TLB entries with caches enabled, for best performace
2996 * while auto-calibrating and ECC generation
2998 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM
<< 20), 0);
3001 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3002 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3003 /*------------------------------------------------------------------
3005 +-----------------------------------------------------------------*/
3006 DQS_autocalibration();
3007 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3008 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3010 #if defined(CONFIG_DDR_ECC)
3012 #endif /* defined(CONFIG_DDR_ECC) */
3014 #if defined(CONFIG_440)
3016 * Now after initialization (auto-calibration and ECC generation)
3017 * remove the TLB entries with caches enabled and program again with
3018 * desired cache functionality
3020 remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM
<< 20));
3021 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM
<< 20), MY_TLB_WORD2_I_ENABLE
);
3024 ppc4xx_ibm_ddr2_register_dump();
3026 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3028 * Clear potential errors resulting from auto-calibration.
3029 * If not done, then we could get an interrupt later on when
3030 * exceptions are enabled.
3032 set_mcsr(get_mcsr());
3033 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3035 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3037 return (CONFIG_SYS_MBYTES_SDRAM
<< 20);
3039 #endif /* CONFIG_SPD_EEPROM */
3041 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3042 #if defined(CONFIG_440)
3043 u32
mfdcr_any(u32 dcr
)
3048 case SDRAM_R0BAS
+ 0:
3049 val
= mfdcr(SDRAM_R0BAS
+ 0);
3051 case SDRAM_R0BAS
+ 1:
3052 val
= mfdcr(SDRAM_R0BAS
+ 1);
3054 case SDRAM_R0BAS
+ 2:
3055 val
= mfdcr(SDRAM_R0BAS
+ 2);
3057 case SDRAM_R0BAS
+ 3:
3058 val
= mfdcr(SDRAM_R0BAS
+ 3);
3061 printf("DCR %d not defined in case statement!!!\n", dcr
);
3062 val
= 0; /* just to satisfy the compiler */
3068 void mtdcr_any(u32 dcr
, u32 val
)
3071 case SDRAM_R0BAS
+ 0:
3072 mtdcr(SDRAM_R0BAS
+ 0, val
);
3074 case SDRAM_R0BAS
+ 1:
3075 mtdcr(SDRAM_R0BAS
+ 1, val
);
3077 case SDRAM_R0BAS
+ 2:
3078 mtdcr(SDRAM_R0BAS
+ 2, val
);
3080 case SDRAM_R0BAS
+ 3:
3081 mtdcr(SDRAM_R0BAS
+ 3, val
);
3084 printf("DCR %d not defined in case statement!!!\n", dcr
);
3087 #endif /* defined(CONFIG_440) */
3088 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3090 inline void ppc4xx_ibm_ddr2_register_dump(void)
3093 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3095 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3096 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3097 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS
);
3098 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS
);
3099 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS
);
3100 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS
);
3101 #endif /* (defined(CONFIG_440SP) || ... */
3102 #if defined(CONFIG_405EX)
3103 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR
);
3104 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL
);
3105 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH
);
3106 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ
);
3107 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT
);
3108 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA
);
3109 #endif /* defined(CONFIG_405EX) */
3110 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF
);
3111 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF
);
3112 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF
);
3113 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF
);
3114 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT
);
3115 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1
);
3116 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2
);
3117 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0
);
3118 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1
);
3119 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2
);
3120 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3
);
3121 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT
);
3122 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3123 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3124 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR
);
3125 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS
);
3127 * OPART is only used as a trigger register.
3129 * No data is contained in this register, and reading or writing
3130 * to is can cause bad things to happen (hangs). Just skip it and
3133 printf("%20s = N/A\n", "SDRAM_OPART");
3134 #endif /* defined(CONFIG_440SP) || ... */
3135 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR
);
3136 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0
);
3137 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1
);
3138 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2
);
3139 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3
);
3140 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4
);
3141 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5
);
3142 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6
);
3143 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7
);
3144 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8
);
3145 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9
);
3146 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10
);
3147 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11
);
3148 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12
);
3149 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13
);
3150 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14
);
3151 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15
);
3152 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC
);
3153 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC
);
3154 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC
);
3155 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR
);
3156 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR
);
3157 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR
);
3158 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1
);
3159 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2
);
3160 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3
);
3161 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE
);
3162 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE
);
3163 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES
);
3164 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3165 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3166 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID
);
3167 #endif /* defined(CONFIG_440SP) || ... */
3168 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID
);
3169 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR
);
3170 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR
);
3171 #endif /* defined(DEBUG) */
3174 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */