1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
86 #include <ppc4xx_enet.h>
93 * Only compile for platform with AMCC EMAC ethernet controller and
94 * network support enabled.
95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
97 #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
99 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
100 #error "CONFIG_MII has to be defined!"
103 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
104 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
107 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
108 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
110 /* Ethernet Transmit and Receive Buffers */
112 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
113 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
115 #define ENET_MAX_MTU PKTSIZE
116 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
118 /*-----------------------------------------------------------------------------+
119 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
120 * Interrupt Controller).
121 *-----------------------------------------------------------------------------*/
122 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
123 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
124 #define EMAC_UIC_DEF UIC_ENET
125 #define EMAC_UIC_DEF1 UIC_ENET1
126 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
130 #define BI_PHYMODE_NONE 0
131 #define BI_PHYMODE_ZMII 1
132 #define BI_PHYMODE_RGMII 2
133 #define BI_PHYMODE_GMII 3
134 #define BI_PHYMODE_RTBI 4
135 #define BI_PHYMODE_TBI 5
136 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
137 #define BI_PHYMODE_SMII 6
138 #define BI_PHYMODE_MII 7
141 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
142 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
145 /*-----------------------------------------------------------------------------+
146 * Global variables. TX and RX descriptors and buffers.
147 *-----------------------------------------------------------------------------*/
149 static uint32_t mal_ier
;
151 #if !defined(CONFIG_NET_MULTI)
152 struct eth_device
*emac0_dev
= NULL
;
156 * Get count of EMAC devices (doesn't have to be the max. possible number
157 * supported by the cpu)
159 #if defined(CONFIG_HAS_ETH3)
160 #define LAST_EMAC_NUM 4
161 #elif defined(CONFIG_HAS_ETH2)
162 #define LAST_EMAC_NUM 3
163 #elif defined(CONFIG_HAS_ETH1)
164 #define LAST_EMAC_NUM 2
166 #define LAST_EMAC_NUM 1
169 /* normal boards start with EMAC0 */
170 #if !defined(CONFIG_EMAC_NR_START)
171 #define CONFIG_EMAC_NR_START 0
174 /*-----------------------------------------------------------------------------+
175 * Prototypes and externals.
176 *-----------------------------------------------------------------------------*/
177 static void enet_rcv (struct eth_device
*dev
, unsigned long malisr
);
179 int enetInt (struct eth_device
*dev
);
180 static void mal_err (struct eth_device
*dev
, unsigned long isr
,
181 unsigned long uic
, unsigned long maldef
,
182 unsigned long mal_errr
);
183 static void emac_err (struct eth_device
*dev
, unsigned long isr
);
185 extern int phy_setup_aneg (char *devname
, unsigned char addr
);
186 extern int emac4xx_miiphy_read (char *devname
, unsigned char addr
,
187 unsigned char reg
, unsigned short *value
);
188 extern int emac4xx_miiphy_write (char *devname
, unsigned char addr
,
189 unsigned char reg
, unsigned short value
);
191 /*-----------------------------------------------------------------------------+
193 | Disable MAL channel, and EMACn
194 +-----------------------------------------------------------------------------*/
195 static void ppc_4xx_eth_halt (struct eth_device
*dev
)
197 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
198 uint32_t failsafe
= 10000;
199 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
203 out32 (EMAC_IER
+ hw_p
->hw_addr
, 0x00000000); /* disable emac interrupts */
205 /* 1st reset MAL channel */
206 /* Note: writing a 0 to a channel has no effect */
207 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
208 mtdcr (maltxcarr
, (MAL_CR_MMSR
>> (hw_p
->devnum
* 2)));
210 mtdcr (maltxcarr
, (MAL_CR_MMSR
>> hw_p
->devnum
));
212 mtdcr (malrxcarr
, (MAL_CR_MMSR
>> hw_p
->devnum
));
215 while (mfdcr (malrxcasr
) & (MAL_CR_MMSR
>> hw_p
->devnum
)) {
216 udelay (1000); /* Delay 1 MS so as not to hammer the register */
223 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
224 /* provide clocks for EMAC internal loopback */
225 mfsdr (sdr_mfr
, mfr
);
226 mfr
|= SDR0_MFR_ETH_CLK_SEL_V(hw_p
->devnum
);
230 out32 (EMAC_M0
+ hw_p
->hw_addr
, EMAC_M0_SRST
);
232 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
233 /* remove clocks for EMAC internal loopback */
234 mfsdr (sdr_mfr
, mfr
);
235 mfr
&= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p
->devnum
);
240 #ifndef CONFIG_NETCONSOLE
241 hw_p
->print_speed
= 1; /* print speed message again next time */
247 #if defined (CONFIG_440GX)
248 int ppc_4xx_eth_setup_bridge(int devnum
, bd_t
* bis
)
251 unsigned long zmiifer
;
252 unsigned long rmiifer
;
254 mfsdr(sdr_pfc1
, pfc1
);
255 pfc1
= SDR0_PFC1_EPS_DECODE(pfc1
);
262 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(0);
263 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(1);
264 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(2);
265 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(3);
266 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
267 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
268 bis
->bi_phymode
[2] = BI_PHYMODE_ZMII
;
269 bis
->bi_phymode
[3] = BI_PHYMODE_ZMII
;
272 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(0);
273 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(1);
274 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(2);
275 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(3);
276 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
277 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
278 bis
->bi_phymode
[2] = BI_PHYMODE_ZMII
;
279 bis
->bi_phymode
[3] = BI_PHYMODE_ZMII
;
282 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(0);
283 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V(2);
284 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
285 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
286 bis
->bi_phymode
[2] = BI_PHYMODE_RGMII
;
287 bis
->bi_phymode
[3] = BI_PHYMODE_NONE
;
290 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(0);
291 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(1);
292 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V (2);
293 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V (3);
294 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
295 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
296 bis
->bi_phymode
[2] = BI_PHYMODE_RGMII
;
297 bis
->bi_phymode
[3] = BI_PHYMODE_RGMII
;
300 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V (0);
301 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V (1);
302 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V (2);
303 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V(3);
304 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
305 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
306 bis
->bi_phymode
[2] = BI_PHYMODE_ZMII
;
307 bis
->bi_phymode
[3] = BI_PHYMODE_RGMII
;
310 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V (0);
311 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V (1);
312 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V(2);
313 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
314 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
315 bis
->bi_phymode
[2] = BI_PHYMODE_RGMII
;
319 zmiifer
= ZMII_FER_MII
<< ZMII_FER_V(devnum
);
321 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
322 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
323 bis
->bi_phymode
[2] = BI_PHYMODE_ZMII
;
324 bis
->bi_phymode
[3] = BI_PHYMODE_ZMII
;
328 /* Ensure we setup mdio for this devnum and ONLY this devnum */
329 zmiifer
|= (ZMII_FER_MDI
) << ZMII_FER_V(devnum
);
331 out32 (ZMII_FER
, zmiifer
);
332 out32 (RGMII_FER
, rmiifer
);
336 #endif /* CONFIG_440_GX */
338 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
339 int ppc_4xx_eth_setup_bridge(int devnum
, bd_t
* bis
)
341 unsigned long zmiifer
=0x0;
344 * Right now only 2*RGMII is supported. Please extend when needed.
350 out32 (ZMII_FER
, 0x00);
351 out32 (RGMII_FER
, 0x00000037);
352 bis
->bi_phymode
[0] = BI_PHYMODE_GMII
;
353 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
356 /* 2 x RGMII ports */
357 out32 (ZMII_FER
, 0x00);
358 out32 (RGMII_FER
, 0x00000055);
359 bis
->bi_phymode
[0] = BI_PHYMODE_RGMII
;
360 bis
->bi_phymode
[1] = BI_PHYMODE_RGMII
;
370 /* Ensure we setup mdio for this devnum and ONLY this devnum */
371 zmiifer
= in32 (ZMII_FER
);
372 zmiifer
|= (ZMII_FER_MDI
) << ZMII_FER_V(devnum
);
373 out32 (ZMII_FER
, zmiifer
);
377 #endif /* CONFIG_440EPX */
379 static int ppc_4xx_eth_init (struct eth_device
*dev
, bd_t
* bis
)
382 unsigned long reg
= 0;
385 unsigned long duplex
;
386 unsigned long failsafe
;
388 unsigned short devnum
;
389 unsigned short reg_short
;
390 #if defined(CONFIG_440GX) || \
391 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
392 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
394 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
395 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
399 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
404 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
406 /* before doing anything, figure out if we have a MAC address */
408 if (memcmp (dev
->enetaddr
, "\0\0\0\0\0\0", 6) == 0) {
409 printf("ERROR: ethaddr not set!\n");
413 #if defined(CONFIG_440GX) || \
414 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
415 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
416 /* Need to get the OPB frequency so we can access the PHY */
417 get_sys_info (&sysinfo
);
421 mtmsr (msr
& ~(MSR_EE
)); /* disable interrupts */
423 devnum
= hw_p
->devnum
;
428 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
429 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
430 * is possible that new packets (without relationship with
431 * current transfer) have got the time to arrived before
432 * netloop calls eth_halt
434 printf ("About preceeding transfer (eth%d):\n"
435 "- Sent packet number %d\n"
436 "- Received packet number %d\n"
437 "- Handled packet number %d\n",
440 hw_p
->stats
.pkts_rx
, hw_p
->stats
.pkts_handled
);
442 hw_p
->stats
.pkts_tx
= 0;
443 hw_p
->stats
.pkts_rx
= 0;
444 hw_p
->stats
.pkts_handled
= 0;
445 hw_p
->print_speed
= 1; /* print speed message again next time */
448 hw_p
->tx_err_index
= 0; /* Transmit Error Index for tx_err_log */
449 hw_p
->rx_err_index
= 0; /* Receive Error Index for rx_err_log */
451 hw_p
->rx_slot
= 0; /* MAL Receive Slot */
452 hw_p
->rx_i_index
= 0; /* Receive Interrupt Queue Index */
453 hw_p
->rx_u_index
= 0; /* Receive User Queue Index */
455 hw_p
->tx_slot
= 0; /* MAL Transmit Slot */
456 hw_p
->tx_i_index
= 0; /* Transmit Interrupt Queue Index */
457 hw_p
->tx_u_index
= 0; /* Transmit User Queue Index */
459 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
461 /* NOTE: 440GX spec states that mode is mutually exclusive */
462 /* NOTE: Therefore, disable all other EMACS, since we handle */
463 /* NOTE: only one emac at a time */
468 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
469 out32 (ZMII_FER
, (ZMII_FER_RMII
| ZMII_FER_MDI
) << ZMII_FER_V (devnum
));
470 #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
471 ethgroup
= ppc_4xx_eth_setup_bridge(devnum
, bis
);
472 #elif defined(CONFIG_440GP)
474 out32 (ZMII_FER
, ZMII_RMII
| ZMII_MDI0
);
476 if ((devnum
== 0) || (devnum
== 1)) {
477 out32 (ZMII_FER
, (ZMII_FER_SMII
| ZMII_FER_MDI
) << ZMII_FER_V (devnum
));
478 } else { /* ((devnum == 2) || (devnum == 3)) */
479 out32 (ZMII_FER
, ZMII_FER_MDI
<< ZMII_FER_V (devnum
));
480 out32 (RGMII_FER
, ((RGMII_FER_RGMII
<< RGMII_FER_V (2)) |
481 (RGMII_FER_RGMII
<< RGMII_FER_V (3))));
485 out32 (ZMII_SSR
, ZMII_SSR_SP
<< ZMII_SSR_V(devnum
));
486 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
488 __asm__
volatile ("eieio");
490 /* reset emac so we have access to the phy */
491 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
492 /* provide clocks for EMAC internal loopback */
493 mfsdr (sdr_mfr
, mfr
);
494 mfr
|= SDR0_MFR_ETH_CLK_SEL_V(devnum
);
498 out32 (EMAC_M0
+ hw_p
->hw_addr
, EMAC_M0_SRST
);
499 __asm__
volatile ("eieio");
502 while ((in32 (EMAC_M0
+ hw_p
->hw_addr
) & (EMAC_M0_SRST
)) && failsafe
) {
507 printf("\nProblem resetting EMAC!\n");
509 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
510 /* remove clocks for EMAC internal loopback */
511 mfsdr (sdr_mfr
, mfr
);
512 mfr
&= ~SDR0_MFR_ETH_CLK_SEL_V(devnum
);
516 #if defined(CONFIG_440GX) || \
517 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
518 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
519 /* Whack the M1 register */
521 mode_reg
&= ~0x00000038;
522 if (sysinfo
.freqOPB
<= 50000000);
523 else if (sysinfo
.freqOPB
<= 66666667)
524 mode_reg
|= EMAC_M1_OBCI_66
;
525 else if (sysinfo
.freqOPB
<= 83333333)
526 mode_reg
|= EMAC_M1_OBCI_83
;
527 else if (sysinfo
.freqOPB
<= 100000000)
528 mode_reg
|= EMAC_M1_OBCI_100
;
530 mode_reg
|= EMAC_M1_OBCI_GT100
;
532 out32 (EMAC_M1
+ hw_p
->hw_addr
, mode_reg
);
533 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
535 /* wait for PHY to complete auto negotiation */
537 #ifndef CONFIG_CS8952_PHY
540 reg
= CONFIG_PHY_ADDR
;
542 #if defined (CONFIG_PHY1_ADDR)
544 reg
= CONFIG_PHY1_ADDR
;
547 #if defined (CONFIG_440GX)
549 reg
= CONFIG_PHY2_ADDR
;
552 reg
= CONFIG_PHY3_ADDR
;
556 reg
= CONFIG_PHY_ADDR
;
560 bis
->bi_phynum
[devnum
] = reg
;
562 #if defined(CONFIG_PHY_RESET)
564 * Reset the phy, only if its the first time through
565 * otherwise, just check the speeds & feeds
567 if (hw_p
->first_init
== 0) {
568 #if defined(CONFIG_M88E1111_PHY)
569 miiphy_write (dev
->name
, reg
, 0x14, 0x0ce3);
570 miiphy_write (dev
->name
, reg
, 0x18, 0x4101);
571 miiphy_write (dev
->name
, reg
, 0x09, 0x0e00);
572 miiphy_write (dev
->name
, reg
, 0x04, 0x01e1);
574 miiphy_reset (dev
->name
, reg
);
576 #if defined(CONFIG_440GX) || \
577 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
578 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
580 #if defined(CONFIG_CIS8201_PHY)
582 * Cicada 8201 PHY needs to have an extended register whacked
585 if (((devnum
== 2) || (devnum
== 3)) && (4 == ethgroup
)) {
586 #if defined(CONFIG_CIS8201_SHORT_ETCH)
587 miiphy_write (dev
->name
, reg
, 23, 0x1300);
589 miiphy_write (dev
->name
, reg
, 23, 0x1000);
592 * Vitesse VSC8201/Cicada CIS8201 errata:
593 * Interoperability problem with Intel 82547EI phys
594 * This work around (provided by Vitesse) changes
595 * the default timer convergence from 8ms to 12ms
597 miiphy_write (dev
->name
, reg
, 0x1f, 0x2a30);
598 miiphy_write (dev
->name
, reg
, 0x08, 0x0200);
599 miiphy_write (dev
->name
, reg
, 0x1f, 0x52b5);
600 miiphy_write (dev
->name
, reg
, 0x02, 0x0004);
601 miiphy_write (dev
->name
, reg
, 0x01, 0x0671);
602 miiphy_write (dev
->name
, reg
, 0x00, 0x8fae);
603 miiphy_write (dev
->name
, reg
, 0x1f, 0x2a30);
604 miiphy_write (dev
->name
, reg
, 0x08, 0x0000);
605 miiphy_write (dev
->name
, reg
, 0x1f, 0x0000);
606 /* end Vitesse/Cicada errata */
610 #if defined(CONFIG_ET1011C_PHY)
612 * Agere ET1011c PHY needs to have an extended register whacked
615 if (((devnum
== 2) || (devnum
==3)) && (4 == ethgroup
)) {
616 miiphy_read (dev
->name
, reg
, 0x16, ®_short
);
618 reg_short
|= 0x6; /* RGMII DLL Delay*/
619 miiphy_write (dev
->name
, reg
, 0x16, reg_short
);
621 miiphy_read (dev
->name
, reg
, 0x17, ®_short
);
622 reg_short
&= ~(0x40);
623 miiphy_write (dev
->name
, reg
, 0x17, reg_short
);
625 miiphy_write(dev
->name
, reg
, 0x1c, 0x74f0);
630 /* Start/Restart autonegotiation */
631 phy_setup_aneg (dev
->name
, reg
);
634 #endif /* defined(CONFIG_PHY_RESET) */
636 miiphy_read (dev
->name
, reg
, PHY_BMSR
, ®_short
);
639 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
641 if ((reg_short
& PHY_BMSR_AUTN_ABLE
)
642 && !(reg_short
& PHY_BMSR_AUTN_COMP
)) {
643 puts ("Waiting for PHY auto negotiation to complete");
645 while (!(reg_short
& PHY_BMSR_AUTN_COMP
)) {
649 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
650 puts (" TIMEOUT !\n");
654 if ((i
++ % 1000) == 0) {
657 udelay (1000); /* 1 ms */
658 miiphy_read (dev
->name
, reg
, PHY_BMSR
, ®_short
);
662 udelay (500000); /* another 500 ms (results in faster booting) */
664 #endif /* #ifndef CONFIG_CS8952_PHY */
666 speed
= miiphy_speed (dev
->name
, reg
);
667 duplex
= miiphy_duplex (dev
->name
, reg
);
669 if (hw_p
->print_speed
) {
670 hw_p
->print_speed
= 0;
671 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
672 (int) speed
, (duplex
== HALF
) ? "HALF" : "FULL",
676 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
677 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
678 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
681 reg
= (reg
& ~SDR0_MFR_ZMII_MODE_MASK
) | SDR0_MFR_ZMII_MODE_RMII_100M
;
683 reg
= (reg
& ~SDR0_MFR_ZMII_MODE_MASK
) | SDR0_MFR_ZMII_MODE_RMII_10M
;
688 /* Set ZMII/RGMII speed according to the phy link speed */
689 reg
= in32 (ZMII_SSR
);
690 if ( (speed
== 100) || (speed
== 1000) )
691 out32 (ZMII_SSR
, reg
| (ZMII_SSR_SP
<< ZMII_SSR_V (devnum
)));
693 out32 (ZMII_SSR
, reg
& (~(ZMII_SSR_SP
<< ZMII_SSR_V (devnum
))));
695 if ((devnum
== 2) || (devnum
== 3)) {
697 reg
= (RGMII_SSR_SP_1000MBPS
<< RGMII_SSR_V (devnum
));
698 else if (speed
== 100)
699 reg
= (RGMII_SSR_SP_100MBPS
<< RGMII_SSR_V (devnum
));
700 else if (speed
== 10)
701 reg
= (RGMII_SSR_SP_10MBPS
<< RGMII_SSR_V (devnum
));
703 printf("Error in RGMII Speed\n");
706 out32 (RGMII_SSR
, reg
);
708 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
710 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
712 reg
= (RGMII_SSR_SP_1000MBPS
<< RGMII_SSR_V (devnum
));
713 else if (speed
== 100)
714 reg
= (RGMII_SSR_SP_100MBPS
<< RGMII_SSR_V (devnum
));
715 else if (speed
== 10)
716 reg
= (RGMII_SSR_SP_10MBPS
<< RGMII_SSR_V (devnum
));
718 printf("Error in RGMII Speed\n");
721 out32 (RGMII_SSR
, reg
);
724 /* set the Mal configuration reg */
725 #if defined(CONFIG_440GX) || \
726 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
727 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
728 mtdcr (malmcr
, MAL_CR_PLBB
| MAL_CR_OPBBL
| MAL_CR_LEA
|
729 MAL_CR_PLBLT_DEFAULT
| MAL_CR_EOPIE
| 0x00330000);
731 mtdcr (malmcr
, MAL_CR_PLBB
| MAL_CR_OPBBL
| MAL_CR_LEA
| MAL_CR_PLBLT_DEFAULT
);
732 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
733 if (get_pvr() == PVR_440GP_RB
) {
734 mtdcr (malmcr
, mfdcr(malmcr
) & ~MAL_CR_PLBB
);
738 /* Free "old" buffers */
739 if (hw_p
->alloc_tx_buf
)
740 free (hw_p
->alloc_tx_buf
);
741 if (hw_p
->alloc_rx_buf
)
742 free (hw_p
->alloc_rx_buf
);
745 * Malloc MAL buffer desciptors, make sure they are
746 * aligned on cache line boundary size
747 * (401/403/IOP480 = 16, 405 = 32)
748 * and doesn't cross cache block boundaries.
751 (mal_desc_t
*) malloc ((sizeof (mal_desc_t
) * NUM_TX_BUFF
) +
752 ((2 * CFG_CACHELINE_SIZE
) - 2));
753 if (NULL
== hw_p
->alloc_tx_buf
)
755 if (((int) hw_p
->alloc_tx_buf
& CACHELINE_MASK
) != 0) {
757 (mal_desc_t
*) ((int) hw_p
->alloc_tx_buf
+
760 alloc_tx_buf
& CACHELINE_MASK
));
762 hw_p
->tx
= hw_p
->alloc_tx_buf
;
766 (mal_desc_t
*) malloc ((sizeof (mal_desc_t
) * NUM_RX_BUFF
) +
767 ((2 * CFG_CACHELINE_SIZE
) - 2));
768 if (NULL
== hw_p
->alloc_rx_buf
) {
769 free(hw_p
->alloc_tx_buf
);
770 hw_p
->alloc_tx_buf
= NULL
;
774 if (((int) hw_p
->alloc_rx_buf
& CACHELINE_MASK
) != 0) {
776 (mal_desc_t
*) ((int) hw_p
->alloc_rx_buf
+
779 alloc_rx_buf
& CACHELINE_MASK
));
781 hw_p
->rx
= hw_p
->alloc_rx_buf
;
784 for (i
= 0; i
< NUM_TX_BUFF
; i
++) {
785 hw_p
->tx
[i
].ctrl
= 0;
786 hw_p
->tx
[i
].data_len
= 0;
787 if (hw_p
->first_init
== 0) {
789 (char *) malloc (ENET_MAX_MTU_ALIGNED
);
790 if (NULL
== hw_p
->txbuf_ptr
) {
791 free(hw_p
->alloc_rx_buf
);
792 free(hw_p
->alloc_tx_buf
);
793 hw_p
->alloc_rx_buf
= NULL
;
794 hw_p
->alloc_tx_buf
= NULL
;
795 for(j
= 0; j
< i
; j
++) {
796 free(hw_p
->tx
[i
].data_ptr
);
797 hw_p
->tx
[i
].data_ptr
= NULL
;
801 hw_p
->tx
[i
].data_ptr
= hw_p
->txbuf_ptr
;
802 if ((NUM_TX_BUFF
- 1) == i
)
803 hw_p
->tx
[i
].ctrl
|= MAL_TX_CTRL_WRAP
;
804 hw_p
->tx_run
[i
] = -1;
806 printf ("TX_BUFF %d @ 0x%08lx\n", i
,
807 (ulong
) hw_p
->tx
[i
].data_ptr
);
811 for (i
= 0; i
< NUM_RX_BUFF
; i
++) {
812 hw_p
->rx
[i
].ctrl
= 0;
813 hw_p
->rx
[i
].data_len
= 0;
814 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
815 hw_p
->rx
[i
].data_ptr
= (char *) NetRxPackets
[i
];
816 if ((NUM_RX_BUFF
- 1) == i
)
817 hw_p
->rx
[i
].ctrl
|= MAL_RX_CTRL_WRAP
;
818 hw_p
->rx
[i
].ctrl
|= MAL_RX_CTRL_EMPTY
| MAL_RX_CTRL_INTR
;
819 hw_p
->rx_ready
[i
] = -1;
821 printf ("RX_BUFF %d @ 0x%08lx\n", i
, (ulong
) hw_p
->rx
[i
].data_ptr
);
827 reg
|= dev
->enetaddr
[0]; /* set high address */
829 reg
|= dev
->enetaddr
[1];
831 out32 (EMAC_IAH
+ hw_p
->hw_addr
, reg
);
834 reg
|= dev
->enetaddr
[2]; /* set low address */
836 reg
|= dev
->enetaddr
[3];
838 reg
|= dev
->enetaddr
[4];
840 reg
|= dev
->enetaddr
[5];
842 out32 (EMAC_IAL
+ hw_p
->hw_addr
, reg
);
846 /* setup MAL tx & rx channel pointers */
847 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
848 mtdcr (maltxctp2r
, hw_p
->tx
);
850 mtdcr (maltxctp1r
, hw_p
->tx
);
852 #if defined(CONFIG_440)
853 mtdcr (maltxbattr
, 0x0);
854 mtdcr (malrxbattr
, 0x0);
856 mtdcr (malrxctp1r
, hw_p
->rx
);
857 /* set RX buffer size */
858 mtdcr (malrcbs1
, ENET_MAX_MTU_ALIGNED
/ 16);
860 #if defined (CONFIG_440GX)
862 /* setup MAL tx & rx channel pointers */
863 mtdcr (maltxbattr
, 0x0);
864 mtdcr (malrxbattr
, 0x0);
865 mtdcr (maltxctp2r
, hw_p
->tx
);
866 mtdcr (malrxctp2r
, hw_p
->rx
);
867 /* set RX buffer size */
868 mtdcr (malrcbs2
, ENET_MAX_MTU_ALIGNED
/ 16);
871 /* setup MAL tx & rx channel pointers */
872 mtdcr (maltxbattr
, 0x0);
873 mtdcr (maltxctp3r
, hw_p
->tx
);
874 mtdcr (malrxbattr
, 0x0);
875 mtdcr (malrxctp3r
, hw_p
->rx
);
876 /* set RX buffer size */
877 mtdcr (malrcbs3
, ENET_MAX_MTU_ALIGNED
/ 16);
879 #endif /* CONFIG_440GX */
882 /* setup MAL tx & rx channel pointers */
883 #if defined(CONFIG_440)
884 mtdcr (maltxbattr
, 0x0);
885 mtdcr (malrxbattr
, 0x0);
887 mtdcr (maltxctp0r
, hw_p
->tx
);
888 mtdcr (malrxctp0r
, hw_p
->rx
);
889 /* set RX buffer size */
890 mtdcr (malrcbs0
, ENET_MAX_MTU_ALIGNED
/ 16);
894 /* Enable MAL transmit and receive channels */
895 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
896 mtdcr (maltxcasr
, (MAL_TXRX_CASR
>> (hw_p
->devnum
*2)));
898 mtdcr (maltxcasr
, (MAL_TXRX_CASR
>> hw_p
->devnum
));
900 mtdcr (malrxcasr
, (MAL_TXRX_CASR
>> hw_p
->devnum
));
902 /* set transmit enable & receive enable */
903 out32 (EMAC_M0
+ hw_p
->hw_addr
, EMAC_M0_TXE
| EMAC_M0_RXE
);
905 /* set receive fifo to 4k and tx fifo to 2k */
906 mode_reg
= in32 (EMAC_M1
+ hw_p
->hw_addr
);
907 mode_reg
|= EMAC_M1_RFS_4K
| EMAC_M1_TX_FIFO_2K
;
910 if (speed
== _1000BASET
) {
911 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
912 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
915 mfsdr (sdr_pfc1
, pfc1
);
916 pfc1
|= SDR0_PFC1_EM_1000
;
917 mtsdr (sdr_pfc1
, pfc1
);
919 mode_reg
= mode_reg
| EMAC_M1_MF_1000MBPS
| EMAC_M1_IST
;
920 } else if (speed
== _100BASET
)
921 mode_reg
= mode_reg
| EMAC_M1_MF_100MBPS
| EMAC_M1_IST
;
923 mode_reg
= mode_reg
& ~0x00C00000; /* 10 MBPS */
925 mode_reg
= mode_reg
| 0x80000000 | EMAC_M1_IST
;
927 out32 (EMAC_M1
+ hw_p
->hw_addr
, mode_reg
);
929 /* Enable broadcast and indvidual address */
930 /* TBS: enabling runts as some misbehaved nics will send runts */
931 out32 (EMAC_RXM
+ hw_p
->hw_addr
, EMAC_RMR_BAE
| EMAC_RMR_IAE
);
933 /* we probably need to set the tx mode1 reg? maybe at tx time */
935 /* set transmit request threshold register */
936 out32 (EMAC_TRTR
+ hw_p
->hw_addr
, 0x18000000); /* 256 byte threshold */
938 /* set receive low/high water mark register */
939 #if defined(CONFIG_440)
940 /* 440s has a 64 byte burst length */
941 out32 (EMAC_RX_HI_LO_WMARK
+ hw_p
->hw_addr
, 0x80009000);
943 /* 405s have a 16 byte burst length */
944 out32 (EMAC_RX_HI_LO_WMARK
+ hw_p
->hw_addr
, 0x0f002000);
945 #endif /* defined(CONFIG_440) */
946 out32 (EMAC_TXM1
+ hw_p
->hw_addr
, 0xf8640000);
948 /* Set fifo limit entry in tx mode 0 */
949 out32 (EMAC_TXM0
+ hw_p
->hw_addr
, 0x00000003);
951 out32 (EMAC_I_FRAME_GAP_REG
+ hw_p
->hw_addr
, 0x00000008);
954 hw_p
->emac_ier
= EMAC_ISR_PTLE
| EMAC_ISR_BFCS
| EMAC_ISR_ORE
| EMAC_ISR_IRE
;
955 if (speed
== _100BASET
)
956 hw_p
->emac_ier
= hw_p
->emac_ier
| EMAC_ISR_SYE
;
958 out32 (EMAC_ISR
+ hw_p
->hw_addr
, 0xffffffff); /* clear pending interrupts */
959 out32 (EMAC_IER
+ hw_p
->hw_addr
, hw_p
->emac_ier
);
961 if (hw_p
->first_init
== 0) {
963 * Connect interrupt service routines
965 irq_install_handler (VECNUM_ETH0
+ (hw_p
->devnum
* 2),
966 (interrupt_handler_t
*) enetInt
, dev
);
969 mtmsr (msr
); /* enable interrupts again */
972 hw_p
->first_init
= 1;
978 static int ppc_4xx_eth_send (struct eth_device
*dev
, volatile void *ptr
,
981 struct enet_frame
*ef_ptr
;
982 ulong time_start
, time_now
;
983 unsigned long temp_txm0
;
984 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
986 ef_ptr
= (struct enet_frame
*) ptr
;
988 /*-----------------------------------------------------------------------+
989 * Copy in our address into the frame.
990 *-----------------------------------------------------------------------*/
991 (void) memcpy (ef_ptr
->source_addr
, dev
->enetaddr
, ENET_ADDR_LENGTH
);
993 /*-----------------------------------------------------------------------+
994 * If frame is too long or too short, modify length.
995 *-----------------------------------------------------------------------*/
996 /* TBS: where does the fragment go???? */
997 if (len
> ENET_MAX_MTU
)
1000 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1001 memcpy ((void *) hw_p
->txbuf_ptr
, (const void *) ptr
, len
);
1003 /*-----------------------------------------------------------------------+
1004 * set TX Buffer busy, and send it
1005 *-----------------------------------------------------------------------*/
1006 hw_p
->tx
[hw_p
->tx_slot
].ctrl
= (MAL_TX_CTRL_LAST
|
1007 EMAC_TX_CTRL_GFCS
| EMAC_TX_CTRL_GP
) &
1008 ~(EMAC_TX_CTRL_ISA
| EMAC_TX_CTRL_RSA
);
1009 if ((NUM_TX_BUFF
- 1) == hw_p
->tx_slot
)
1010 hw_p
->tx
[hw_p
->tx_slot
].ctrl
|= MAL_TX_CTRL_WRAP
;
1012 hw_p
->tx
[hw_p
->tx_slot
].data_len
= (short) len
;
1013 hw_p
->tx
[hw_p
->tx_slot
].ctrl
|= MAL_TX_CTRL_READY
;
1015 __asm__
volatile ("eieio");
1017 out32 (EMAC_TXM0
+ hw_p
->hw_addr
,
1018 in32 (EMAC_TXM0
+ hw_p
->hw_addr
) | EMAC_TXM0_GNP0
);
1019 #ifdef INFO_4XX_ENET
1020 hw_p
->stats
.pkts_tx
++;
1023 /*-----------------------------------------------------------------------+
1024 * poll unitl the packet is sent and then make sure it is OK
1025 *-----------------------------------------------------------------------*/
1026 time_start
= get_timer (0);
1028 temp_txm0
= in32 (EMAC_TXM0
+ hw_p
->hw_addr
);
1029 /* loop until either TINT turns on or 3 seconds elapse */
1030 if ((temp_txm0
& EMAC_TXM0_GNP0
) != 0) {
1031 /* transmit is done, so now check for errors
1032 * If there is an error, an interrupt should
1033 * happen when we return
1035 time_now
= get_timer (0);
1036 if ((time_now
- time_start
) > 3000) {
1046 #if defined (CONFIG_440)
1048 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1050 * Hack: On 440SP all enet irq sources are located on UIC1
1051 * Needs some cleanup. --sr
1053 #define UIC0MSR uic1msr
1054 #define UIC0SR uic1sr
1056 #define UIC0MSR uic0msr
1057 #define UIC0SR uic0sr
1060 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1061 #define UICMSR_ETHX uic0msr
1062 #define UICSR_ETHX uic0sr
1064 #define UICMSR_ETHX uic1msr
1065 #define UICSR_ETHX uic1sr
1068 int enetInt (struct eth_device
*dev
)
1071 int rc
= -1; /* default to not us */
1072 unsigned long mal_isr
;
1073 unsigned long emac_isr
= 0;
1074 unsigned long mal_rx_eob
;
1075 unsigned long my_uic0msr
, my_uic1msr
;
1076 unsigned long my_uicmsr_ethx
;
1078 #if defined(CONFIG_440GX)
1079 unsigned long my_uic2msr
;
1081 EMAC_4XX_HW_PST hw_p
;
1084 * Because the mal is generic, we need to get the current
1087 #if defined(CONFIG_NET_MULTI)
1088 dev
= eth_get_dev();
1095 /* enter loop that stays in interrupt code until nothing to service */
1099 my_uic0msr
= mfdcr (UIC0MSR
);
1100 my_uic1msr
= mfdcr (uic1msr
);
1101 #if defined(CONFIG_440GX)
1102 my_uic2msr
= mfdcr (uic2msr
);
1104 my_uicmsr_ethx
= mfdcr (UICMSR_ETHX
);
1106 if (!(my_uic0msr
& (UIC_MRE
| UIC_MTE
))
1107 && !(my_uic1msr
& (UIC_MS
| UIC_MTDE
| UIC_MRDE
))
1108 && !(my_uicmsr_ethx
& (UIC_ETH0
| UIC_ETH1
))) {
1112 #if defined (CONFIG_440GX)
1113 if (!(my_uic0msr
& (UIC_MRE
| UIC_MTE
))
1114 && !(my_uic2msr
& (UIC_ETH2
| UIC_ETH3
))) {
1119 /* get and clear controller status interrupts */
1120 /* look at Mal and EMAC interrupts */
1121 if ((my_uic0msr
& (UIC_MRE
| UIC_MTE
))
1122 || (my_uic1msr
& (UIC_MS
| UIC_MTDE
| UIC_MRDE
))) {
1123 /* we have a MAL interrupt */
1124 mal_isr
= mfdcr (malesr
);
1125 /* look for mal error */
1126 if (my_uic1msr
& (UIC_MS
| UIC_MTDE
| UIC_MRDE
)) {
1127 mal_err (dev
, mal_isr
, my_uic1msr
, MAL_UIC_DEF
, MAL_UIC_ERR
);
1133 /* port by port dispatch of emac interrupts */
1134 if (hw_p
->devnum
== 0) {
1135 if (UIC_ETH0
& my_uicmsr_ethx
) { /* look for EMAC errors */
1136 emac_isr
= in32 (EMAC_ISR
+ hw_p
->hw_addr
);
1137 if ((hw_p
->emac_ier
& emac_isr
) != 0) {
1138 emac_err (dev
, emac_isr
);
1143 if ((hw_p
->emac_ier
& emac_isr
)
1144 || (my_uic1msr
& (UIC_MS
| UIC_MTDE
| UIC_MRDE
))) {
1145 mtdcr (UIC0SR
, UIC_MRE
| UIC_MTE
); /* Clear */
1146 mtdcr (uic1sr
, UIC_MS
| UIC_MTDE
| UIC_MRDE
); /* Clear */
1147 mtdcr (UICSR_ETHX
, UIC_ETH0
); /* Clear */
1148 return (rc
); /* we had errors so get out */
1152 #if !defined(CONFIG_440SP)
1153 if (hw_p
->devnum
== 1) {
1154 if (UIC_ETH1
& my_uicmsr_ethx
) { /* look for EMAC errors */
1155 emac_isr
= in32 (EMAC_ISR
+ hw_p
->hw_addr
);
1156 if ((hw_p
->emac_ier
& emac_isr
) != 0) {
1157 emac_err (dev
, emac_isr
);
1162 if ((hw_p
->emac_ier
& emac_isr
)
1163 || (my_uic1msr
& (UIC_MS
| UIC_MTDE
| UIC_MRDE
))) {
1164 mtdcr (UIC0SR
, UIC_MRE
| UIC_MTE
); /* Clear */
1165 mtdcr (uic1sr
, UIC_MS
| UIC_MTDE
| UIC_MRDE
); /* Clear */
1166 mtdcr (UICSR_ETHX
, UIC_ETH1
); /* Clear */
1167 return (rc
); /* we had errors so get out */
1170 #if defined (CONFIG_440GX)
1171 if (hw_p
->devnum
== 2) {
1172 if (UIC_ETH2
& my_uic2msr
) { /* look for EMAC errors */
1173 emac_isr
= in32 (EMAC_ISR
+ hw_p
->hw_addr
);
1174 if ((hw_p
->emac_ier
& emac_isr
) != 0) {
1175 emac_err (dev
, emac_isr
);
1180 if ((hw_p
->emac_ier
& emac_isr
)
1181 || (my_uic1msr
& (UIC_MS
| UIC_MTDE
| UIC_MRDE
))) {
1182 mtdcr (UIC0SR
, UIC_MRE
| UIC_MTE
); /* Clear */
1183 mtdcr (uic1sr
, UIC_MS
| UIC_MTDE
| UIC_MRDE
); /* Clear */
1184 mtdcr (uic2sr
, UIC_ETH2
);
1185 return (rc
); /* we had errors so get out */
1189 if (hw_p
->devnum
== 3) {
1190 if (UIC_ETH3
& my_uic2msr
) { /* look for EMAC errors */
1191 emac_isr
= in32 (EMAC_ISR
+ hw_p
->hw_addr
);
1192 if ((hw_p
->emac_ier
& emac_isr
) != 0) {
1193 emac_err (dev
, emac_isr
);
1198 if ((hw_p
->emac_ier
& emac_isr
)
1199 || (my_uic1msr
& (UIC_MS
| UIC_MTDE
| UIC_MRDE
))) {
1200 mtdcr (UIC0SR
, UIC_MRE
| UIC_MTE
); /* Clear */
1201 mtdcr (uic1sr
, UIC_MS
| UIC_MTDE
| UIC_MRDE
); /* Clear */
1202 mtdcr (uic2sr
, UIC_ETH3
);
1203 return (rc
); /* we had errors so get out */
1206 #endif /* CONFIG_440GX */
1207 #endif /* !CONFIG_440SP */
1209 /* handle MAX TX EOB interrupt from a tx */
1210 if (my_uic0msr
& UIC_MTE
) {
1211 mal_rx_eob
= mfdcr (maltxeobisr
);
1212 mtdcr (maltxeobisr
, mal_rx_eob
);
1213 mtdcr (UIC0SR
, UIC_MTE
);
1215 /* handle MAL RX EOB interupt from a receive */
1216 /* check for EOB on valid channels */
1217 if (my_uic0msr
& UIC_MRE
) {
1218 mal_rx_eob
= mfdcr (malrxeobisr
);
1219 if ((mal_rx_eob
& (0x80000000 >> hw_p
->devnum
)) != 0) { /* call emac routine for channel x */
1221 mtdcr(malrxeobisr, mal_rx_eob); */
1222 enet_rcv (dev
, emac_isr
);
1223 /* indicate that we serviced an interrupt */
1229 mtdcr (UIC0SR
, UIC_MRE
); /* Clear */
1230 mtdcr (uic1sr
, UIC_MS
| UIC_MTDE
| UIC_MRDE
); /* Clear */
1231 switch (hw_p
->devnum
) {
1233 mtdcr (UICSR_ETHX
, UIC_ETH0
);
1236 mtdcr (UICSR_ETHX
, UIC_ETH1
);
1238 #if defined (CONFIG_440GX)
1240 mtdcr (uic2sr
, UIC_ETH2
);
1243 mtdcr (uic2sr
, UIC_ETH3
);
1245 #endif /* CONFIG_440GX */
1254 #else /* CONFIG_440 */
1256 int enetInt (struct eth_device
*dev
)
1259 int rc
= -1; /* default to not us */
1260 unsigned long mal_isr
;
1261 unsigned long emac_isr
= 0;
1262 unsigned long mal_rx_eob
;
1263 unsigned long my_uicmsr
;
1265 EMAC_4XX_HW_PST hw_p
;
1268 * Because the mal is generic, we need to get the current
1271 #if defined(CONFIG_NET_MULTI)
1272 dev
= eth_get_dev();
1279 /* enter loop that stays in interrupt code until nothing to service */
1283 my_uicmsr
= mfdcr (uicmsr
);
1285 if ((my_uicmsr
& (MAL_UIC_DEF
| EMAC_UIC_DEF
)) == 0) { /* not for us */
1288 /* get and clear controller status interrupts */
1289 /* look at Mal and EMAC interrupts */
1290 if ((MAL_UIC_DEF
& my_uicmsr
) != 0) { /* we have a MAL interrupt */
1291 mal_isr
= mfdcr (malesr
);
1292 /* look for mal error */
1293 if ((my_uicmsr
& MAL_UIC_ERR
) != 0) {
1294 mal_err (dev
, mal_isr
, my_uicmsr
, MAL_UIC_DEF
, MAL_UIC_ERR
);
1300 /* port by port dispatch of emac interrupts */
1302 if ((SEL_UIC_DEF(hw_p
->devnum
) & my_uicmsr
) != 0) { /* look for EMAC errors */
1303 emac_isr
= in32 (EMAC_ISR
+ hw_p
->hw_addr
);
1304 if ((hw_p
->emac_ier
& emac_isr
) != 0) {
1305 emac_err (dev
, emac_isr
);
1310 if (((hw_p
->emac_ier
& emac_isr
) != 0) || ((MAL_UIC_ERR
& my_uicmsr
) != 0)) {
1311 mtdcr (uicsr
, MAL_UIC_DEF
| SEL_UIC_DEF(hw_p
->devnum
)); /* Clear */
1312 return (rc
); /* we had errors so get out */
1315 /* handle MAX TX EOB interrupt from a tx */
1316 if (my_uicmsr
& UIC_MAL_TXEOB
) {
1317 mal_rx_eob
= mfdcr (maltxeobisr
);
1318 mtdcr (maltxeobisr
, mal_rx_eob
);
1319 mtdcr (uicsr
, UIC_MAL_TXEOB
);
1321 /* handle MAL RX EOB interupt from a receive */
1322 /* check for EOB on valid channels */
1323 if (my_uicmsr
& UIC_MAL_RXEOB
)
1325 mal_rx_eob
= mfdcr (malrxeobisr
);
1326 if ((mal_rx_eob
& (0x80000000 >> hw_p
->devnum
)) != 0) { /* call emac routine for channel x */
1328 mtdcr(malrxeobisr, mal_rx_eob); */
1329 enet_rcv (dev
, emac_isr
);
1330 /* indicate that we serviced an interrupt */
1335 mtdcr (uicsr
, MAL_UIC_DEF
|EMAC_UIC_DEF
|EMAC_UIC_DEF1
); /* Clear */
1342 #endif /* CONFIG_440 */
1344 /*-----------------------------------------------------------------------------+
1346 *-----------------------------------------------------------------------------*/
1347 static void mal_err (struct eth_device
*dev
, unsigned long isr
,
1348 unsigned long uic
, unsigned long maldef
,
1349 unsigned long mal_errr
)
1351 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
1353 mtdcr (malesr
, isr
); /* clear interrupt */
1355 /* clear DE interrupt */
1356 mtdcr (maltxdeir
, 0xC0000000);
1357 mtdcr (malrxdeir
, 0x80000000);
1359 #ifdef INFO_4XX_ENET
1360 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr
, uic
, maldef
, mal_errr
);
1363 eth_init (hw_p
->bis
); /* start again... */
1366 /*-----------------------------------------------------------------------------+
1367 * EMAC Error Routine
1368 *-----------------------------------------------------------------------------*/
1369 static void emac_err (struct eth_device
*dev
, unsigned long isr
)
1371 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
1373 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p
->devnum
, isr
);
1374 out32 (EMAC_ISR
+ hw_p
->hw_addr
, isr
);
1377 /*-----------------------------------------------------------------------------+
1378 * enet_rcv() handles the ethernet receive data
1379 *-----------------------------------------------------------------------------*/
1380 static void enet_rcv (struct eth_device
*dev
, unsigned long malisr
)
1382 struct enet_frame
*ef_ptr
;
1383 unsigned long data_len
;
1384 unsigned long rx_eob_isr
;
1385 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
1391 rx_eob_isr
= mfdcr (malrxeobisr
);
1392 if ((0x80000000 >> hw_p
->devnum
) & rx_eob_isr
) {
1394 mtdcr (malrxeobisr
, rx_eob_isr
);
1397 while (1) { /* do all */
1400 if ((MAL_RX_CTRL_EMPTY
& hw_p
->rx
[i
].ctrl
)
1401 || (loop_count
>= NUM_RX_BUFF
))
1405 if (NUM_RX_BUFF
== hw_p
->rx_slot
)
1408 data_len
= (unsigned long) hw_p
->rx
[i
].data_len
; /* Get len */
1410 if (data_len
> ENET_MAX_MTU
) /* Check len */
1413 if (EMAC_RX_ERRORS
& hw_p
->rx
[i
].ctrl
) { /* Check Errors */
1415 hw_p
->stats
.rx_err_log
[hw_p
->
1418 hw_p
->rx_err_index
++;
1419 if (hw_p
->rx_err_index
==
1421 hw_p
->rx_err_index
=
1424 } /* data_len < max mtu */
1426 if (!data_len
) { /* no data */
1427 hw_p
->rx
[i
].ctrl
|= MAL_RX_CTRL_EMPTY
; /* Free Recv Buffer */
1429 hw_p
->stats
.data_len_err
++; /* Error at Rx */
1434 /* Check if user has already eaten buffer */
1435 /* if not => ERROR */
1436 else if (hw_p
->rx_ready
[hw_p
->rx_i_index
] != -1) {
1437 if (hw_p
->is_receiving
)
1438 printf ("ERROR : Receive buffers are full!\n");
1441 hw_p
->stats
.rx_frames
++;
1442 hw_p
->stats
.rx
+= data_len
;
1443 ef_ptr
= (struct enet_frame
*) hw_p
->rx
[i
].
1445 #ifdef INFO_4XX_ENET
1446 hw_p
->stats
.pkts_rx
++;
1451 hw_p
->rx_ready
[hw_p
->rx_i_index
] = i
;
1453 if (NUM_RX_BUFF
== hw_p
->rx_i_index
)
1454 hw_p
->rx_i_index
= 0;
1457 * free receive buffer only when
1458 * buffer has been handled (eth_rx)
1459 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1463 } /* if EMACK_RXCHL */
1467 static int ppc_4xx_eth_rx (struct eth_device
*dev
)
1472 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
1474 hw_p
->is_receiving
= 1; /* tell driver */
1478 * use ring buffer and
1479 * get index from rx buffer desciptor queue
1481 user_index
= hw_p
->rx_ready
[hw_p
->rx_u_index
];
1482 if (user_index
== -1) {
1484 break; /* nothing received - leave for() loop */
1488 mtmsr (msr
& ~(MSR_EE
));
1490 length
= hw_p
->rx
[user_index
].data_len
;
1492 /* Pass the packet up to the protocol layers. */
1493 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1494 /* NetReceive(NetRxPackets[i], length); */
1495 NetReceive (NetRxPackets
[user_index
], length
- 4);
1496 /* Free Recv Buffer */
1497 hw_p
->rx
[user_index
].ctrl
|= MAL_RX_CTRL_EMPTY
;
1498 /* Free rx buffer descriptor queue */
1499 hw_p
->rx_ready
[hw_p
->rx_u_index
] = -1;
1501 if (NUM_RX_BUFF
== hw_p
->rx_u_index
)
1502 hw_p
->rx_u_index
= 0;
1504 #ifdef INFO_4XX_ENET
1505 hw_p
->stats
.pkts_handled
++;
1508 mtmsr (msr
); /* Enable IRQ's */
1511 hw_p
->is_receiving
= 0; /* tell driver */
1516 int ppc_4xx_eth_initialize (bd_t
* bis
)
1518 static int virgin
= 0;
1519 struct eth_device
*dev
;
1521 EMAC_4XX_HW_PST hw
= NULL
;
1522 u8 ethaddr
[4 + CONFIG_EMAC_NR_START
][6];
1525 #if defined(CONFIG_440GX)
1528 mfsdr (sdr_pfc1
, pfc1
);
1529 pfc1
&= ~(0x01e00000);
1531 mtsdr (sdr_pfc1
, pfc1
);
1534 /* first clear all mac-addresses */
1535 for (eth_num
= 0; eth_num
< LAST_EMAC_NUM
; eth_num
++)
1536 memcpy(ethaddr
[eth_num
], "\0\0\0\0\0\0", 6);
1538 for (eth_num
= 0; eth_num
< LAST_EMAC_NUM
; eth_num
++) {
1540 default: /* fall through */
1542 memcpy(ethaddr
[eth_num
+ CONFIG_EMAC_NR_START
],
1543 bis
->bi_enetaddr
, 6);
1544 hw_addr
[eth_num
] = 0x0;
1546 #ifdef CONFIG_HAS_ETH1
1548 memcpy(ethaddr
[eth_num
+ CONFIG_EMAC_NR_START
],
1549 bis
->bi_enet1addr
, 6);
1550 hw_addr
[eth_num
] = 0x100;
1553 #ifdef CONFIG_HAS_ETH2
1555 memcpy(ethaddr
[eth_num
+ CONFIG_EMAC_NR_START
],
1556 bis
->bi_enet2addr
, 6);
1557 hw_addr
[eth_num
] = 0x400;
1560 #ifdef CONFIG_HAS_ETH3
1562 memcpy(ethaddr
[eth_num
+ CONFIG_EMAC_NR_START
],
1563 bis
->bi_enet3addr
, 6);
1564 hw_addr
[eth_num
] = 0x600;
1570 /* set phy num and mode */
1571 bis
->bi_phynum
[0] = CONFIG_PHY_ADDR
;
1572 bis
->bi_phymode
[0] = 0;
1574 #if defined(CONFIG_PHY1_ADDR)
1575 bis
->bi_phynum
[1] = CONFIG_PHY1_ADDR
;
1576 bis
->bi_phymode
[1] = 0;
1578 #if defined(CONFIG_440GX)
1579 bis
->bi_phynum
[2] = CONFIG_PHY2_ADDR
;
1580 bis
->bi_phynum
[3] = CONFIG_PHY3_ADDR
;
1581 bis
->bi_phymode
[2] = 2;
1582 bis
->bi_phymode
[3] = 2;
1584 ppc_4xx_eth_setup_bridge(0, bis
);
1587 for (eth_num
= 0; eth_num
< LAST_EMAC_NUM
; eth_num
++) {
1589 * See if we can actually bring up the interface,
1590 * otherwise, skip it
1592 if (memcmp (ethaddr
[eth_num
], "\0\0\0\0\0\0", 6) == 0) {
1593 bis
->bi_phymode
[eth_num
] = BI_PHYMODE_NONE
;
1597 /* Allocate device structure */
1598 dev
= (struct eth_device
*) malloc (sizeof (*dev
));
1600 printf ("ppc_4xx_eth_initialize: "
1601 "Cannot allocate eth_device %d\n", eth_num
);
1604 memset(dev
, 0, sizeof(*dev
));
1606 /* Allocate our private use data */
1607 hw
= (EMAC_4XX_HW_PST
) malloc (sizeof (*hw
));
1609 printf ("ppc_4xx_eth_initialize: "
1610 "Cannot allocate private hw data for eth_device %d",
1615 memset(hw
, 0, sizeof(*hw
));
1617 hw
->hw_addr
= hw_addr
[eth_num
];
1618 memcpy (dev
->enetaddr
, ethaddr
[eth_num
], 6);
1619 hw
->devnum
= eth_num
;
1620 hw
->print_speed
= 1;
1622 sprintf (dev
->name
, "ppc_4xx_eth%d", eth_num
- CONFIG_EMAC_NR_START
);
1623 dev
->priv
= (void *) hw
;
1624 dev
->init
= ppc_4xx_eth_init
;
1625 dev
->halt
= ppc_4xx_eth_halt
;
1626 dev
->send
= ppc_4xx_eth_send
;
1627 dev
->recv
= ppc_4xx_eth_rx
;
1630 /* set the MAL IER ??? names may change with new spec ??? */
1631 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1633 MAL_IER_PT
| MAL_IER_PRE
| MAL_IER_PWE
|
1634 MAL_IER_DE
| MAL_IER_OTE
| MAL_IER_OE
| MAL_IER_PE
;
1637 MAL_IER_DE
| MAL_IER_NE
| MAL_IER_TE
|
1638 MAL_IER_OPBE
| MAL_IER_PLBE
;
1640 mtdcr (malesr
, 0xffffffff); /* clear pending interrupts */
1641 mtdcr (maltxdeir
, 0xffffffff); /* clear pending interrupts */
1642 mtdcr (malrxdeir
, 0xffffffff); /* clear pending interrupts */
1643 mtdcr (malier
, mal_ier
);
1645 /* install MAL interrupt handler */
1646 irq_install_handler (VECNUM_MS
,
1647 (interrupt_handler_t
*) enetInt
,
1649 irq_install_handler (VECNUM_MTE
,
1650 (interrupt_handler_t
*) enetInt
,
1652 irq_install_handler (VECNUM_MRE
,
1653 (interrupt_handler_t
*) enetInt
,
1655 irq_install_handler (VECNUM_TXDE
,
1656 (interrupt_handler_t
*) enetInt
,
1658 irq_install_handler (VECNUM_RXDE
,
1659 (interrupt_handler_t
*) enetInt
,
1664 #if defined(CONFIG_NET_MULTI)
1670 #if defined(CONFIG_NET_MULTI)
1671 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1672 miiphy_register (dev
->name
,
1673 emac4xx_miiphy_read
, emac4xx_miiphy_write
);
1676 } /* end for each supported device */
1680 #if !defined(CONFIG_NET_MULTI)
1681 void eth_halt (void) {
1683 ppc_4xx_eth_halt(emac0_dev
);
1689 int eth_init (bd_t
*bis
)
1691 ppc_4xx_eth_initialize(bis
);
1693 return ppc_4xx_eth_init(emac0_dev
, bis
);
1695 printf("ERROR: ethaddr not set!\n");
1700 int eth_send(volatile void *packet
, int length
)
1702 return (ppc_4xx_eth_send(emac0_dev
, packet
, length
));
1707 return (ppc_4xx_eth_rx(emac0_dev
));
1710 int emac4xx_miiphy_initialize (bd_t
* bis
)
1712 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1713 miiphy_register ("ppc_4xx_eth0",
1714 emac4xx_miiphy_read
, emac4xx_miiphy_write
);
1719 #endif /* !defined(CONFIG_NET_MULTI) */
1721 #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */