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1 /*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
22 *
23 * File Name: enetemac.c
24 *
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
26 *
27 * Author: Mark Wisner
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
74 * (2 EMACs) also
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
79
80 #include <config.h>
81 #include <common.h>
82 #include <net.h>
83 #include <asm/processor.h>
84 #include <commproc.h>
85 #include <ppc4xx.h>
86 #include <ppc4xx_enet.h>
87 #include <405_mal.h>
88 #include <miiphy.h>
89 #include <malloc.h>
90 #include "vecnum.h"
91
92 /*
93 * Only compile for platform with IBM/AMCC EMAC ethernet controller and
94 * network support enabled.
95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
96 */
97 #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
98
99 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
100 #error "CONFIG_MII has to be defined!"
101 #endif
102
103 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
104 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
105
106 /* Ethernet Transmit and Receive Buffers */
107 /* AS.HARNOIS
108 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
109 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
110 */
111 #define ENET_MAX_MTU PKTSIZE
112 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
113
114 /* define the number of channels implemented */
115 #define EMAC_RXCHL EMAC_NUM_DEV
116 #define EMAC_TXCHL EMAC_NUM_DEV
117
118 /*-----------------------------------------------------------------------------+
119 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
120 * Interrupt Controller).
121 *-----------------------------------------------------------------------------*/
122 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
123 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
124 #define EMAC_UIC_DEF UIC_ENET
125 #define EMAC_UIC_DEF1 UIC_ENET1
126 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
127
128 #undef INFO_4XX_ENET
129
130 #define BI_PHYMODE_NONE 0
131 #define BI_PHYMODE_ZMII 1
132 #define BI_PHYMODE_RGMII 2
133
134
135 /*-----------------------------------------------------------------------------+
136 * Global variables. TX and RX descriptors and buffers.
137 *-----------------------------------------------------------------------------*/
138 /* IER globals */
139 static uint32_t mal_ier;
140
141 #if !defined(CONFIG_NET_MULTI)
142 struct eth_device *emac0_dev;
143 #endif
144
145
146 /*-----------------------------------------------------------------------------+
147 * Prototypes and externals.
148 *-----------------------------------------------------------------------------*/
149 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
150
151 int enetInt (struct eth_device *dev);
152 static void mal_err (struct eth_device *dev, unsigned long isr,
153 unsigned long uic, unsigned long maldef,
154 unsigned long mal_errr);
155 static void emac_err (struct eth_device *dev, unsigned long isr);
156
157
158 /*-----------------------------------------------------------------------------+
159 | ppc_4xx_eth_halt
160 | Disable MAL channel, and EMACn
161 +-----------------------------------------------------------------------------*/
162 static void ppc_4xx_eth_halt (struct eth_device *dev)
163 {
164 EMAC_4XX_HW_PST hw_p = dev->priv;
165 uint32_t failsafe = 10000;
166
167 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
168
169 /* 1st reset MAL channel */
170 /* Note: writing a 0 to a channel has no effect */
171 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
172 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
173 #else
174 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
175 #endif
176 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
177
178 /* wait for reset */
179 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
180 udelay (1000); /* Delay 1 MS so as not to hammer the register */
181 failsafe--;
182 if (failsafe == 0)
183 break;
184 }
185
186 /* EMAC RESET */
187 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
188
189 hw_p->print_speed = 1; /* print speed message again next time */
190
191 return;
192 }
193
194 extern int phy_setup_aneg (unsigned char addr);
195 extern int miiphy_reset (unsigned char addr);
196
197 #if defined (CONFIG_440GX)
198 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
199 {
200 unsigned long pfc1;
201 unsigned long zmiifer;
202 unsigned long rmiifer;
203
204 mfsdr(sdr_pfc1, pfc1);
205 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
206
207 zmiifer = 0;
208 rmiifer = 0;
209
210 switch (pfc1) {
211 case 1:
212 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
213 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
214 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
215 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
216 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
217 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
218 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
219 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
220 break;
221 case 2:
222 zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
223 zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
224 zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
225 zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
226 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
227 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
228 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
229 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
230 break;
231 case 3:
232 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
233 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
234 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
235 bis->bi_phymode[1] = BI_PHYMODE_NONE;
236 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
237 bis->bi_phymode[3] = BI_PHYMODE_NONE;
238 break;
239 case 4:
240 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
241 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
242 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
243 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
244 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
245 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
246 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
247 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
248 break;
249 case 5:
250 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
251 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
252 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
253 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
254 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
255 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
256 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
257 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
258 break;
259 case 6:
260 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
261 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
262 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
263 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
264 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
265 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
266 break;
267 case 0:
268 default:
269 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
270 rmiifer = 0x0;
271 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
272 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
273 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
274 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
275 break;
276 }
277
278 /* Ensure we setup mdio for this devnum and ONLY this devnum */
279 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
280
281 out32 (ZMII_FER, zmiifer);
282 out32 (RGMII_FER, rmiifer);
283
284 return ((int)pfc1);
285
286 }
287 #endif
288
289 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
290 {
291 int i, j;
292 unsigned long reg = 0;
293 unsigned long msr;
294 unsigned long speed;
295 unsigned long duplex;
296 unsigned long failsafe;
297 unsigned mode_reg;
298 unsigned short devnum;
299 unsigned short reg_short;
300 #if defined(CONFIG_440GX)
301 sys_info_t sysinfo;
302 int ethgroup;
303 #endif
304
305 EMAC_4XX_HW_PST hw_p = dev->priv;
306
307 /* before doing anything, figure out if we have a MAC address */
308 /* if not, bail */
309 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
310 return -1;
311
312 #if defined(CONFIG_440GX)
313 /* Need to get the OPB frequency so we can access the PHY */
314 get_sys_info (&sysinfo);
315 #endif
316
317 msr = mfmsr ();
318 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
319
320 devnum = hw_p->devnum;
321
322 #ifdef INFO_4XX_ENET
323 /* AS.HARNOIS
324 * We should have :
325 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
326 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
327 * is possible that new packets (without relationship with
328 * current transfer) have got the time to arrived before
329 * netloop calls eth_halt
330 */
331 printf ("About preceeding transfer (eth%d):\n"
332 "- Sent packet number %d\n"
333 "- Received packet number %d\n"
334 "- Handled packet number %d\n",
335 hw_p->devnum,
336 hw_p->stats.pkts_tx,
337 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
338
339 hw_p->stats.pkts_tx = 0;
340 hw_p->stats.pkts_rx = 0;
341 hw_p->stats.pkts_handled = 0;
342 #endif
343
344 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
345 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
346
347 hw_p->rx_slot = 0; /* MAL Receive Slot */
348 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
349 hw_p->rx_u_index = 0; /* Receive User Queue Index */
350
351 hw_p->tx_slot = 0; /* MAL Transmit Slot */
352 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
353 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
354
355 #if defined(CONFIG_440)
356 /* set RMII mode */
357 /* NOTE: 440GX spec states that mode is mutually exclusive */
358 /* NOTE: Therefore, disable all other EMACS, since we handle */
359 /* NOTE: only one emac at a time */
360 reg = 0;
361 out32 (ZMII_FER, 0);
362 udelay (100);
363
364 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
365 out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
366 #elif defined(CONFIG_440GX)
367 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
368 #elif defined(CONFIG_440GP)
369 /* set RMII mode */
370 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
371 #else
372 if ((devnum == 0) || (devnum == 1)) {
373 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
374 }
375 else { /* ((devnum == 2) || (devnum == 3)) */
376 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
377 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
378 (RGMII_FER_RGMII << RGMII_FER_V (3))));
379 }
380 #endif
381
382 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
383 #endif /* defined(CONFIG_440) */
384
385 __asm__ volatile ("eieio");
386
387 /* reset emac so we have access to the phy */
388
389 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
390 __asm__ volatile ("eieio");
391
392 failsafe = 1000;
393 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
394 udelay (1000);
395 failsafe--;
396 }
397
398 #if defined(CONFIG_440GX)
399 /* Whack the M1 register */
400 mode_reg = 0x0;
401 mode_reg &= ~0x00000038;
402 if (sysinfo.freqOPB <= 50000000);
403 else if (sysinfo.freqOPB <= 66666667)
404 mode_reg |= EMAC_M1_OBCI_66;
405 else if (sysinfo.freqOPB <= 83333333)
406 mode_reg |= EMAC_M1_OBCI_83;
407 else if (sysinfo.freqOPB <= 100000000)
408 mode_reg |= EMAC_M1_OBCI_100;
409 else
410 mode_reg |= EMAC_M1_OBCI_GT100;
411
412 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
413 #endif /* defined(CONFIG_440GX) */
414
415 /* wait for PHY to complete auto negotiation */
416 reg_short = 0;
417 #ifndef CONFIG_CS8952_PHY
418 switch (devnum) {
419 case 0:
420 reg = CONFIG_PHY_ADDR;
421 break;
422 #if defined (CONFIG_PHY1_ADDR)
423 case 1:
424 reg = CONFIG_PHY1_ADDR;
425 break;
426 #endif
427 #if defined (CONFIG_440GX)
428 case 2:
429 reg = CONFIG_PHY2_ADDR;
430 break;
431 case 3:
432 reg = CONFIG_PHY3_ADDR;
433 break;
434 #endif
435 default:
436 reg = CONFIG_PHY_ADDR;
437 break;
438 }
439
440 bis->bi_phynum[devnum] = reg;
441
442 #if defined(CONFIG_PHY_RESET)
443 /*
444 * Reset the phy, only if its the first time through
445 * otherwise, just check the speeds & feeds
446 */
447 if (hw_p->first_init == 0) {
448 miiphy_reset (reg);
449
450 #if defined(CONFIG_440GX)
451 #if defined(CONFIG_CIS8201_PHY)
452 /*
453 * Cicada 8201 PHY needs to have an extended register whacked
454 * for RGMII mode.
455 */
456 if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
457 #if defined(CONFIG_CIS8201_SHORT_ETCH)
458 miiphy_write (reg, 23, 0x1300);
459 #else
460 miiphy_write (reg, 23, 0x1000);
461 #endif
462 /*
463 * Vitesse VSC8201/Cicada CIS8201 errata:
464 * Interoperability problem with Intel 82547EI phys
465 * This work around (provided by Vitesse) changes
466 * the default timer convergence from 8ms to 12ms
467 */
468 miiphy_write (reg, 0x1f, 0x2a30);
469 miiphy_write (reg, 0x08, 0x0200);
470 miiphy_write (reg, 0x1f, 0x52b5);
471 miiphy_write (reg, 0x02, 0x0004);
472 miiphy_write (reg, 0x01, 0x0671);
473 miiphy_write (reg, 0x00, 0x8fae);
474 miiphy_write (reg, 0x1f, 0x2a30);
475 miiphy_write (reg, 0x08, 0x0000);
476 miiphy_write (reg, 0x1f, 0x0000);
477 /* end Vitesse/Cicada errata */
478 }
479 #endif
480 #endif
481 /* Start/Restart autonegotiation */
482 phy_setup_aneg (reg);
483 udelay (1000);
484 }
485 #endif /* defined(CONFIG_PHY_RESET) */
486
487 miiphy_read (reg, PHY_BMSR, &reg_short);
488
489 /*
490 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
491 */
492 if ((reg_short & PHY_BMSR_AUTN_ABLE)
493 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
494 puts ("Waiting for PHY auto negotiation to complete");
495 i = 0;
496 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
497 /*
498 * Timeout reached ?
499 */
500 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
501 puts (" TIMEOUT !\n");
502 break;
503 }
504
505 if ((i++ % 1000) == 0) {
506 putc ('.');
507 }
508 udelay (1000); /* 1 ms */
509 miiphy_read (reg, PHY_BMSR, &reg_short);
510
511 }
512 puts (" done\n");
513 udelay (500000); /* another 500 ms (results in faster booting) */
514 }
515 #endif /* #ifndef CONFIG_CS8952_PHY */
516
517 speed = miiphy_speed (reg);
518 duplex = miiphy_duplex (reg);
519
520 if (hw_p->print_speed) {
521 hw_p->print_speed = 0;
522 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
523 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
524 }
525
526 #if defined(CONFIG_440)
527 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
528 mfsdr(sdr_mfr, reg);
529 if (speed == 100) {
530 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
531 } else {
532 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
533 }
534 mtsdr(sdr_mfr, reg);
535 #endif
536
537 /* Set ZMII/RGMII speed according to the phy link speed */
538 reg = in32 (ZMII_SSR);
539 if ( (speed == 100) || (speed == 1000) )
540 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
541 else
542 out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
543
544 if ((devnum == 2) || (devnum == 3)) {
545 if (speed == 1000)
546 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
547 else if (speed == 100)
548 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
549 else
550 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
551
552 out32 (RGMII_SSR, reg);
553 }
554 #endif /* defined(CONFIG_440) */
555
556 /* set the Mal configuration reg */
557 #if defined(CONFIG_440GX)
558 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
559 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
560 #else
561 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
562 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
563 if (get_pvr() == PVR_440GP_RB) {
564 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
565 }
566 #endif
567
568 /* Free "old" buffers */
569 if (hw_p->alloc_tx_buf)
570 free (hw_p->alloc_tx_buf);
571 if (hw_p->alloc_rx_buf)
572 free (hw_p->alloc_rx_buf);
573
574 /*
575 * Malloc MAL buffer desciptors, make sure they are
576 * aligned on cache line boundary size
577 * (401/403/IOP480 = 16, 405 = 32)
578 * and doesn't cross cache block boundaries.
579 */
580 hw_p->alloc_tx_buf =
581 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
582 ((2 * CFG_CACHELINE_SIZE) - 2));
583 if (NULL == hw_p->alloc_tx_buf)
584 return -1;
585 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
586 hw_p->tx =
587 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
588 CFG_CACHELINE_SIZE -
589 ((int) hw_p->
590 alloc_tx_buf & CACHELINE_MASK));
591 } else {
592 hw_p->tx = hw_p->alloc_tx_buf;
593 }
594
595 hw_p->alloc_rx_buf =
596 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
597 ((2 * CFG_CACHELINE_SIZE) - 2));
598 if (NULL == hw_p->alloc_rx_buf) {
599 free(hw_p->alloc_tx_buf);
600 hw_p->alloc_tx_buf = NULL;
601 return -1;
602 }
603
604 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
605 hw_p->rx =
606 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
607 CFG_CACHELINE_SIZE -
608 ((int) hw_p->
609 alloc_rx_buf & CACHELINE_MASK));
610 } else {
611 hw_p->rx = hw_p->alloc_rx_buf;
612 }
613
614 for (i = 0; i < NUM_TX_BUFF; i++) {
615 hw_p->tx[i].ctrl = 0;
616 hw_p->tx[i].data_len = 0;
617 if (hw_p->first_init == 0) {
618 hw_p->txbuf_ptr =
619 (char *) malloc (ENET_MAX_MTU_ALIGNED);
620 if (NULL == hw_p->txbuf_ptr) {
621 free(hw_p->alloc_rx_buf);
622 free(hw_p->alloc_tx_buf);
623 hw_p->alloc_rx_buf = NULL;
624 hw_p->alloc_tx_buf = NULL;
625 for(j = 0; j < i; j++) {
626 free(hw_p->tx[i].data_ptr);
627 hw_p->tx[i].data_ptr = NULL;
628 }
629 }
630 }
631 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
632 if ((NUM_TX_BUFF - 1) == i)
633 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
634 hw_p->tx_run[i] = -1;
635 #if 0
636 printf ("TX_BUFF %d @ 0x%08lx\n", i,
637 (ulong) hw_p->tx[i].data_ptr);
638 #endif
639 }
640
641 for (i = 0; i < NUM_RX_BUFF; i++) {
642 hw_p->rx[i].ctrl = 0;
643 hw_p->rx[i].data_len = 0;
644 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
645 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
646 if ((NUM_RX_BUFF - 1) == i)
647 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
648 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
649 hw_p->rx_ready[i] = -1;
650 #if 0
651 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
652 #endif
653 }
654
655 reg = 0x00000000;
656
657 reg |= dev->enetaddr[0]; /* set high address */
658 reg = reg << 8;
659 reg |= dev->enetaddr[1];
660
661 out32 (EMAC_IAH + hw_p->hw_addr, reg);
662
663 reg = 0x00000000;
664 reg |= dev->enetaddr[2]; /* set low address */
665 reg = reg << 8;
666 reg |= dev->enetaddr[3];
667 reg = reg << 8;
668 reg |= dev->enetaddr[4];
669 reg = reg << 8;
670 reg |= dev->enetaddr[5];
671
672 out32 (EMAC_IAL + hw_p->hw_addr, reg);
673
674 switch (devnum) {
675 case 1:
676 /* setup MAL tx & rx channel pointers */
677 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
678 mtdcr (maltxctp2r, hw_p->tx);
679 #else
680 mtdcr (maltxctp1r, hw_p->tx);
681 #endif
682 #if defined(CONFIG_440)
683 mtdcr (maltxbattr, 0x0);
684 mtdcr (malrxbattr, 0x0);
685 #endif
686 mtdcr (malrxctp1r, hw_p->rx);
687 /* set RX buffer size */
688 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
689 break;
690 #if defined (CONFIG_440GX)
691 case 2:
692 /* setup MAL tx & rx channel pointers */
693 mtdcr (maltxbattr, 0x0);
694 mtdcr (malrxbattr, 0x0);
695 mtdcr (maltxctp2r, hw_p->tx);
696 mtdcr (malrxctp2r, hw_p->rx);
697 /* set RX buffer size */
698 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
699 break;
700 case 3:
701 /* setup MAL tx & rx channel pointers */
702 mtdcr (maltxbattr, 0x0);
703 mtdcr (maltxctp3r, hw_p->tx);
704 mtdcr (malrxbattr, 0x0);
705 mtdcr (malrxctp3r, hw_p->rx);
706 /* set RX buffer size */
707 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
708 break;
709 #endif /* CONFIG_440GX */
710 case 0:
711 default:
712 /* setup MAL tx & rx channel pointers */
713 #if defined(CONFIG_440)
714 mtdcr (maltxbattr, 0x0);
715 mtdcr (malrxbattr, 0x0);
716 #endif
717 mtdcr (maltxctp0r, hw_p->tx);
718 mtdcr (malrxctp0r, hw_p->rx);
719 /* set RX buffer size */
720 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
721 break;
722 }
723
724 /* Enable MAL transmit and receive channels */
725 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
726 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
727 #else
728 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
729 #endif
730 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
731
732 /* set transmit enable & receive enable */
733 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
734
735 /* set receive fifo to 4k and tx fifo to 2k */
736 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
737 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
738
739 /* set speed */
740 if (speed == _1000BASET)
741 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
742 else if (speed == _100BASET)
743 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
744 else
745 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
746 if (duplex == FULL)
747 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
748
749 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
750
751 /* Enable broadcast and indvidual address */
752 /* TBS: enabling runts as some misbehaved nics will send runts */
753 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
754
755 /* we probably need to set the tx mode1 reg? maybe at tx time */
756
757 /* set transmit request threshold register */
758 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
759
760 /* set receive low/high water mark register */
761 #if defined(CONFIG_440)
762 /* 440GP has a 64 byte burst length */
763 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
764 #else
765 /* 405s have a 16 byte burst length */
766 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
767 #endif /* defined(CONFIG_440) */
768 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
769
770 /* Set fifo limit entry in tx mode 0 */
771 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
772 /* Frame gap set */
773 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
774
775 /* Set EMAC IER */
776 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
777 if (speed == _100BASET)
778 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
779
780 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
781 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
782
783 if (hw_p->first_init == 0) {
784 /*
785 * Connect interrupt service routines
786 */
787 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
788 (interrupt_handler_t *) enetInt, dev);
789 }
790
791 mtmsr (msr); /* enable interrupts again */
792
793 hw_p->bis = bis;
794 hw_p->first_init = 1;
795
796 return (1);
797 }
798
799
800 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
801 int len)
802 {
803 struct enet_frame *ef_ptr;
804 ulong time_start, time_now;
805 unsigned long temp_txm0;
806 EMAC_4XX_HW_PST hw_p = dev->priv;
807
808 ef_ptr = (struct enet_frame *) ptr;
809
810 /*-----------------------------------------------------------------------+
811 * Copy in our address into the frame.
812 *-----------------------------------------------------------------------*/
813 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
814
815 /*-----------------------------------------------------------------------+
816 * If frame is too long or too short, modify length.
817 *-----------------------------------------------------------------------*/
818 /* TBS: where does the fragment go???? */
819 if (len > ENET_MAX_MTU)
820 len = ENET_MAX_MTU;
821
822 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
823 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
824
825 /*-----------------------------------------------------------------------+
826 * set TX Buffer busy, and send it
827 *-----------------------------------------------------------------------*/
828 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
829 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
830 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
831 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
832 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
833
834 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
835 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
836
837 __asm__ volatile ("eieio");
838
839 out32 (EMAC_TXM0 + hw_p->hw_addr,
840 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
841 #ifdef INFO_4XX_ENET
842 hw_p->stats.pkts_tx++;
843 #endif
844
845 /*-----------------------------------------------------------------------+
846 * poll unitl the packet is sent and then make sure it is OK
847 *-----------------------------------------------------------------------*/
848 time_start = get_timer (0);
849 while (1) {
850 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
851 /* loop until either TINT turns on or 3 seconds elapse */
852 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
853 /* transmit is done, so now check for errors
854 * If there is an error, an interrupt should
855 * happen when we return
856 */
857 time_now = get_timer (0);
858 if ((time_now - time_start) > 3000) {
859 return (-1);
860 }
861 } else {
862 return (len);
863 }
864 }
865 }
866
867 #if defined (CONFIG_440)
868
869 int enetInt (struct eth_device *dev)
870 {
871 int serviced;
872 int rc = -1; /* default to not us */
873 unsigned long mal_isr;
874 unsigned long emac_isr = 0;
875 unsigned long mal_rx_eob;
876 unsigned long my_uic0msr, my_uic1msr;
877
878 #if defined(CONFIG_440GX)
879 unsigned long my_uic2msr;
880 #endif
881 EMAC_4XX_HW_PST hw_p;
882
883 /*
884 * Because the mal is generic, we need to get the current
885 * eth device
886 */
887 #if defined(CONFIG_NET_MULTI)
888 dev = eth_get_dev();
889 #else
890 dev = emac0_dev;
891 #endif
892
893 hw_p = dev->priv;
894
895
896 /* enter loop that stays in interrupt code until nothing to service */
897 do {
898 serviced = 0;
899
900 my_uic0msr = mfdcr (uic0msr);
901 my_uic1msr = mfdcr (uic1msr);
902 #if defined(CONFIG_440GX)
903 my_uic2msr = mfdcr (uic2msr);
904 #endif
905 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
906 && !(my_uic1msr &
907 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
908 UIC_MRDE))) {
909 /* not for us */
910 return (rc);
911 }
912 #if defined (CONFIG_440GX)
913 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
914 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
915 /* not for us */
916 return (rc);
917 }
918 #endif
919 /* get and clear controller status interrupts */
920 /* look at Mal and EMAC interrupts */
921 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
922 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
923 /* we have a MAL interrupt */
924 mal_isr = mfdcr (malesr);
925 /* look for mal error */
926 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
927 mal_err (dev, mal_isr, my_uic0msr,
928 MAL_UIC_DEF, MAL_UIC_ERR);
929 serviced = 1;
930 rc = 0;
931 }
932 }
933
934 /* port by port dispatch of emac interrupts */
935 if (hw_p->devnum == 0) {
936 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
937 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
938 if ((hw_p->emac_ier & emac_isr) != 0) {
939 emac_err (dev, emac_isr);
940 serviced = 1;
941 rc = 0;
942 }
943 }
944 if ((hw_p->emac_ier & emac_isr)
945 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
946 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
947 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
948 return (rc); /* we had errors so get out */
949 }
950 }
951
952 if (hw_p->devnum == 1) {
953 if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
954 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
955 if ((hw_p->emac_ier & emac_isr) != 0) {
956 emac_err (dev, emac_isr);
957 serviced = 1;
958 rc = 0;
959 }
960 }
961 if ((hw_p->emac_ier & emac_isr)
962 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
963 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
964 mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
965 return (rc); /* we had errors so get out */
966 }
967 }
968 #if defined (CONFIG_440GX)
969 if (hw_p->devnum == 2) {
970 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
971 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
972 if ((hw_p->emac_ier & emac_isr) != 0) {
973 emac_err (dev, emac_isr);
974 serviced = 1;
975 rc = 0;
976 }
977 }
978 if ((hw_p->emac_ier & emac_isr)
979 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
980 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
981 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
982 mtdcr (uic2sr, UIC_ETH2);
983 return (rc); /* we had errors so get out */
984 }
985 }
986
987 if (hw_p->devnum == 3) {
988 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
989 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
990 if ((hw_p->emac_ier & emac_isr) != 0) {
991 emac_err (dev, emac_isr);
992 serviced = 1;
993 rc = 0;
994 }
995 }
996 if ((hw_p->emac_ier & emac_isr)
997 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
998 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
999 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1000 mtdcr (uic2sr, UIC_ETH3);
1001 return (rc); /* we had errors so get out */
1002 }
1003 }
1004 #endif /* CONFIG_440GX */
1005 /* handle MAX TX EOB interrupt from a tx */
1006 if (my_uic0msr & UIC_MTE) {
1007 mal_rx_eob = mfdcr (maltxeobisr);
1008 mtdcr (maltxeobisr, mal_rx_eob);
1009 mtdcr (uic0sr, UIC_MTE);
1010 }
1011 /* handle MAL RX EOB interupt from a receive */
1012 /* check for EOB on valid channels */
1013 if (my_uic0msr & UIC_MRE) {
1014 mal_rx_eob = mfdcr (malrxeobisr);
1015 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1016 /* clear EOB
1017 mtdcr(malrxeobisr, mal_rx_eob); */
1018 enet_rcv (dev, emac_isr);
1019 /* indicate that we serviced an interrupt */
1020 serviced = 1;
1021 rc = 0;
1022 }
1023 }
1024 mtdcr (uic0sr, UIC_MRE); /* Clear */
1025 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1026 switch (hw_p->devnum) {
1027 case 0:
1028 mtdcr (uic1sr, UIC_ETH0);
1029 break;
1030 case 1:
1031 mtdcr (uic1sr, UIC_ETH1);
1032 break;
1033 #if defined (CONFIG_440GX)
1034 case 2:
1035 mtdcr (uic2sr, UIC_ETH2);
1036 break;
1037 case 3:
1038 mtdcr (uic2sr, UIC_ETH3);
1039 break;
1040 #endif /* CONFIG_440GX */
1041 default:
1042 break;
1043 }
1044 } while (serviced);
1045
1046 return (rc);
1047 }
1048
1049 #else /* CONFIG_440 */
1050
1051 int enetInt (struct eth_device *dev)
1052 {
1053 int serviced;
1054 int rc = -1; /* default to not us */
1055 unsigned long mal_isr;
1056 unsigned long emac_isr = 0;
1057 unsigned long mal_rx_eob;
1058 unsigned long my_uicmsr;
1059
1060 EMAC_4XX_HW_PST hw_p;
1061
1062 /*
1063 * Because the mal is generic, we need to get the current
1064 * eth device
1065 */
1066 #if defined(CONFIG_NET_MULTI)
1067 dev = eth_get_dev();
1068 #else
1069 dev = emac0_dev;
1070 #endif
1071
1072 hw_p = dev->priv;
1073
1074 /* enter loop that stays in interrupt code until nothing to service */
1075 do {
1076 serviced = 0;
1077
1078 my_uicmsr = mfdcr (uicmsr);
1079
1080 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1081 return (rc);
1082 }
1083 /* get and clear controller status interrupts */
1084 /* look at Mal and EMAC interrupts */
1085 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1086 mal_isr = mfdcr (malesr);
1087 /* look for mal error */
1088 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1089 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1090 serviced = 1;
1091 rc = 0;
1092 }
1093 }
1094
1095 /* port by port dispatch of emac interrupts */
1096
1097 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1098 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1099 if ((hw_p->emac_ier & emac_isr) != 0) {
1100 emac_err (dev, emac_isr);
1101 serviced = 1;
1102 rc = 0;
1103 }
1104 }
1105 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1106 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1107 return (rc); /* we had errors so get out */
1108 }
1109
1110 /* handle MAX TX EOB interrupt from a tx */
1111 if (my_uicmsr & UIC_MAL_TXEOB) {
1112 mal_rx_eob = mfdcr (maltxeobisr);
1113 mtdcr (maltxeobisr, mal_rx_eob);
1114 mtdcr (uicsr, UIC_MAL_TXEOB);
1115 }
1116 /* handle MAL RX EOB interupt from a receive */
1117 /* check for EOB on valid channels */
1118 if (my_uicmsr & UIC_MAL_RXEOB)
1119 {
1120 mal_rx_eob = mfdcr (malrxeobisr);
1121 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1122 /* clear EOB
1123 mtdcr(malrxeobisr, mal_rx_eob); */
1124 enet_rcv (dev, emac_isr);
1125 /* indicate that we serviced an interrupt */
1126 serviced = 1;
1127 rc = 0;
1128 }
1129 }
1130 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1131 }
1132 while (serviced);
1133
1134 return (rc);
1135 }
1136
1137 #endif /* CONFIG_440 */
1138
1139 /*-----------------------------------------------------------------------------+
1140 * MAL Error Routine
1141 *-----------------------------------------------------------------------------*/
1142 static void mal_err (struct eth_device *dev, unsigned long isr,
1143 unsigned long uic, unsigned long maldef,
1144 unsigned long mal_errr)
1145 {
1146 EMAC_4XX_HW_PST hw_p = dev->priv;
1147
1148 mtdcr (malesr, isr); /* clear interrupt */
1149
1150 /* clear DE interrupt */
1151 mtdcr (maltxdeir, 0xC0000000);
1152 mtdcr (malrxdeir, 0x80000000);
1153
1154 #ifdef INFO_4XX_ENET
1155 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1156 #endif
1157
1158 eth_init (hw_p->bis); /* start again... */
1159 }
1160
1161 /*-----------------------------------------------------------------------------+
1162 * EMAC Error Routine
1163 *-----------------------------------------------------------------------------*/
1164 static void emac_err (struct eth_device *dev, unsigned long isr)
1165 {
1166 EMAC_4XX_HW_PST hw_p = dev->priv;
1167
1168 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1169 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1170 }
1171
1172 /*-----------------------------------------------------------------------------+
1173 * enet_rcv() handles the ethernet receive data
1174 *-----------------------------------------------------------------------------*/
1175 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1176 {
1177 struct enet_frame *ef_ptr;
1178 unsigned long data_len;
1179 unsigned long rx_eob_isr;
1180 EMAC_4XX_HW_PST hw_p = dev->priv;
1181
1182 int handled = 0;
1183 int i;
1184 int loop_count = 0;
1185
1186 rx_eob_isr = mfdcr (malrxeobisr);
1187 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1188 /* clear EOB */
1189 mtdcr (malrxeobisr, rx_eob_isr);
1190
1191 /* EMAC RX done */
1192 while (1) { /* do all */
1193 i = hw_p->rx_slot;
1194
1195 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1196 || (loop_count >= NUM_RX_BUFF))
1197 break;
1198 loop_count++;
1199 hw_p->rx_slot++;
1200 if (NUM_RX_BUFF == hw_p->rx_slot)
1201 hw_p->rx_slot = 0;
1202 handled++;
1203 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1204 if (data_len) {
1205 if (data_len > ENET_MAX_MTU) /* Check len */
1206 data_len = 0;
1207 else {
1208 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1209 data_len = 0;
1210 hw_p->stats.rx_err_log[hw_p->
1211 rx_err_index]
1212 = hw_p->rx[i].ctrl;
1213 hw_p->rx_err_index++;
1214 if (hw_p->rx_err_index ==
1215 MAX_ERR_LOG)
1216 hw_p->rx_err_index =
1217 0;
1218 } /* emac_erros */
1219 } /* data_len < max mtu */
1220 } /* if data_len */
1221 if (!data_len) { /* no data */
1222 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1223
1224 hw_p->stats.data_len_err++; /* Error at Rx */
1225 }
1226
1227 /* !data_len */
1228 /* AS.HARNOIS */
1229 /* Check if user has already eaten buffer */
1230 /* if not => ERROR */
1231 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1232 if (hw_p->is_receiving)
1233 printf ("ERROR : Receive buffers are full!\n");
1234 break;
1235 } else {
1236 hw_p->stats.rx_frames++;
1237 hw_p->stats.rx += data_len;
1238 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1239 data_ptr;
1240 #ifdef INFO_4XX_ENET
1241 hw_p->stats.pkts_rx++;
1242 #endif
1243 /* AS.HARNOIS
1244 * use ring buffer
1245 */
1246 hw_p->rx_ready[hw_p->rx_i_index] = i;
1247 hw_p->rx_i_index++;
1248 if (NUM_RX_BUFF == hw_p->rx_i_index)
1249 hw_p->rx_i_index = 0;
1250
1251 /* AS.HARNOIS
1252 * free receive buffer only when
1253 * buffer has been handled (eth_rx)
1254 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1255 */
1256 } /* if data_len */
1257 } /* while */
1258 } /* if EMACK_RXCHL */
1259 }
1260
1261
1262 static int ppc_4xx_eth_rx (struct eth_device *dev)
1263 {
1264 int length;
1265 int user_index;
1266 unsigned long msr;
1267 EMAC_4XX_HW_PST hw_p = dev->priv;
1268
1269 hw_p->is_receiving = 1; /* tell driver */
1270
1271 for (;;) {
1272 /* AS.HARNOIS
1273 * use ring buffer and
1274 * get index from rx buffer desciptor queue
1275 */
1276 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1277 if (user_index == -1) {
1278 length = -1;
1279 break; /* nothing received - leave for() loop */
1280 }
1281
1282 msr = mfmsr ();
1283 mtmsr (msr & ~(MSR_EE));
1284
1285 length = hw_p->rx[user_index].data_len;
1286
1287 /* Pass the packet up to the protocol layers. */
1288 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1289 /* NetReceive(NetRxPackets[i], length); */
1290 NetReceive (NetRxPackets[user_index], length - 4);
1291 /* Free Recv Buffer */
1292 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1293 /* Free rx buffer descriptor queue */
1294 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1295 hw_p->rx_u_index++;
1296 if (NUM_RX_BUFF == hw_p->rx_u_index)
1297 hw_p->rx_u_index = 0;
1298
1299 #ifdef INFO_4XX_ENET
1300 hw_p->stats.pkts_handled++;
1301 #endif
1302
1303 mtmsr (msr); /* Enable IRQ's */
1304 }
1305
1306 hw_p->is_receiving = 0; /* tell driver */
1307
1308 return length;
1309 }
1310
1311 int ppc_4xx_eth_initialize (bd_t * bis)
1312 {
1313 static int virgin = 0;
1314 struct eth_device *dev;
1315 int eth_num = 0;
1316 EMAC_4XX_HW_PST hw = NULL;
1317
1318 #if defined(CONFIG_440GX)
1319 unsigned long pfc1;
1320
1321 mfsdr (sdr_pfc1, pfc1);
1322 pfc1 &= ~(0x01e00000);
1323 pfc1 |= 0x01200000;
1324 mtsdr (sdr_pfc1, pfc1);
1325 #endif
1326 /* set phy num and mode */
1327 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1328 #if defined(CONFIG_PHY1_ADDR)
1329 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1330 #endif
1331 #if defined(CONFIG_440GX)
1332 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1333 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1334 bis->bi_phymode[0] = 0;
1335 bis->bi_phymode[1] = 0;
1336 bis->bi_phymode[2] = 2;
1337 bis->bi_phymode[3] = 2;
1338
1339 #if defined (CONFIG_440GX)
1340 ppc_4xx_eth_setup_bridge(0, bis);
1341 #endif
1342 #endif
1343
1344 for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
1345
1346 /* See if we can actually bring up the interface, otherwise, skip it */
1347 switch (eth_num) {
1348 default: /* fall through */
1349 case 0:
1350 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1351 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1352 continue;
1353 }
1354 break;
1355 #ifdef CONFIG_HAS_ETH1
1356 case 1:
1357 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
1358 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1359 continue;
1360 }
1361 break;
1362 #endif
1363 #ifdef CONFIG_HAS_ETH2
1364 case 2:
1365 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
1366 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1367 continue;
1368 }
1369 break;
1370 #endif
1371 #ifdef CONFIG_HAS_ETH3
1372 case 3:
1373 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
1374 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1375 continue;
1376 }
1377 break;
1378 #endif
1379 }
1380
1381 /* Allocate device structure */
1382 dev = (struct eth_device *) malloc (sizeof (*dev));
1383 if (dev == NULL) {
1384 printf ("ppc_4xx_eth_initialize: "
1385 "Cannot allocate eth_device %d\n", eth_num);
1386 return (-1);
1387 }
1388 memset(dev, 0, sizeof(*dev));
1389
1390 /* Allocate our private use data */
1391 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1392 if (hw == NULL) {
1393 printf ("ppc_4xx_eth_initialize: "
1394 "Cannot allocate private hw data for eth_device %d",
1395 eth_num);
1396 free (dev);
1397 return (-1);
1398 }
1399 memset(hw, 0, sizeof(*hw));
1400
1401 switch (eth_num) {
1402 default: /* fall through */
1403 case 0:
1404 hw->hw_addr = 0;
1405 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1406 break;
1407 #ifdef CONFIG_HAS_ETH1
1408 case 1:
1409 hw->hw_addr = 0x100;
1410 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1411 break;
1412 #endif
1413 #ifdef CONFIG_HAS_ETH2
1414 case 2:
1415 hw->hw_addr = 0x400;
1416 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1417 break;
1418 #endif
1419 #ifdef CONFIG_HAS_ETH3
1420 case 3:
1421 hw->hw_addr = 0x600;
1422 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1423 break;
1424 #endif
1425 }
1426
1427 hw->devnum = eth_num;
1428 hw->print_speed = 1;
1429
1430 sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
1431 dev->priv = (void *) hw;
1432 dev->init = ppc_4xx_eth_init;
1433 dev->halt = ppc_4xx_eth_halt;
1434 dev->send = ppc_4xx_eth_send;
1435 dev->recv = ppc_4xx_eth_rx;
1436
1437 if (0 == virgin) {
1438 /* set the MAL IER ??? names may change with new spec ??? */
1439 mal_ier =
1440 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1441 MAL_IER_OPBE | MAL_IER_PLBE;
1442 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1443 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1444 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1445 mtdcr (malier, mal_ier);
1446
1447 /* install MAL interrupt handler */
1448 irq_install_handler (VECNUM_MS,
1449 (interrupt_handler_t *) enetInt,
1450 dev);
1451 irq_install_handler (VECNUM_MTE,
1452 (interrupt_handler_t *) enetInt,
1453 dev);
1454 irq_install_handler (VECNUM_MRE,
1455 (interrupt_handler_t *) enetInt,
1456 dev);
1457 irq_install_handler (VECNUM_TXDE,
1458 (interrupt_handler_t *) enetInt,
1459 dev);
1460 irq_install_handler (VECNUM_RXDE,
1461 (interrupt_handler_t *) enetInt,
1462 dev);
1463 virgin = 1;
1464 }
1465
1466 #if defined(CONFIG_NET_MULTI)
1467 eth_register (dev);
1468 #else
1469 emac0_dev = dev;
1470 #endif
1471
1472 } /* end for each supported device */
1473 return (1);
1474 }
1475
1476
1477 #if !defined(CONFIG_NET_MULTI)
1478 void eth_halt (void) {
1479 if (emac0_dev) {
1480 ppc_4xx_eth_halt(emac0_dev);
1481 free(emac0_dev);
1482 emac0_dev = NULL;
1483 }
1484 }
1485
1486 int eth_init (bd_t *bis)
1487 {
1488 ppc_4xx_eth_initialize(bis);
1489 return(ppc_4xx_eth_init(emac0_dev, bis));
1490 }
1491
1492 int eth_send(volatile void *packet, int length)
1493 {
1494
1495 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1496 }
1497
1498 int eth_rx(void)
1499 {
1500 return (ppc_4xx_eth_rx(emac0_dev));
1501 }
1502 #endif /* !defined(CONFIG_NET_MULTI) */
1503
1504 #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */
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