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Add support for AMCC 440SPe CPU based eval board (Yucca).
[people/ms/u-boot.git] / cpu / ppc4xx / 4xx_enet.c
1 /*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
22 *
23 * File Name: enetemac.c
24 *
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
26 *
27 * Author: Mark Wisner
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
74 * (2 EMACs) also
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
79
80 #include <config.h>
81 #include <common.h>
82 #include <net.h>
83 #include <asm/processor.h>
84 #include <commproc.h>
85 #include <ppc4xx.h>
86 #include <ppc4xx_enet.h>
87 #include <405_mal.h>
88 #include <miiphy.h>
89 #include <malloc.h>
90 #include "vecnum.h"
91
92 /*
93 * Only compile for platform with AMCC EMAC ethernet controller and
94 * network support enabled.
95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
96 */
97 #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
98
99 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
100 #error "CONFIG_MII has to be defined!"
101 #endif
102
103 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
104 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
105 #endif
106
107 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
108 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
109
110 /* Ethernet Transmit and Receive Buffers */
111 /* AS.HARNOIS
112 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
113 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
114 */
115 #define ENET_MAX_MTU PKTSIZE
116 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
117
118 /*-----------------------------------------------------------------------------+
119 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
120 * Interrupt Controller).
121 *-----------------------------------------------------------------------------*/
122 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
123 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
124 #define EMAC_UIC_DEF UIC_ENET
125 #define EMAC_UIC_DEF1 UIC_ENET1
126 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
127
128 #undef INFO_4XX_ENET
129
130 #define BI_PHYMODE_NONE 0
131 #define BI_PHYMODE_ZMII 1
132 #define BI_PHYMODE_RGMII 2
133
134
135 /*-----------------------------------------------------------------------------+
136 * Global variables. TX and RX descriptors and buffers.
137 *-----------------------------------------------------------------------------*/
138 /* IER globals */
139 static uint32_t mal_ier;
140
141 #if !defined(CONFIG_NET_MULTI)
142 struct eth_device *emac0_dev = NULL;
143 #endif
144
145 /*
146 * Get count of EMAC devices (doesn't have to be the max. possible number
147 * supported by the cpu)
148 */
149 #if defined(CONFIG_HAS_ETH3)
150 #define LAST_EMAC_NUM 4
151 #elif defined(CONFIG_HAS_ETH2)
152 #define LAST_EMAC_NUM 3
153 #elif defined(CONFIG_HAS_ETH1)
154 #define LAST_EMAC_NUM 2
155 #else
156 #define LAST_EMAC_NUM 1
157 #endif
158
159 /*-----------------------------------------------------------------------------+
160 * Prototypes and externals.
161 *-----------------------------------------------------------------------------*/
162 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
163
164 int enetInt (struct eth_device *dev);
165 static void mal_err (struct eth_device *dev, unsigned long isr,
166 unsigned long uic, unsigned long maldef,
167 unsigned long mal_errr);
168 static void emac_err (struct eth_device *dev, unsigned long isr);
169
170 extern int phy_setup_aneg (char *devname, unsigned char addr);
171 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
172 unsigned char reg, unsigned short *value);
173 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
174 unsigned char reg, unsigned short value);
175
176 /*-----------------------------------------------------------------------------+
177 | ppc_4xx_eth_halt
178 | Disable MAL channel, and EMACn
179 +-----------------------------------------------------------------------------*/
180 static void ppc_4xx_eth_halt (struct eth_device *dev)
181 {
182 EMAC_4XX_HW_PST hw_p = dev->priv;
183 uint32_t failsafe = 10000;
184 #if defined(CONFIG_440SPE)
185 unsigned long mfr;
186 #endif
187
188 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
189
190 /* 1st reset MAL channel */
191 /* Note: writing a 0 to a channel has no effect */
192 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
193 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
194 #else
195 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
196 #endif
197 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
198
199 /* wait for reset */
200 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
201 udelay (1000); /* Delay 1 MS so as not to hammer the register */
202 failsafe--;
203 if (failsafe == 0)
204 break;
205 }
206
207 /* EMAC RESET */
208 #if defined(CONFIG_440SPE)
209 /* provide clocks for EMAC internal loopback */
210 mfsdr (sdr_mfr, mfr);
211 mfr |= 0x08000000;
212 mtsdr(sdr_mfr, mfr);
213 #endif
214
215 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
216
217 #if defined(CONFIG_440SPE)
218 /* remove clocks for EMAC internal loopback */
219 mfsdr (sdr_mfr, mfr);
220 mfr &= ~0x08000000;
221 mtsdr(sdr_mfr, mfr);
222 #endif
223
224
225 #ifndef CONFIG_NETCONSOLE
226 hw_p->print_speed = 1; /* print speed message again next time */
227 #endif
228
229 return;
230 }
231
232 #if defined (CONFIG_440GX)
233 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
234 {
235 unsigned long pfc1;
236 unsigned long zmiifer;
237 unsigned long rmiifer;
238
239 mfsdr(sdr_pfc1, pfc1);
240 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
241
242 zmiifer = 0;
243 rmiifer = 0;
244
245 switch (pfc1) {
246 case 1:
247 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
248 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
249 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
250 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
251 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
252 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
253 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
254 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
255 break;
256 case 2:
257 zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
258 zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
259 zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
260 zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
261 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
262 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
263 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
264 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
265 break;
266 case 3:
267 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
268 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
269 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
270 bis->bi_phymode[1] = BI_PHYMODE_NONE;
271 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
272 bis->bi_phymode[3] = BI_PHYMODE_NONE;
273 break;
274 case 4:
275 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
276 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
277 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
278 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
279 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
280 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
281 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
282 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
283 break;
284 case 5:
285 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
286 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
287 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
288 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
289 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
290 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
291 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
292 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
293 break;
294 case 6:
295 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
296 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
297 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
298 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
299 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
300 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
301 break;
302 case 0:
303 default:
304 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
305 rmiifer = 0x0;
306 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
307 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
308 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
309 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
310 break;
311 }
312
313 /* Ensure we setup mdio for this devnum and ONLY this devnum */
314 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
315
316 out32 (ZMII_FER, zmiifer);
317 out32 (RGMII_FER, rmiifer);
318
319 return ((int)pfc1);
320
321 }
322 #endif /* CONFIG_440_GX */
323
324 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
325 {
326 int i, j;
327 unsigned long reg = 0;
328 unsigned long msr;
329 unsigned long speed;
330 unsigned long duplex;
331 unsigned long failsafe;
332 unsigned mode_reg;
333 unsigned short devnum;
334 unsigned short reg_short;
335 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
336 sys_info_t sysinfo;
337 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
338 int ethgroup = -1;
339 #endif
340 #endif
341 #if defined(CONFIG_440SPE)
342 unsigned long mfr;
343 #endif
344
345
346 EMAC_4XX_HW_PST hw_p = dev->priv;
347
348 /* before doing anything, figure out if we have a MAC address */
349 /* if not, bail */
350 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
351 printf("ERROR: ethaddr not set!\n");
352 return -1;
353 }
354
355 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
356 /* Need to get the OPB frequency so we can access the PHY */
357 get_sys_info (&sysinfo);
358 #endif
359
360 msr = mfmsr ();
361 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
362
363 devnum = hw_p->devnum;
364
365 #ifdef INFO_4XX_ENET
366 /* AS.HARNOIS
367 * We should have :
368 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
369 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
370 * is possible that new packets (without relationship with
371 * current transfer) have got the time to arrived before
372 * netloop calls eth_halt
373 */
374 printf ("About preceeding transfer (eth%d):\n"
375 "- Sent packet number %d\n"
376 "- Received packet number %d\n"
377 "- Handled packet number %d\n",
378 hw_p->devnum,
379 hw_p->stats.pkts_tx,
380 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
381
382 hw_p->stats.pkts_tx = 0;
383 hw_p->stats.pkts_rx = 0;
384 hw_p->stats.pkts_handled = 0;
385 hw_p->print_speed = 1; /* print speed message again next time */
386 #endif
387
388 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
389 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
390
391 hw_p->rx_slot = 0; /* MAL Receive Slot */
392 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
393 hw_p->rx_u_index = 0; /* Receive User Queue Index */
394
395 hw_p->tx_slot = 0; /* MAL Transmit Slot */
396 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
397 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
398
399 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
400 /* set RMII mode */
401 /* NOTE: 440GX spec states that mode is mutually exclusive */
402 /* NOTE: Therefore, disable all other EMACS, since we handle */
403 /* NOTE: only one emac at a time */
404 reg = 0;
405 out32 (ZMII_FER, 0);
406 udelay (100);
407
408 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
409 out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
410 #elif defined(CONFIG_440GX)
411 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
412 #elif defined(CONFIG_440GP)
413 /* set RMII mode */
414 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
415 #else
416 if ((devnum == 0) || (devnum == 1)) {
417 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
418 }
419 else { /* ((devnum == 2) || (devnum == 3)) */
420 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
421 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
422 (RGMII_FER_RGMII << RGMII_FER_V (3))));
423 }
424 #endif
425
426 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
427 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
428
429 __asm__ volatile ("eieio");
430
431 /* reset emac so we have access to the phy */
432 #if defined(CONFIG_440SPE)
433 /* provide clocks for EMAC internal loopback */
434 mfsdr (sdr_mfr, mfr);
435 mfr |= 0x08000000;
436 mtsdr(sdr_mfr, mfr);
437 #endif
438
439 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
440 __asm__ volatile ("eieio");
441
442 failsafe = 1000;
443 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
444 udelay (1000);
445 failsafe--;
446 }
447
448 #if defined(CONFIG_440SPE)
449 /* remove clocks for EMAC internal loopback */
450 mfsdr (sdr_mfr, mfr);
451 mfr &= ~0x08000000;
452 mtsdr(sdr_mfr, mfr);
453 #endif
454
455 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
456 /* Whack the M1 register */
457 mode_reg = 0x0;
458 mode_reg &= ~0x00000038;
459 if (sysinfo.freqOPB <= 50000000);
460 else if (sysinfo.freqOPB <= 66666667)
461 mode_reg |= EMAC_M1_OBCI_66;
462 else if (sysinfo.freqOPB <= 83333333)
463 mode_reg |= EMAC_M1_OBCI_83;
464 else if (sysinfo.freqOPB <= 100000000)
465 mode_reg |= EMAC_M1_OBCI_100;
466 else
467 mode_reg |= EMAC_M1_OBCI_GT100;
468
469 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
470 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
471
472 /* wait for PHY to complete auto negotiation */
473 reg_short = 0;
474 #ifndef CONFIG_CS8952_PHY
475 switch (devnum) {
476 case 0:
477 reg = CONFIG_PHY_ADDR;
478 break;
479 #if defined (CONFIG_PHY1_ADDR)
480 case 1:
481 reg = CONFIG_PHY1_ADDR;
482 break;
483 #endif
484 #if defined (CONFIG_440GX)
485 case 2:
486 reg = CONFIG_PHY2_ADDR;
487 break;
488 case 3:
489 reg = CONFIG_PHY3_ADDR;
490 break;
491 #endif
492 default:
493 reg = CONFIG_PHY_ADDR;
494 break;
495 }
496
497 bis->bi_phynum[devnum] = reg;
498
499 #if defined(CONFIG_PHY_RESET)
500 /*
501 * Reset the phy, only if its the first time through
502 * otherwise, just check the speeds & feeds
503 */
504 if (hw_p->first_init == 0) {
505 miiphy_reset (dev->name, reg);
506
507 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
508 #if defined(CONFIG_CIS8201_PHY)
509 /*
510 * Cicada 8201 PHY needs to have an extended register whacked
511 * for RGMII mode.
512 */
513 if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
514 #if defined(CONFIG_CIS8201_SHORT_ETCH)
515 miiphy_write (dev->name, reg, 23, 0x1300);
516 #else
517 miiphy_write (dev->name, reg, 23, 0x1000);
518 #endif
519 /*
520 * Vitesse VSC8201/Cicada CIS8201 errata:
521 * Interoperability problem with Intel 82547EI phys
522 * This work around (provided by Vitesse) changes
523 * the default timer convergence from 8ms to 12ms
524 */
525 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
526 miiphy_write (dev->name, reg, 0x08, 0x0200);
527 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
528 miiphy_write (dev->name, reg, 0x02, 0x0004);
529 miiphy_write (dev->name, reg, 0x01, 0x0671);
530 miiphy_write (dev->name, reg, 0x00, 0x8fae);
531 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
532 miiphy_write (dev->name, reg, 0x08, 0x0000);
533 miiphy_write (dev->name, reg, 0x1f, 0x0000);
534 /* end Vitesse/Cicada errata */
535 }
536 #endif
537 #endif
538 /* Start/Restart autonegotiation */
539 phy_setup_aneg (dev->name, reg);
540 udelay (1000);
541 }
542 #endif /* defined(CONFIG_PHY_RESET) */
543
544 miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
545
546 /*
547 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
548 */
549 if ((reg_short & PHY_BMSR_AUTN_ABLE)
550 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
551 puts ("Waiting for PHY auto negotiation to complete");
552 i = 0;
553 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
554 /*
555 * Timeout reached ?
556 */
557 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
558 puts (" TIMEOUT !\n");
559 break;
560 }
561
562 if ((i++ % 1000) == 0) {
563 putc ('.');
564 }
565 udelay (1000); /* 1 ms */
566 miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
567
568 }
569 puts (" done\n");
570 udelay (500000); /* another 500 ms (results in faster booting) */
571 }
572 #endif /* #ifndef CONFIG_CS8952_PHY */
573
574 speed = miiphy_speed (dev->name, reg);
575 duplex = miiphy_duplex (dev->name, reg);
576
577 if (hw_p->print_speed) {
578 hw_p->print_speed = 0;
579 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
580 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
581 }
582
583 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
584 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
585 mfsdr(sdr_mfr, reg);
586 if (speed == 100) {
587 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
588 } else {
589 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
590 }
591 mtsdr(sdr_mfr, reg);
592 #endif
593
594 /* Set ZMII/RGMII speed according to the phy link speed */
595 reg = in32 (ZMII_SSR);
596 if ( (speed == 100) || (speed == 1000) )
597 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
598 else
599 out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
600
601 if ((devnum == 2) || (devnum == 3)) {
602 if (speed == 1000)
603 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
604 else if (speed == 100)
605 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
606 else
607 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
608
609 out32 (RGMII_SSR, reg);
610 }
611 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
612
613 /* set the Mal configuration reg */
614 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
615 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
616 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
617 #else
618 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
619 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
620 if (get_pvr() == PVR_440GP_RB) {
621 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
622 }
623 #endif
624
625 /* Free "old" buffers */
626 if (hw_p->alloc_tx_buf)
627 free (hw_p->alloc_tx_buf);
628 if (hw_p->alloc_rx_buf)
629 free (hw_p->alloc_rx_buf);
630
631 /*
632 * Malloc MAL buffer desciptors, make sure they are
633 * aligned on cache line boundary size
634 * (401/403/IOP480 = 16, 405 = 32)
635 * and doesn't cross cache block boundaries.
636 */
637 hw_p->alloc_tx_buf =
638 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
639 ((2 * CFG_CACHELINE_SIZE) - 2));
640 if (NULL == hw_p->alloc_tx_buf)
641 return -1;
642 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
643 hw_p->tx =
644 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
645 CFG_CACHELINE_SIZE -
646 ((int) hw_p->
647 alloc_tx_buf & CACHELINE_MASK));
648 } else {
649 hw_p->tx = hw_p->alloc_tx_buf;
650 }
651
652 hw_p->alloc_rx_buf =
653 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
654 ((2 * CFG_CACHELINE_SIZE) - 2));
655 if (NULL == hw_p->alloc_rx_buf) {
656 free(hw_p->alloc_tx_buf);
657 hw_p->alloc_tx_buf = NULL;
658 return -1;
659 }
660
661 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
662 hw_p->rx =
663 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
664 CFG_CACHELINE_SIZE -
665 ((int) hw_p->
666 alloc_rx_buf & CACHELINE_MASK));
667 } else {
668 hw_p->rx = hw_p->alloc_rx_buf;
669 }
670
671 for (i = 0; i < NUM_TX_BUFF; i++) {
672 hw_p->tx[i].ctrl = 0;
673 hw_p->tx[i].data_len = 0;
674 if (hw_p->first_init == 0) {
675 hw_p->txbuf_ptr =
676 (char *) malloc (ENET_MAX_MTU_ALIGNED);
677 if (NULL == hw_p->txbuf_ptr) {
678 free(hw_p->alloc_rx_buf);
679 free(hw_p->alloc_tx_buf);
680 hw_p->alloc_rx_buf = NULL;
681 hw_p->alloc_tx_buf = NULL;
682 for(j = 0; j < i; j++) {
683 free(hw_p->tx[i].data_ptr);
684 hw_p->tx[i].data_ptr = NULL;
685 }
686 }
687 }
688 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
689 if ((NUM_TX_BUFF - 1) == i)
690 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
691 hw_p->tx_run[i] = -1;
692 #if 0
693 printf ("TX_BUFF %d @ 0x%08lx\n", i,
694 (ulong) hw_p->tx[i].data_ptr);
695 #endif
696 }
697
698 for (i = 0; i < NUM_RX_BUFF; i++) {
699 hw_p->rx[i].ctrl = 0;
700 hw_p->rx[i].data_len = 0;
701 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
702 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
703 if ((NUM_RX_BUFF - 1) == i)
704 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
705 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
706 hw_p->rx_ready[i] = -1;
707 #if 0
708 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
709 #endif
710 }
711
712 reg = 0x00000000;
713
714 reg |= dev->enetaddr[0]; /* set high address */
715 reg = reg << 8;
716 reg |= dev->enetaddr[1];
717
718 out32 (EMAC_IAH + hw_p->hw_addr, reg);
719
720 reg = 0x00000000;
721 reg |= dev->enetaddr[2]; /* set low address */
722 reg = reg << 8;
723 reg |= dev->enetaddr[3];
724 reg = reg << 8;
725 reg |= dev->enetaddr[4];
726 reg = reg << 8;
727 reg |= dev->enetaddr[5];
728
729 out32 (EMAC_IAL + hw_p->hw_addr, reg);
730
731 switch (devnum) {
732 case 1:
733 /* setup MAL tx & rx channel pointers */
734 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
735 mtdcr (maltxctp2r, hw_p->tx);
736 #else
737 mtdcr (maltxctp1r, hw_p->tx);
738 #endif
739 #if defined(CONFIG_440)
740 mtdcr (maltxbattr, 0x0);
741 mtdcr (malrxbattr, 0x0);
742 #endif
743 mtdcr (malrxctp1r, hw_p->rx);
744 /* set RX buffer size */
745 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
746 break;
747 #if defined (CONFIG_440GX)
748 case 2:
749 /* setup MAL tx & rx channel pointers */
750 mtdcr (maltxbattr, 0x0);
751 mtdcr (malrxbattr, 0x0);
752 mtdcr (maltxctp2r, hw_p->tx);
753 mtdcr (malrxctp2r, hw_p->rx);
754 /* set RX buffer size */
755 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
756 break;
757 case 3:
758 /* setup MAL tx & rx channel pointers */
759 mtdcr (maltxbattr, 0x0);
760 mtdcr (maltxctp3r, hw_p->tx);
761 mtdcr (malrxbattr, 0x0);
762 mtdcr (malrxctp3r, hw_p->rx);
763 /* set RX buffer size */
764 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
765 break;
766 #endif /* CONFIG_440GX */
767 case 0:
768 default:
769 /* setup MAL tx & rx channel pointers */
770 #if defined(CONFIG_440)
771 mtdcr (maltxbattr, 0x0);
772 mtdcr (malrxbattr, 0x0);
773 #endif
774 mtdcr (maltxctp0r, hw_p->tx);
775 mtdcr (malrxctp0r, hw_p->rx);
776 /* set RX buffer size */
777 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
778 break;
779 }
780
781 /* Enable MAL transmit and receive channels */
782 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
783 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
784 #else
785 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
786 #endif
787 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
788
789 /* set transmit enable & receive enable */
790 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
791
792 /* set receive fifo to 4k and tx fifo to 2k */
793 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
794 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
795
796 /* set speed */
797 if (speed == _1000BASET) {
798 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
799 unsigned long pfc1;
800 mfsdr (sdr_pfc1, pfc1);
801 pfc1 |= SDR0_PFC1_EM_1000;
802 mtsdr (sdr_pfc1, pfc1);
803 #endif
804 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
805 } else if (speed == _100BASET)
806 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
807 else
808 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
809 if (duplex == FULL)
810 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
811
812 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
813
814 /* Enable broadcast and indvidual address */
815 /* TBS: enabling runts as some misbehaved nics will send runts */
816 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
817
818 /* we probably need to set the tx mode1 reg? maybe at tx time */
819
820 /* set transmit request threshold register */
821 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
822
823 /* set receive low/high water mark register */
824 #if defined(CONFIG_440)
825 /* 440s has a 64 byte burst length */
826 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
827 #else
828 /* 405s have a 16 byte burst length */
829 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
830 #endif /* defined(CONFIG_440) */
831 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
832
833 /* Set fifo limit entry in tx mode 0 */
834 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
835 /* Frame gap set */
836 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
837
838 /* Set EMAC IER */
839 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
840 if (speed == _100BASET)
841 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
842
843 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
844 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
845
846 if (hw_p->first_init == 0) {
847 /*
848 * Connect interrupt service routines
849 */
850 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
851 (interrupt_handler_t *) enetInt, dev);
852 }
853
854 mtmsr (msr); /* enable interrupts again */
855
856 hw_p->bis = bis;
857 hw_p->first_init = 1;
858
859 return (1);
860 }
861
862
863 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
864 int len)
865 {
866 struct enet_frame *ef_ptr;
867 ulong time_start, time_now;
868 unsigned long temp_txm0;
869 EMAC_4XX_HW_PST hw_p = dev->priv;
870
871 ef_ptr = (struct enet_frame *) ptr;
872
873 /*-----------------------------------------------------------------------+
874 * Copy in our address into the frame.
875 *-----------------------------------------------------------------------*/
876 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
877
878 /*-----------------------------------------------------------------------+
879 * If frame is too long or too short, modify length.
880 *-----------------------------------------------------------------------*/
881 /* TBS: where does the fragment go???? */
882 if (len > ENET_MAX_MTU)
883 len = ENET_MAX_MTU;
884
885 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
886 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
887
888 /*-----------------------------------------------------------------------+
889 * set TX Buffer busy, and send it
890 *-----------------------------------------------------------------------*/
891 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
892 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
893 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
894 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
895 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
896
897 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
898 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
899
900 __asm__ volatile ("eieio");
901
902 out32 (EMAC_TXM0 + hw_p->hw_addr,
903 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
904 #ifdef INFO_4XX_ENET
905 hw_p->stats.pkts_tx++;
906 #endif
907
908 /*-----------------------------------------------------------------------+
909 * poll unitl the packet is sent and then make sure it is OK
910 *-----------------------------------------------------------------------*/
911 time_start = get_timer (0);
912 while (1) {
913 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
914 /* loop until either TINT turns on or 3 seconds elapse */
915 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
916 /* transmit is done, so now check for errors
917 * If there is an error, an interrupt should
918 * happen when we return
919 */
920 time_now = get_timer (0);
921 if ((time_now - time_start) > 3000) {
922 return (-1);
923 }
924 } else {
925 return (len);
926 }
927 }
928 }
929
930
931 #if defined (CONFIG_440)
932
933 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
934 /*
935 * Hack: On 440SP all enet irq sources are located on UIC1
936 * Needs some cleanup. --sr
937 */
938 #define UIC0MSR uic1msr
939 #define UIC0SR uic1sr
940 #else
941 #define UIC0MSR uic0msr
942 #define UIC0SR uic0sr
943 #endif
944
945 int enetInt (struct eth_device *dev)
946 {
947 int serviced;
948 int rc = -1; /* default to not us */
949 unsigned long mal_isr;
950 unsigned long emac_isr = 0;
951 unsigned long mal_rx_eob;
952 unsigned long my_uic0msr, my_uic1msr;
953
954 #if defined(CONFIG_440GX)
955 unsigned long my_uic2msr;
956 #endif
957 EMAC_4XX_HW_PST hw_p;
958
959 /*
960 * Because the mal is generic, we need to get the current
961 * eth device
962 */
963 #if defined(CONFIG_NET_MULTI)
964 dev = eth_get_dev();
965 #else
966 dev = emac0_dev;
967 #endif
968
969 hw_p = dev->priv;
970
971 /* enter loop that stays in interrupt code until nothing to service */
972 do {
973 serviced = 0;
974
975 my_uic0msr = mfdcr (UIC0MSR);
976 my_uic1msr = mfdcr (uic1msr);
977 #if defined(CONFIG_440GX)
978 my_uic2msr = mfdcr (uic2msr);
979 #endif
980 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
981 && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
982 /* not for us */
983 return (rc);
984 }
985 #if defined (CONFIG_440GX)
986 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
987 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
988 /* not for us */
989 return (rc);
990 }
991 #endif
992 /* get and clear controller status interrupts */
993 /* look at Mal and EMAC interrupts */
994 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
995 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
996 /* we have a MAL interrupt */
997 mal_isr = mfdcr (malesr);
998 /* look for mal error */
999 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
1000 mal_err (dev, mal_isr, my_uic0msr,
1001 MAL_UIC_DEF, MAL_UIC_ERR);
1002 serviced = 1;
1003 rc = 0;
1004 }
1005 }
1006
1007 /* port by port dispatch of emac interrupts */
1008 if (hw_p->devnum == 0) {
1009 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
1010 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1011 if ((hw_p->emac_ier & emac_isr) != 0) {
1012 emac_err (dev, emac_isr);
1013 serviced = 1;
1014 rc = 0;
1015 }
1016 }
1017 if ((hw_p->emac_ier & emac_isr)
1018 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1019 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1020 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1021 return (rc); /* we had errors so get out */
1022 }
1023 }
1024
1025 #if !defined(CONFIG_440SP)
1026 if (hw_p->devnum == 1) {
1027 if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
1028 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1029 if ((hw_p->emac_ier & emac_isr) != 0) {
1030 emac_err (dev, emac_isr);
1031 serviced = 1;
1032 rc = 0;
1033 }
1034 }
1035 if ((hw_p->emac_ier & emac_isr)
1036 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1037 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1038 mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1039 return (rc); /* we had errors so get out */
1040 }
1041 }
1042 #if defined (CONFIG_440GX)
1043 if (hw_p->devnum == 2) {
1044 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
1045 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1046 if ((hw_p->emac_ier & emac_isr) != 0) {
1047 emac_err (dev, emac_isr);
1048 serviced = 1;
1049 rc = 0;
1050 }
1051 }
1052 if ((hw_p->emac_ier & emac_isr)
1053 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1054 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1055 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1056 mtdcr (uic2sr, UIC_ETH2);
1057 return (rc); /* we had errors so get out */
1058 }
1059 }
1060
1061 if (hw_p->devnum == 3) {
1062 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
1063 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1064 if ((hw_p->emac_ier & emac_isr) != 0) {
1065 emac_err (dev, emac_isr);
1066 serviced = 1;
1067 rc = 0;
1068 }
1069 }
1070 if ((hw_p->emac_ier & emac_isr)
1071 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1072 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1073 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1074 mtdcr (uic2sr, UIC_ETH3);
1075 return (rc); /* we had errors so get out */
1076 }
1077 }
1078 #endif /* CONFIG_440GX */
1079 #endif /* !CONFIG_440SP */
1080
1081 /* handle MAX TX EOB interrupt from a tx */
1082 if (my_uic0msr & UIC_MTE) {
1083 mal_rx_eob = mfdcr (maltxeobisr);
1084 mtdcr (maltxeobisr, mal_rx_eob);
1085 mtdcr (UIC0SR, UIC_MTE);
1086 }
1087 /* handle MAL RX EOB interupt from a receive */
1088 /* check for EOB on valid channels */
1089 if (my_uic0msr & UIC_MRE) {
1090 mal_rx_eob = mfdcr (malrxeobisr);
1091 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1092 /* clear EOB
1093 mtdcr(malrxeobisr, mal_rx_eob); */
1094 enet_rcv (dev, emac_isr);
1095 /* indicate that we serviced an interrupt */
1096 serviced = 1;
1097 rc = 0;
1098 }
1099 }
1100
1101 mtdcr (UIC0SR, UIC_MRE); /* Clear */
1102 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1103 switch (hw_p->devnum) {
1104 case 0:
1105 mtdcr (uic1sr, UIC_ETH0);
1106 break;
1107 case 1:
1108 mtdcr (uic1sr, UIC_ETH1);
1109 break;
1110 #if defined (CONFIG_440GX)
1111 case 2:
1112 mtdcr (uic2sr, UIC_ETH2);
1113 break;
1114 case 3:
1115 mtdcr (uic2sr, UIC_ETH3);
1116 break;
1117 #endif /* CONFIG_440GX */
1118 default:
1119 break;
1120 }
1121 } while (serviced);
1122
1123 return (rc);
1124 }
1125
1126 #else /* CONFIG_440 */
1127
1128 int enetInt (struct eth_device *dev)
1129 {
1130 int serviced;
1131 int rc = -1; /* default to not us */
1132 unsigned long mal_isr;
1133 unsigned long emac_isr = 0;
1134 unsigned long mal_rx_eob;
1135 unsigned long my_uicmsr;
1136
1137 EMAC_4XX_HW_PST hw_p;
1138
1139 /*
1140 * Because the mal is generic, we need to get the current
1141 * eth device
1142 */
1143 #if defined(CONFIG_NET_MULTI)
1144 dev = eth_get_dev();
1145 #else
1146 dev = emac0_dev;
1147 #endif
1148
1149 hw_p = dev->priv;
1150
1151 /* enter loop that stays in interrupt code until nothing to service */
1152 do {
1153 serviced = 0;
1154
1155 my_uicmsr = mfdcr (uicmsr);
1156
1157 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1158 return (rc);
1159 }
1160 /* get and clear controller status interrupts */
1161 /* look at Mal and EMAC interrupts */
1162 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1163 mal_isr = mfdcr (malesr);
1164 /* look for mal error */
1165 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1166 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1167 serviced = 1;
1168 rc = 0;
1169 }
1170 }
1171
1172 /* port by port dispatch of emac interrupts */
1173
1174 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1175 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1176 if ((hw_p->emac_ier & emac_isr) != 0) {
1177 emac_err (dev, emac_isr);
1178 serviced = 1;
1179 rc = 0;
1180 }
1181 }
1182 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1183 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1184 return (rc); /* we had errors so get out */
1185 }
1186
1187 /* handle MAX TX EOB interrupt from a tx */
1188 if (my_uicmsr & UIC_MAL_TXEOB) {
1189 mal_rx_eob = mfdcr (maltxeobisr);
1190 mtdcr (maltxeobisr, mal_rx_eob);
1191 mtdcr (uicsr, UIC_MAL_TXEOB);
1192 }
1193 /* handle MAL RX EOB interupt from a receive */
1194 /* check for EOB on valid channels */
1195 if (my_uicmsr & UIC_MAL_RXEOB)
1196 {
1197 mal_rx_eob = mfdcr (malrxeobisr);
1198 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1199 /* clear EOB
1200 mtdcr(malrxeobisr, mal_rx_eob); */
1201 enet_rcv (dev, emac_isr);
1202 /* indicate that we serviced an interrupt */
1203 serviced = 1;
1204 rc = 0;
1205 }
1206 }
1207 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1208 }
1209 while (serviced);
1210
1211 return (rc);
1212 }
1213
1214 #endif /* CONFIG_440 */
1215
1216 /*-----------------------------------------------------------------------------+
1217 * MAL Error Routine
1218 *-----------------------------------------------------------------------------*/
1219 static void mal_err (struct eth_device *dev, unsigned long isr,
1220 unsigned long uic, unsigned long maldef,
1221 unsigned long mal_errr)
1222 {
1223 EMAC_4XX_HW_PST hw_p = dev->priv;
1224
1225 mtdcr (malesr, isr); /* clear interrupt */
1226
1227 /* clear DE interrupt */
1228 mtdcr (maltxdeir, 0xC0000000);
1229 mtdcr (malrxdeir, 0x80000000);
1230
1231 #ifdef INFO_4XX_ENET
1232 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1233 #endif
1234
1235 eth_init (hw_p->bis); /* start again... */
1236 }
1237
1238 /*-----------------------------------------------------------------------------+
1239 * EMAC Error Routine
1240 *-----------------------------------------------------------------------------*/
1241 static void emac_err (struct eth_device *dev, unsigned long isr)
1242 {
1243 EMAC_4XX_HW_PST hw_p = dev->priv;
1244
1245 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1246 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1247 }
1248
1249 /*-----------------------------------------------------------------------------+
1250 * enet_rcv() handles the ethernet receive data
1251 *-----------------------------------------------------------------------------*/
1252 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1253 {
1254 struct enet_frame *ef_ptr;
1255 unsigned long data_len;
1256 unsigned long rx_eob_isr;
1257 EMAC_4XX_HW_PST hw_p = dev->priv;
1258
1259 int handled = 0;
1260 int i;
1261 int loop_count = 0;
1262
1263 rx_eob_isr = mfdcr (malrxeobisr);
1264 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1265 /* clear EOB */
1266 mtdcr (malrxeobisr, rx_eob_isr);
1267
1268 /* EMAC RX done */
1269 while (1) { /* do all */
1270 i = hw_p->rx_slot;
1271
1272 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1273 || (loop_count >= NUM_RX_BUFF))
1274 break;
1275 loop_count++;
1276 hw_p->rx_slot++;
1277 if (NUM_RX_BUFF == hw_p->rx_slot)
1278 hw_p->rx_slot = 0;
1279 handled++;
1280 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1281 if (data_len) {
1282 if (data_len > ENET_MAX_MTU) /* Check len */
1283 data_len = 0;
1284 else {
1285 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1286 data_len = 0;
1287 hw_p->stats.rx_err_log[hw_p->
1288 rx_err_index]
1289 = hw_p->rx[i].ctrl;
1290 hw_p->rx_err_index++;
1291 if (hw_p->rx_err_index ==
1292 MAX_ERR_LOG)
1293 hw_p->rx_err_index =
1294 0;
1295 } /* emac_erros */
1296 } /* data_len < max mtu */
1297 } /* if data_len */
1298 if (!data_len) { /* no data */
1299 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1300
1301 hw_p->stats.data_len_err++; /* Error at Rx */
1302 }
1303
1304 /* !data_len */
1305 /* AS.HARNOIS */
1306 /* Check if user has already eaten buffer */
1307 /* if not => ERROR */
1308 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1309 if (hw_p->is_receiving)
1310 printf ("ERROR : Receive buffers are full!\n");
1311 break;
1312 } else {
1313 hw_p->stats.rx_frames++;
1314 hw_p->stats.rx += data_len;
1315 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1316 data_ptr;
1317 #ifdef INFO_4XX_ENET
1318 hw_p->stats.pkts_rx++;
1319 #endif
1320 /* AS.HARNOIS
1321 * use ring buffer
1322 */
1323 hw_p->rx_ready[hw_p->rx_i_index] = i;
1324 hw_p->rx_i_index++;
1325 if (NUM_RX_BUFF == hw_p->rx_i_index)
1326 hw_p->rx_i_index = 0;
1327
1328 /* AS.HARNOIS
1329 * free receive buffer only when
1330 * buffer has been handled (eth_rx)
1331 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1332 */
1333 } /* if data_len */
1334 } /* while */
1335 } /* if EMACK_RXCHL */
1336 }
1337
1338
1339 static int ppc_4xx_eth_rx (struct eth_device *dev)
1340 {
1341 int length;
1342 int user_index;
1343 unsigned long msr;
1344 EMAC_4XX_HW_PST hw_p = dev->priv;
1345
1346 hw_p->is_receiving = 1; /* tell driver */
1347
1348 for (;;) {
1349 /* AS.HARNOIS
1350 * use ring buffer and
1351 * get index from rx buffer desciptor queue
1352 */
1353 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1354 if (user_index == -1) {
1355 length = -1;
1356 break; /* nothing received - leave for() loop */
1357 }
1358
1359 msr = mfmsr ();
1360 mtmsr (msr & ~(MSR_EE));
1361
1362 length = hw_p->rx[user_index].data_len;
1363
1364 /* Pass the packet up to the protocol layers. */
1365 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1366 /* NetReceive(NetRxPackets[i], length); */
1367 NetReceive (NetRxPackets[user_index], length - 4);
1368 /* Free Recv Buffer */
1369 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1370 /* Free rx buffer descriptor queue */
1371 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1372 hw_p->rx_u_index++;
1373 if (NUM_RX_BUFF == hw_p->rx_u_index)
1374 hw_p->rx_u_index = 0;
1375
1376 #ifdef INFO_4XX_ENET
1377 hw_p->stats.pkts_handled++;
1378 #endif
1379
1380 mtmsr (msr); /* Enable IRQ's */
1381 }
1382
1383 hw_p->is_receiving = 0; /* tell driver */
1384
1385 return length;
1386 }
1387
1388 int ppc_4xx_eth_initialize (bd_t * bis)
1389 {
1390 static int virgin = 0;
1391 struct eth_device *dev;
1392 int eth_num = 0;
1393 EMAC_4XX_HW_PST hw = NULL;
1394
1395 #if defined(CONFIG_440GX)
1396 unsigned long pfc1;
1397
1398 mfsdr (sdr_pfc1, pfc1);
1399 pfc1 &= ~(0x01e00000);
1400 pfc1 |= 0x01200000;
1401 mtsdr (sdr_pfc1, pfc1);
1402 #endif
1403 /* set phy num and mode */
1404 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1405 bis->bi_phymode[0] = 0;
1406
1407 #if defined(CONFIG_PHY1_ADDR)
1408 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1409 bis->bi_phymode[1] = 0;
1410 #endif
1411 #if defined(CONFIG_440GX)
1412 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1413 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1414 bis->bi_phymode[2] = 2;
1415 bis->bi_phymode[3] = 2;
1416
1417 ppc_4xx_eth_setup_bridge(0, bis);
1418 #endif
1419
1420 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1421
1422 /* See if we can actually bring up the interface, otherwise, skip it */
1423 switch (eth_num) {
1424 default: /* fall through */
1425 case 0:
1426 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1427 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1428 continue;
1429 }
1430 break;
1431 #ifdef CONFIG_HAS_ETH1
1432 case 1:
1433 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
1434 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1435 continue;
1436 }
1437 break;
1438 #endif
1439 #ifdef CONFIG_HAS_ETH2
1440 case 2:
1441 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
1442 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1443 continue;
1444 }
1445 break;
1446 #endif
1447 #ifdef CONFIG_HAS_ETH3
1448 case 3:
1449 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
1450 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1451 continue;
1452 }
1453 break;
1454 #endif
1455 }
1456
1457 /* Allocate device structure */
1458 dev = (struct eth_device *) malloc (sizeof (*dev));
1459 if (dev == NULL) {
1460 printf ("ppc_4xx_eth_initialize: "
1461 "Cannot allocate eth_device %d\n", eth_num);
1462 return (-1);
1463 }
1464 memset(dev, 0, sizeof(*dev));
1465
1466 /* Allocate our private use data */
1467 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1468 if (hw == NULL) {
1469 printf ("ppc_4xx_eth_initialize: "
1470 "Cannot allocate private hw data for eth_device %d",
1471 eth_num);
1472 free (dev);
1473 return (-1);
1474 }
1475 memset(hw, 0, sizeof(*hw));
1476
1477 switch (eth_num) {
1478 default: /* fall through */
1479 case 0:
1480 hw->hw_addr = 0;
1481 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1482 break;
1483 #ifdef CONFIG_HAS_ETH1
1484 case 1:
1485 hw->hw_addr = 0x100;
1486 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1487 break;
1488 #endif
1489 #ifdef CONFIG_HAS_ETH2
1490 case 2:
1491 hw->hw_addr = 0x400;
1492 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1493 break;
1494 #endif
1495 #ifdef CONFIG_HAS_ETH3
1496 case 3:
1497 hw->hw_addr = 0x600;
1498 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1499 break;
1500 #endif
1501 }
1502
1503 hw->devnum = eth_num;
1504 hw->print_speed = 1;
1505
1506 sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
1507 dev->priv = (void *) hw;
1508 dev->init = ppc_4xx_eth_init;
1509 dev->halt = ppc_4xx_eth_halt;
1510 dev->send = ppc_4xx_eth_send;
1511 dev->recv = ppc_4xx_eth_rx;
1512
1513 if (0 == virgin) {
1514 /* set the MAL IER ??? names may change with new spec ??? */
1515 #if defined(CONFIG_440SPE)
1516 mal_ier =
1517 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1518 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1519 #else
1520 mal_ier =
1521 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1522 MAL_IER_OPBE | MAL_IER_PLBE;
1523 #endif
1524 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1525 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1526 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1527 mtdcr (malier, mal_ier);
1528
1529 /* install MAL interrupt handler */
1530 irq_install_handler (VECNUM_MS,
1531 (interrupt_handler_t *) enetInt,
1532 dev);
1533 irq_install_handler (VECNUM_MTE,
1534 (interrupt_handler_t *) enetInt,
1535 dev);
1536 irq_install_handler (VECNUM_MRE,
1537 (interrupt_handler_t *) enetInt,
1538 dev);
1539 irq_install_handler (VECNUM_TXDE,
1540 (interrupt_handler_t *) enetInt,
1541 dev);
1542 irq_install_handler (VECNUM_RXDE,
1543 (interrupt_handler_t *) enetInt,
1544 dev);
1545 virgin = 1;
1546 }
1547
1548 #if defined(CONFIG_NET_MULTI)
1549 eth_register (dev);
1550 #else
1551 emac0_dev = dev;
1552 #endif
1553
1554 #if defined(CONFIG_NET_MULTI)
1555 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1556 miiphy_register (dev->name,
1557 emac4xx_miiphy_read, emac4xx_miiphy_write);
1558 #endif
1559 #endif
1560 } /* end for each supported device */
1561 return (1);
1562 }
1563
1564
1565 #if !defined(CONFIG_NET_MULTI)
1566 void eth_halt (void) {
1567 if (emac0_dev) {
1568 ppc_4xx_eth_halt(emac0_dev);
1569 free(emac0_dev);
1570 emac0_dev = NULL;
1571 }
1572 }
1573
1574 int eth_init (bd_t *bis)
1575 {
1576 ppc_4xx_eth_initialize(bis);
1577 if (emac0_dev) {
1578 return ppc_4xx_eth_init(emac0_dev, bis);
1579 } else {
1580 printf("ERROR: ethaddr not set!\n");
1581 return -1;
1582 }
1583 }
1584
1585 int eth_send(volatile void *packet, int length)
1586 {
1587 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1588 }
1589
1590 int eth_rx(void)
1591 {
1592 return (ppc_4xx_eth_rx(emac0_dev));
1593 }
1594
1595 int emac4xx_miiphy_initialize (bd_t * bis)
1596 {
1597 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1598 miiphy_register ("ppc_4xx_eth0",
1599 emac4xx_miiphy_read, emac4xx_miiphy_write);
1600 #endif
1601
1602 return 0;
1603 }
1604 #endif /* !defined(CONFIG_NET_MULTI) */
1605
1606 #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */
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