1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
85 #include <asm/cache.h>
89 #include <ppc4xx_enet.h>
95 * Only compile for platform with AMCC EMAC ethernet controller and
96 * network support enabled.
97 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
99 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
101 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
102 #error "CONFIG_MII has to be defined!"
105 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
106 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
109 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
110 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
112 /* Ethernet Transmit and Receive Buffers */
114 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
115 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
117 #define ENET_MAX_MTU PKTSIZE
118 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
120 /*-----------------------------------------------------------------------------+
121 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
122 * Interrupt Controller).
123 *-----------------------------------------------------------------------------*/
124 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
126 #if defined(CONFIG_HAS_ETH3)
127 #if !defined(CONFIG_440GX)
128 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
129 UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
131 /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
132 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
133 #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
134 #endif /* !defined(CONFIG_440GX) */
135 #elif defined(CONFIG_HAS_ETH2)
136 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
137 UIC_MASK(ETH_IRQ_NUM(2)))
138 #elif defined(CONFIG_HAS_ETH1)
139 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
141 #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
145 * Define a default version for UIC_ETHxB for non 440GX so that we can
146 * use common code for all 4xx variants
148 #if !defined(UIC_ETHxB)
152 #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
153 #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
154 #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
155 #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
156 #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
158 #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
159 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
162 * We have 3 different interrupt types:
163 * - MAL interrupts indicating successful transfer
164 * - MAL error interrupts indicating MAL related errors
165 * - EMAC interrupts indicating EMAC related errors
167 * All those interrupts can be on different UIC's, but since
168 * now at least all interrupts from one type are on the same
169 * UIC. Only exception is 440GX where the EMAC interrupts are
170 * spread over two UIC's!
172 #if defined(CONFIG_440GX)
173 #define UIC_BASE_MAL UIC1_DCR_BASE
174 #define UIC_BASE_MAL_ERR UIC2_DCR_BASE
175 #define UIC_BASE_EMAC UIC2_DCR_BASE
176 #define UIC_BASE_EMAC_B UIC3_DCR_BASE
178 #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
179 #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
180 #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
181 #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
186 #define BI_PHYMODE_NONE 0
187 #define BI_PHYMODE_ZMII 1
188 #define BI_PHYMODE_RGMII 2
189 #define BI_PHYMODE_GMII 3
190 #define BI_PHYMODE_RTBI 4
191 #define BI_PHYMODE_TBI 5
192 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
193 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
194 defined(CONFIG_405EX)
195 #define BI_PHYMODE_SMII 6
196 #define BI_PHYMODE_MII 7
197 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
198 #define BI_PHYMODE_RMII 8
202 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
203 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
204 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
205 defined(CONFIG_405EX)
206 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
209 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
210 #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
213 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
214 #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
216 #define MAL_RX_CHAN_MUL 1
219 /*-----------------------------------------------------------------------------+
220 * Global variables. TX and RX descriptors and buffers.
221 *-----------------------------------------------------------------------------*/
222 #if !defined(CONFIG_NET_MULTI)
223 struct eth_device
*emac0_dev
= NULL
;
227 * Get count of EMAC devices (doesn't have to be the max. possible number
228 * supported by the cpu)
230 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
231 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
232 * 405EX/405EXr eval board, using the same binary.
234 #if defined(CONFIG_BOARD_EMAC_COUNT)
235 #define LAST_EMAC_NUM board_emac_count()
236 #else /* CONFIG_BOARD_EMAC_COUNT */
237 #if defined(CONFIG_HAS_ETH3)
238 #define LAST_EMAC_NUM 4
239 #elif defined(CONFIG_HAS_ETH2)
240 #define LAST_EMAC_NUM 3
241 #elif defined(CONFIG_HAS_ETH1)
242 #define LAST_EMAC_NUM 2
244 #define LAST_EMAC_NUM 1
246 #endif /* CONFIG_BOARD_EMAC_COUNT */
248 /* normal boards start with EMAC0 */
249 #if !defined(CONFIG_EMAC_NR_START)
250 #define CONFIG_EMAC_NR_START 0
253 #define MAL_RX_DESC_SIZE 2048
254 #define MAL_TX_DESC_SIZE 2048
255 #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
257 /*-----------------------------------------------------------------------------+
258 * Prototypes and externals.
259 *-----------------------------------------------------------------------------*/
260 static void enet_rcv (struct eth_device
*dev
, unsigned long malisr
);
262 int enetInt (struct eth_device
*dev
);
263 static void mal_err (struct eth_device
*dev
, unsigned long isr
,
264 unsigned long uic
, unsigned long maldef
,
265 unsigned long mal_errr
);
266 static void emac_err (struct eth_device
*dev
, unsigned long isr
);
268 extern int phy_setup_aneg (char *devname
, unsigned char addr
);
269 extern int emac4xx_miiphy_read (char *devname
, unsigned char addr
,
270 unsigned char reg
, unsigned short *value
);
271 extern int emac4xx_miiphy_write (char *devname
, unsigned char addr
,
272 unsigned char reg
, unsigned short value
);
274 int board_emac_count(void);
276 static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p
)
278 #if defined(CONFIG_440SPE) || \
279 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
280 defined(CONFIG_405EX)
284 val
|= SDR0_MFR_ETH_CLK_SEL_V(hw_p
->devnum
);
286 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
289 mfsdr(SDR0_ETH_CFG
, val
);
290 val
|= SDR0_ETH_CFG_CLK_SEL_V(hw_p
->devnum
);
291 mtsdr(SDR0_ETH_CFG
, val
);
295 static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p
)
297 #if defined(CONFIG_440SPE) || \
298 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
299 defined(CONFIG_405EX)
303 val
&= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p
->devnum
);
305 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
308 mfsdr(SDR0_ETH_CFG
, val
);
309 val
&= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p
->devnum
);
310 mtsdr(SDR0_ETH_CFG
, val
);
314 /*-----------------------------------------------------------------------------+
316 | Disable MAL channel, and EMACn
317 +-----------------------------------------------------------------------------*/
318 static void ppc_4xx_eth_halt (struct eth_device
*dev
)
320 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
323 out_be32((void *)EMAC_IER
+ hw_p
->hw_addr
, 0x00000000); /* disable emac interrupts */
325 /* 1st reset MAL channel */
326 /* Note: writing a 0 to a channel has no effect */
327 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
328 mtdcr (maltxcarr
, (MAL_CR_MMSR
>> (hw_p
->devnum
* 2)));
330 mtdcr (maltxcarr
, (MAL_CR_MMSR
>> hw_p
->devnum
));
332 mtdcr (malrxcarr
, (MAL_CR_MMSR
>> hw_p
->devnum
));
335 while (mfdcr (malrxcasr
) & (MAL_CR_MMSR
>> hw_p
->devnum
)) {
336 udelay (1000); /* Delay 1 MS so as not to hammer the register */
342 /* provide clocks for EMAC internal loopback */
343 emac_loopback_enable(hw_p
);
346 out_be32((void *)EMAC_M0
+ hw_p
->hw_addr
, EMAC_M0_SRST
);
348 /* remove clocks for EMAC internal loopback */
349 emac_loopback_disable(hw_p
);
351 #ifndef CONFIG_NETCONSOLE
352 hw_p
->print_speed
= 1; /* print speed message again next time */
355 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
356 /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
357 mfsdr(SDR0_ETH_CFG
, val
);
358 val
&= ~(SDR0_ETH_CFG_TAHOE0_BYPASS
| SDR0_ETH_CFG_TAHOE1_BYPASS
);
359 mtsdr(SDR0_ETH_CFG
, val
);
365 #if defined (CONFIG_440GX)
366 int ppc_4xx_eth_setup_bridge(int devnum
, bd_t
* bis
)
369 unsigned long zmiifer
;
370 unsigned long rmiifer
;
372 mfsdr(sdr_pfc1
, pfc1
);
373 pfc1
= SDR0_PFC1_EPS_DECODE(pfc1
);
380 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(0);
381 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(1);
382 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(2);
383 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(3);
384 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
385 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
386 bis
->bi_phymode
[2] = BI_PHYMODE_ZMII
;
387 bis
->bi_phymode
[3] = BI_PHYMODE_ZMII
;
390 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(0);
391 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(1);
392 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(2);
393 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(3);
394 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
395 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
396 bis
->bi_phymode
[2] = BI_PHYMODE_ZMII
;
397 bis
->bi_phymode
[3] = BI_PHYMODE_ZMII
;
400 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(0);
401 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V(2);
402 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
403 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
404 bis
->bi_phymode
[2] = BI_PHYMODE_RGMII
;
405 bis
->bi_phymode
[3] = BI_PHYMODE_NONE
;
408 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(0);
409 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(1);
410 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V (2);
411 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V (3);
412 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
413 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
414 bis
->bi_phymode
[2] = BI_PHYMODE_RGMII
;
415 bis
->bi_phymode
[3] = BI_PHYMODE_RGMII
;
418 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V (0);
419 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V (1);
420 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V (2);
421 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V(3);
422 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
423 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
424 bis
->bi_phymode
[2] = BI_PHYMODE_ZMII
;
425 bis
->bi_phymode
[3] = BI_PHYMODE_RGMII
;
428 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V (0);
429 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V (1);
430 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V(2);
431 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
432 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
433 bis
->bi_phymode
[2] = BI_PHYMODE_RGMII
;
437 zmiifer
= ZMII_FER_MII
<< ZMII_FER_V(devnum
);
439 bis
->bi_phymode
[0] = BI_PHYMODE_ZMII
;
440 bis
->bi_phymode
[1] = BI_PHYMODE_ZMII
;
441 bis
->bi_phymode
[2] = BI_PHYMODE_ZMII
;
442 bis
->bi_phymode
[3] = BI_PHYMODE_ZMII
;
446 /* Ensure we setup mdio for this devnum and ONLY this devnum */
447 zmiifer
|= (ZMII_FER_MDI
) << ZMII_FER_V(devnum
);
449 out_be32((void *)ZMII_FER
, zmiifer
);
450 out_be32((void *)RGMII_FER
, rmiifer
);
454 #endif /* CONFIG_440_GX */
456 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
457 int ppc_4xx_eth_setup_bridge(int devnum
, bd_t
* bis
)
459 unsigned long zmiifer
=0x0;
462 mfsdr(sdr_pfc1
, pfc1
);
463 pfc1
&= SDR0_PFC1_SELECT_MASK
;
466 case SDR0_PFC1_SELECT_CONFIG_2
:
468 out_be32((void *)ZMII_FER
, 0x00);
469 out_be32((void *)RGMII_FER
, 0x00000037);
470 bis
->bi_phymode
[0] = BI_PHYMODE_GMII
;
471 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
473 case SDR0_PFC1_SELECT_CONFIG_4
:
474 /* 2 x RGMII ports */
475 out_be32((void *)ZMII_FER
, 0x00);
476 out_be32((void *)RGMII_FER
, 0x00000055);
477 bis
->bi_phymode
[0] = BI_PHYMODE_RGMII
;
478 bis
->bi_phymode
[1] = BI_PHYMODE_RGMII
;
480 case SDR0_PFC1_SELECT_CONFIG_6
:
482 out_be32((void *)ZMII_FER
,
483 ((ZMII_FER_SMII
) << ZMII_FER_V(0)) |
484 ((ZMII_FER_SMII
) << ZMII_FER_V(1)));
485 out_be32((void *)RGMII_FER
, 0x00000000);
486 bis
->bi_phymode
[0] = BI_PHYMODE_SMII
;
487 bis
->bi_phymode
[1] = BI_PHYMODE_SMII
;
489 case SDR0_PFC1_SELECT_CONFIG_1_2
:
490 /* only 1 x MII supported */
491 out_be32((void *)ZMII_FER
, (ZMII_FER_MII
) << ZMII_FER_V(0));
492 out_be32((void *)RGMII_FER
, 0x00000000);
493 bis
->bi_phymode
[0] = BI_PHYMODE_MII
;
494 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
500 /* Ensure we setup mdio for this devnum and ONLY this devnum */
501 zmiifer
= in_be32((void *)ZMII_FER
);
502 zmiifer
|= (ZMII_FER_MDI
) << ZMII_FER_V(devnum
);
503 out_be32((void *)ZMII_FER
, zmiifer
);
507 #endif /* CONFIG_440EPX */
509 #if defined(CONFIG_405EX)
510 int ppc_4xx_eth_setup_bridge(int devnum
, bd_t
* bis
)
515 * The 405EX(r)'s RGMII bridge can operate in one of several
516 * modes, only one of which (2 x RGMII) allows the
517 * simultaneous use of both EMACs on the 405EX.
520 switch (CONFIG_EMAC_PHY_MODE
) {
522 case EMAC_PHY_MODE_NONE
:
524 rgmiifer
|= RGMII_FER_DIS
<< 0;
525 rgmiifer
|= RGMII_FER_DIS
<< 4;
526 out_be32((void *)RGMII_FER
, rgmiifer
);
527 bis
->bi_phymode
[0] = BI_PHYMODE_NONE
;
528 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
530 case EMAC_PHY_MODE_NONE_RGMII
:
531 /* 1 x RGMII port on channel 0 */
532 rgmiifer
|= RGMII_FER_RGMII
<< 0;
533 rgmiifer
|= RGMII_FER_DIS
<< 4;
534 out_be32((void *)RGMII_FER
, rgmiifer
);
535 bis
->bi_phymode
[0] = BI_PHYMODE_RGMII
;
536 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
538 case EMAC_PHY_MODE_RGMII_NONE
:
539 /* 1 x RGMII port on channel 1 */
540 rgmiifer
|= RGMII_FER_DIS
<< 0;
541 rgmiifer
|= RGMII_FER_RGMII
<< 4;
542 out_be32((void *)RGMII_FER
, rgmiifer
);
543 bis
->bi_phymode
[0] = BI_PHYMODE_NONE
;
544 bis
->bi_phymode
[1] = BI_PHYMODE_RGMII
;
546 case EMAC_PHY_MODE_RGMII_RGMII
:
547 /* 2 x RGMII ports */
548 rgmiifer
|= RGMII_FER_RGMII
<< 0;
549 rgmiifer
|= RGMII_FER_RGMII
<< 4;
550 out_be32((void *)RGMII_FER
, rgmiifer
);
551 bis
->bi_phymode
[0] = BI_PHYMODE_RGMII
;
552 bis
->bi_phymode
[1] = BI_PHYMODE_RGMII
;
554 case EMAC_PHY_MODE_NONE_GMII
:
555 /* 1 x GMII port on channel 0 */
556 rgmiifer
|= RGMII_FER_GMII
<< 0;
557 rgmiifer
|= RGMII_FER_DIS
<< 4;
558 out_be32((void *)RGMII_FER
, rgmiifer
);
559 bis
->bi_phymode
[0] = BI_PHYMODE_GMII
;
560 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
562 case EMAC_PHY_MODE_NONE_MII
:
563 /* 1 x MII port on channel 0 */
564 rgmiifer
|= RGMII_FER_MII
<< 0;
565 rgmiifer
|= RGMII_FER_DIS
<< 4;
566 out_be32((void *)RGMII_FER
, rgmiifer
);
567 bis
->bi_phymode
[0] = BI_PHYMODE_MII
;
568 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
570 case EMAC_PHY_MODE_GMII_NONE
:
571 /* 1 x GMII port on channel 1 */
572 rgmiifer
|= RGMII_FER_DIS
<< 0;
573 rgmiifer
|= RGMII_FER_GMII
<< 4;
574 out_be32((void *)RGMII_FER
, rgmiifer
);
575 bis
->bi_phymode
[0] = BI_PHYMODE_NONE
;
576 bis
->bi_phymode
[1] = BI_PHYMODE_GMII
;
578 case EMAC_PHY_MODE_MII_NONE
:
579 /* 1 x MII port on channel 1 */
580 rgmiifer
|= RGMII_FER_DIS
<< 0;
581 rgmiifer
|= RGMII_FER_MII
<< 4;
582 out_be32((void *)RGMII_FER
, rgmiifer
);
583 bis
->bi_phymode
[0] = BI_PHYMODE_NONE
;
584 bis
->bi_phymode
[1] = BI_PHYMODE_MII
;
590 /* Ensure we setup mdio for this devnum and ONLY this devnum */
591 rgmiifer
= in_be32((void *)RGMII_FER
);
592 rgmiifer
|= (1 << (19-devnum
));
593 out_be32((void *)RGMII_FER
, rgmiifer
);
597 #endif /* CONFIG_405EX */
599 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
600 int ppc_4xx_eth_setup_bridge(int devnum
, bd_t
* bis
)
603 u32 zmiifer
; /* ZMII0_FER reg. */
604 u32 rmiifer
; /* RGMII0_FER reg. Bridge 0 */
605 u32 rmiifer1
; /* RGMII0_FER reg. Bridge 1 */
612 #if defined(CONFIG_460EX)
619 * NOTE: 460GT has 2 RGMII bridge cores:
620 * emac0 ------ RGMII0_BASE
624 * emac2 ------ RGMII1_BASE
628 * 460EX has 1 RGMII bridge core:
629 * and RGMII1_BASE is disabled
630 * emac0 ------ RGMII0_BASE
636 * Right now only 2*RGMII is supported. Please extend when needed.
642 /* GMC0 EMAC4_0, ZMII Bridge */
643 zmiifer
|= ZMII_FER_MII
<< ZMII_FER_V(0);
644 bis
->bi_phymode
[0] = BI_PHYMODE_MII
;
645 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
646 bis
->bi_phymode
[2] = BI_PHYMODE_NONE
;
647 bis
->bi_phymode
[3] = BI_PHYMODE_NONE
;
651 /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
652 zmiifer
|= ZMII_FER_MII
<< ZMII_FER_V(0);
653 zmiifer
|= ZMII_FER_MII
<< ZMII_FER_V(2);
654 bis
->bi_phymode
[0] = BI_PHYMODE_MII
;
655 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
656 bis
->bi_phymode
[2] = BI_PHYMODE_MII
;
657 bis
->bi_phymode
[3] = BI_PHYMODE_NONE
;
661 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
662 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(0);
663 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(1);
664 bis
->bi_phymode
[0] = BI_PHYMODE_RMII
;
665 bis
->bi_phymode
[1] = BI_PHYMODE_RMII
;
666 bis
->bi_phymode
[2] = BI_PHYMODE_NONE
;
667 bis
->bi_phymode
[3] = BI_PHYMODE_NONE
;
671 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
673 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(0);
674 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(1);
675 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(2);
676 zmiifer
|= ZMII_FER_RMII
<< ZMII_FER_V(3);
677 bis
->bi_phymode
[0] = BI_PHYMODE_RMII
;
678 bis
->bi_phymode
[1] = BI_PHYMODE_RMII
;
679 bis
->bi_phymode
[2] = BI_PHYMODE_RMII
;
680 bis
->bi_phymode
[3] = BI_PHYMODE_RMII
;
684 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
685 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(0);
686 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(1);
687 bis
->bi_phymode
[0] = BI_PHYMODE_SMII
;
688 bis
->bi_phymode
[1] = BI_PHYMODE_SMII
;
689 bis
->bi_phymode
[2] = BI_PHYMODE_NONE
;
690 bis
->bi_phymode
[3] = BI_PHYMODE_NONE
;
694 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
696 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(0);
697 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(1);
698 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(2);
699 zmiifer
|= ZMII_FER_SMII
<< ZMII_FER_V(3);
700 bis
->bi_phymode
[0] = BI_PHYMODE_SMII
;
701 bis
->bi_phymode
[1] = BI_PHYMODE_SMII
;
702 bis
->bi_phymode
[2] = BI_PHYMODE_SMII
;
703 bis
->bi_phymode
[3] = BI_PHYMODE_SMII
;
706 /* This is the default mode that we want for board bringup - Maple */
708 /* GMC0 EMAC4_0, RGMII Bridge 0 */
709 rmiifer
|= RGMII_FER_MDIO(0);
712 rmiifer
|= RGMII_FER_GMII
<< RGMII_FER_V(2); /* CH0CFG - EMAC0 */
713 bis
->bi_phymode
[0] = BI_PHYMODE_GMII
;
714 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
715 bis
->bi_phymode
[2] = BI_PHYMODE_NONE
;
716 bis
->bi_phymode
[3] = BI_PHYMODE_NONE
;
718 rmiifer
|= RGMII_FER_GMII
<< RGMII_FER_V(3); /* CH1CFG - EMAC1 */
719 bis
->bi_phymode
[0] = BI_PHYMODE_NONE
;
720 bis
->bi_phymode
[1] = BI_PHYMODE_GMII
;
721 bis
->bi_phymode
[2] = BI_PHYMODE_NONE
;
722 bis
->bi_phymode
[3] = BI_PHYMODE_NONE
;
727 /* GMC0 EMAC4_0, RGMII Bridge 0 */
728 /* GMC1 EMAC4_2, RGMII Bridge 1 */
729 rmiifer
|= RGMII_FER_GMII
<< RGMII_FER_V(2); /* CH0CFG - EMAC0 */
730 rmiifer1
|= RGMII_FER_GMII
<< RGMII_FER_V(2); /* CH0CFG - EMAC2 */
731 rmiifer
|= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
732 rmiifer1
|= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
734 bis
->bi_phymode
[0] = BI_PHYMODE_GMII
;
735 bis
->bi_phymode
[1] = BI_PHYMODE_NONE
;
736 bis
->bi_phymode
[2] = BI_PHYMODE_GMII
;
737 bis
->bi_phymode
[3] = BI_PHYMODE_NONE
;
740 /* 2 RGMII - 460EX */
741 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
742 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V(2);
743 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V(3);
744 rmiifer
|= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
746 bis
->bi_phymode
[0] = BI_PHYMODE_RGMII
;
747 bis
->bi_phymode
[1] = BI_PHYMODE_RGMII
;
748 bis
->bi_phymode
[2] = BI_PHYMODE_NONE
;
749 bis
->bi_phymode
[3] = BI_PHYMODE_NONE
;
752 /* 4 RGMII - 460GT */
753 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
754 /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
755 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V(2);
756 rmiifer
|= RGMII_FER_RGMII
<< RGMII_FER_V(3);
757 rmiifer1
|= RGMII_FER_RGMII
<< RGMII_FER_V(2);
758 rmiifer1
|= RGMII_FER_RGMII
<< RGMII_FER_V(3);
759 bis
->bi_phymode
[0] = BI_PHYMODE_RGMII
;
760 bis
->bi_phymode
[1] = BI_PHYMODE_RGMII
;
761 bis
->bi_phymode
[2] = BI_PHYMODE_RGMII
;
762 bis
->bi_phymode
[3] = BI_PHYMODE_RGMII
;
768 /* Set EMAC for MDIO */
769 mfsdr(SDR0_ETH_CFG
, eth_cfg
);
770 eth_cfg
|= SDR0_ETH_CFG_MDIO_SEL_EMAC0
;
771 mtsdr(SDR0_ETH_CFG
, eth_cfg
);
773 out_be32((void *)RGMII_FER
, rmiifer
);
774 #if defined(CONFIG_460GT)
775 out_be32((void *)RGMII_FER
+ RGMII1_BASE_OFFSET
, rmiifer1
);
778 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
779 mfsdr(SDR0_ETH_CFG
, eth_cfg
);
780 eth_cfg
|= (SDR0_ETH_CFG_TAHOE0_BYPASS
| SDR0_ETH_CFG_TAHOE1_BYPASS
);
781 mtsdr(SDR0_ETH_CFG
, eth_cfg
);
785 #endif /* CONFIG_460EX || CONFIG_460GT */
787 static inline void *malloc_aligned(u32 size
, u32 align
)
789 return (void *)(((u32
)malloc(size
+ align
) + align
- 1) &
793 static int ppc_4xx_eth_init (struct eth_device
*dev
, bd_t
* bis
)
796 unsigned long reg
= 0;
799 unsigned long duplex
;
800 unsigned long failsafe
;
802 unsigned short devnum
;
803 unsigned short reg_short
;
804 #if defined(CONFIG_440GX) || \
805 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
806 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
807 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
808 defined(CONFIG_405EX)
810 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
811 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
812 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
813 defined(CONFIG_405EX)
819 #ifdef CONFIG_4xx_DCACHE
820 static u32 last_used_ea
= 0;
822 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
823 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
824 defined(CONFIG_405EX)
828 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
830 /* before doing anything, figure out if we have a MAC address */
832 if (memcmp (dev
->enetaddr
, "\0\0\0\0\0\0", 6) == 0) {
833 printf("ERROR: ethaddr not set!\n");
837 #if defined(CONFIG_440GX) || \
838 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
839 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
840 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
841 defined(CONFIG_405EX)
842 /* Need to get the OPB frequency so we can access the PHY */
843 get_sys_info (&sysinfo
);
847 mtmsr (msr
& ~(MSR_EE
)); /* disable interrupts */
849 devnum
= hw_p
->devnum
;
854 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
855 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
856 * is possible that new packets (without relationship with
857 * current transfer) have got the time to arrived before
858 * netloop calls eth_halt
860 printf ("About preceeding transfer (eth%d):\n"
861 "- Sent packet number %d\n"
862 "- Received packet number %d\n"
863 "- Handled packet number %d\n",
866 hw_p
->stats
.pkts_rx
, hw_p
->stats
.pkts_handled
);
868 hw_p
->stats
.pkts_tx
= 0;
869 hw_p
->stats
.pkts_rx
= 0;
870 hw_p
->stats
.pkts_handled
= 0;
871 hw_p
->print_speed
= 1; /* print speed message again next time */
874 hw_p
->tx_err_index
= 0; /* Transmit Error Index for tx_err_log */
875 hw_p
->rx_err_index
= 0; /* Receive Error Index for rx_err_log */
877 hw_p
->rx_slot
= 0; /* MAL Receive Slot */
878 hw_p
->rx_i_index
= 0; /* Receive Interrupt Queue Index */
879 hw_p
->rx_u_index
= 0; /* Receive User Queue Index */
881 hw_p
->tx_slot
= 0; /* MAL Transmit Slot */
882 hw_p
->tx_i_index
= 0; /* Transmit Interrupt Queue Index */
883 hw_p
->tx_u_index
= 0; /* Transmit User Queue Index */
885 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
887 /* NOTE: 440GX spec states that mode is mutually exclusive */
888 /* NOTE: Therefore, disable all other EMACS, since we handle */
889 /* NOTE: only one emac at a time */
891 out_be32((void *)ZMII_FER
, 0);
894 #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
895 out_be32((void *)ZMII_FER
, (ZMII_FER_RMII
| ZMII_FER_MDI
) << ZMII_FER_V (devnum
));
896 #elif defined(CONFIG_440GX) || \
897 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
898 defined(CONFIG_460EX) || defined(CONFIG_460GT)
899 ethgroup
= ppc_4xx_eth_setup_bridge(devnum
, bis
);
902 out_be32((void *)ZMII_SSR
, ZMII_SSR_SP
<< ZMII_SSR_V(devnum
));
903 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
904 #if defined(CONFIG_405EX)
905 ethgroup
= ppc_4xx_eth_setup_bridge(devnum
, bis
);
910 /* provide clocks for EMAC internal loopback */
911 emac_loopback_enable(hw_p
);
914 out_be32((void *)EMAC_M0
+ hw_p
->hw_addr
, EMAC_M0_SRST
);
916 /* remove clocks for EMAC internal loopback */
917 emac_loopback_disable(hw_p
);
920 while ((in_be32((void *)EMAC_M0
+ hw_p
->hw_addr
) & (EMAC_M0_SRST
)) && failsafe
) {
925 printf("\nProblem resetting EMAC!\n");
927 #if defined(CONFIG_440GX) || \
928 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
929 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
930 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
931 defined(CONFIG_405EX)
932 /* Whack the M1 register */
934 mode_reg
&= ~0x00000038;
935 if (sysinfo
.freqOPB
<= 50000000);
936 else if (sysinfo
.freqOPB
<= 66666667)
937 mode_reg
|= EMAC_M1_OBCI_66
;
938 else if (sysinfo
.freqOPB
<= 83333333)
939 mode_reg
|= EMAC_M1_OBCI_83
;
940 else if (sysinfo
.freqOPB
<= 100000000)
941 mode_reg
|= EMAC_M1_OBCI_100
;
943 mode_reg
|= EMAC_M1_OBCI_GT100
;
945 out_be32((void *)EMAC_M1
+ hw_p
->hw_addr
, mode_reg
);
946 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
948 /* wait for PHY to complete auto negotiation */
950 #ifndef CONFIG_CS8952_PHY
953 reg
= CONFIG_PHY_ADDR
;
955 #if defined (CONFIG_PHY1_ADDR)
957 reg
= CONFIG_PHY1_ADDR
;
960 #if defined (CONFIG_PHY2_ADDR)
962 reg
= CONFIG_PHY2_ADDR
;
965 #if defined (CONFIG_PHY3_ADDR)
967 reg
= CONFIG_PHY3_ADDR
;
971 reg
= CONFIG_PHY_ADDR
;
975 bis
->bi_phynum
[devnum
] = reg
;
977 #if defined(CONFIG_PHY_RESET)
979 * Reset the phy, only if its the first time through
980 * otherwise, just check the speeds & feeds
982 if (hw_p
->first_init
== 0) {
983 #if defined(CONFIG_M88E1111_PHY)
984 miiphy_write (dev
->name
, reg
, 0x14, 0x0ce3);
985 miiphy_write (dev
->name
, reg
, 0x18, 0x4101);
986 miiphy_write (dev
->name
, reg
, 0x09, 0x0e00);
987 miiphy_write (dev
->name
, reg
, 0x04, 0x01e1);
989 miiphy_reset (dev
->name
, reg
);
991 #if defined(CONFIG_440GX) || \
992 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
993 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
994 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
995 defined(CONFIG_405EX)
997 #if defined(CONFIG_CIS8201_PHY)
999 * Cicada 8201 PHY needs to have an extended register whacked
1002 if (((devnum
== 2) || (devnum
== 3)) && (4 == ethgroup
)) {
1003 #if defined(CONFIG_CIS8201_SHORT_ETCH)
1004 miiphy_write (dev
->name
, reg
, 23, 0x1300);
1006 miiphy_write (dev
->name
, reg
, 23, 0x1000);
1009 * Vitesse VSC8201/Cicada CIS8201 errata:
1010 * Interoperability problem with Intel 82547EI phys
1011 * This work around (provided by Vitesse) changes
1012 * the default timer convergence from 8ms to 12ms
1014 miiphy_write (dev
->name
, reg
, 0x1f, 0x2a30);
1015 miiphy_write (dev
->name
, reg
, 0x08, 0x0200);
1016 miiphy_write (dev
->name
, reg
, 0x1f, 0x52b5);
1017 miiphy_write (dev
->name
, reg
, 0x02, 0x0004);
1018 miiphy_write (dev
->name
, reg
, 0x01, 0x0671);
1019 miiphy_write (dev
->name
, reg
, 0x00, 0x8fae);
1020 miiphy_write (dev
->name
, reg
, 0x1f, 0x2a30);
1021 miiphy_write (dev
->name
, reg
, 0x08, 0x0000);
1022 miiphy_write (dev
->name
, reg
, 0x1f, 0x0000);
1023 /* end Vitesse/Cicada errata */
1027 #if defined(CONFIG_ET1011C_PHY)
1029 * Agere ET1011c PHY needs to have an extended register whacked
1032 if (((devnum
== 2) || (devnum
==3)) && (4 == ethgroup
)) {
1033 miiphy_read (dev
->name
, reg
, 0x16, ®_short
);
1034 reg_short
&= ~(0x7);
1035 reg_short
|= 0x6; /* RGMII DLL Delay*/
1036 miiphy_write (dev
->name
, reg
, 0x16, reg_short
);
1038 miiphy_read (dev
->name
, reg
, 0x17, ®_short
);
1039 reg_short
&= ~(0x40);
1040 miiphy_write (dev
->name
, reg
, 0x17, reg_short
);
1042 miiphy_write(dev
->name
, reg
, 0x1c, 0x74f0);
1047 /* Start/Restart autonegotiation */
1048 phy_setup_aneg (dev
->name
, reg
);
1051 #endif /* defined(CONFIG_PHY_RESET) */
1053 miiphy_read (dev
->name
, reg
, PHY_BMSR
, ®_short
);
1056 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
1058 if ((reg_short
& PHY_BMSR_AUTN_ABLE
)
1059 && !(reg_short
& PHY_BMSR_AUTN_COMP
)) {
1060 puts ("Waiting for PHY auto negotiation to complete");
1062 while (!(reg_short
& PHY_BMSR_AUTN_COMP
)) {
1066 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
1067 puts (" TIMEOUT !\n");
1071 if ((i
++ % 1000) == 0) {
1074 udelay (1000); /* 1 ms */
1075 miiphy_read (dev
->name
, reg
, PHY_BMSR
, ®_short
);
1079 udelay (500000); /* another 500 ms (results in faster booting) */
1081 #endif /* #ifndef CONFIG_CS8952_PHY */
1083 speed
= miiphy_speed (dev
->name
, reg
);
1084 duplex
= miiphy_duplex (dev
->name
, reg
);
1086 if (hw_p
->print_speed
) {
1087 hw_p
->print_speed
= 0;
1088 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
1089 (int) speed
, (duplex
== HALF
) ? "HALF" : "FULL",
1093 #if defined(CONFIG_440) && \
1094 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
1095 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1096 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
1097 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
1098 mfsdr(sdr_mfr
, reg
);
1100 reg
= (reg
& ~SDR0_MFR_ZMII_MODE_MASK
) | SDR0_MFR_ZMII_MODE_RMII_100M
;
1102 reg
= (reg
& ~SDR0_MFR_ZMII_MODE_MASK
) | SDR0_MFR_ZMII_MODE_RMII_10M
;
1104 mtsdr(sdr_mfr
, reg
);
1107 /* Set ZMII/RGMII speed according to the phy link speed */
1108 reg
= in_be32((void *)ZMII_SSR
);
1109 if ( (speed
== 100) || (speed
== 1000) )
1110 out_be32((void *)ZMII_SSR
, reg
| (ZMII_SSR_SP
<< ZMII_SSR_V (devnum
)));
1112 out_be32((void *)ZMII_SSR
, reg
& (~(ZMII_SSR_SP
<< ZMII_SSR_V (devnum
))));
1114 if ((devnum
== 2) || (devnum
== 3)) {
1116 reg
= (RGMII_SSR_SP_1000MBPS
<< RGMII_SSR_V (devnum
));
1117 else if (speed
== 100)
1118 reg
= (RGMII_SSR_SP_100MBPS
<< RGMII_SSR_V (devnum
));
1119 else if (speed
== 10)
1120 reg
= (RGMII_SSR_SP_10MBPS
<< RGMII_SSR_V (devnum
));
1122 printf("Error in RGMII Speed\n");
1125 out_be32((void *)RGMII_SSR
, reg
);
1127 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
1129 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1130 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1131 defined(CONFIG_405EX)
1133 rgmii_channel
= devnum
- 2;
1135 rgmii_channel
= devnum
;
1138 reg
= (RGMII_SSR_SP_1000MBPS
<< RGMII_SSR_V(rgmii_channel
));
1139 else if (speed
== 100)
1140 reg
= (RGMII_SSR_SP_100MBPS
<< RGMII_SSR_V(rgmii_channel
));
1141 else if (speed
== 10)
1142 reg
= (RGMII_SSR_SP_10MBPS
<< RGMII_SSR_V(rgmii_channel
));
1144 printf("Error in RGMII Speed\n");
1147 out_be32((void *)RGMII_SSR
, reg
);
1148 #if defined(CONFIG_460GT)
1149 if ((devnum
== 2) || (devnum
== 3))
1150 out_be32((void *)RGMII_SSR
+ RGMII1_BASE_OFFSET
, reg
);
1154 /* set the Mal configuration reg */
1155 #if defined(CONFIG_440GX) || \
1156 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1157 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1158 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1159 defined(CONFIG_405EX)
1160 mtdcr (malmcr
, MAL_CR_PLBB
| MAL_CR_OPBBL
| MAL_CR_LEA
|
1161 MAL_CR_PLBLT_DEFAULT
| MAL_CR_EOPIE
| 0x00330000);
1163 mtdcr (malmcr
, MAL_CR_PLBB
| MAL_CR_OPBBL
| MAL_CR_LEA
| MAL_CR_PLBLT_DEFAULT
);
1164 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
1165 if (get_pvr() == PVR_440GP_RB
) {
1166 mtdcr (malmcr
, mfdcr(malmcr
) & ~MAL_CR_PLBB
);
1171 * Malloc MAL buffer desciptors, make sure they are
1172 * aligned on cache line boundary size
1173 * (401/403/IOP480 = 16, 405 = 32)
1174 * and doesn't cross cache block boundaries.
1176 if (hw_p
->first_init
== 0) {
1177 debug("*** Allocating descriptor memory ***\n");
1179 bd_cached
= (u32
)malloc_aligned(MAL_ALLOC_SIZE
, 4096);
1181 printf("%s: Error allocating MAL descriptor buffers!\n", __func__
);
1185 #ifdef CONFIG_4xx_DCACHE
1186 flush_dcache_range(bd_cached
, bd_cached
+ MAL_ALLOC_SIZE
);
1188 #if defined(CFG_MEM_TOP_HIDE)
1189 bd_uncached
= bis
->bi_memsize
+ CFG_MEM_TOP_HIDE
;
1191 bd_uncached
= bis
->bi_memsize
;
1194 bd_uncached
= last_used_ea
+ MAL_ALLOC_SIZE
;
1196 last_used_ea
= bd_uncached
;
1197 program_tlb(bd_cached
, bd_uncached
, MAL_ALLOC_SIZE
,
1198 TLB_WORD2_I_ENABLE
);
1200 bd_uncached
= bd_cached
;
1202 hw_p
->tx_phys
= bd_cached
;
1203 hw_p
->rx_phys
= bd_cached
+ MAL_TX_DESC_SIZE
;
1204 hw_p
->tx
= (mal_desc_t
*)(bd_uncached
);
1205 hw_p
->rx
= (mal_desc_t
*)(bd_uncached
+ MAL_TX_DESC_SIZE
);
1206 debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p
->tx
, hw_p
->rx
);
1209 for (i
= 0; i
< NUM_TX_BUFF
; i
++) {
1210 hw_p
->tx
[i
].ctrl
= 0;
1211 hw_p
->tx
[i
].data_len
= 0;
1212 if (hw_p
->first_init
== 0)
1213 hw_p
->txbuf_ptr
= malloc_aligned(MAL_ALLOC_SIZE
,
1215 hw_p
->tx
[i
].data_ptr
= hw_p
->txbuf_ptr
;
1216 if ((NUM_TX_BUFF
- 1) == i
)
1217 hw_p
->tx
[i
].ctrl
|= MAL_TX_CTRL_WRAP
;
1218 hw_p
->tx_run
[i
] = -1;
1219 debug("TX_BUFF %d @ 0x%08lx\n", i
, (u32
)hw_p
->tx
[i
].data_ptr
);
1222 for (i
= 0; i
< NUM_RX_BUFF
; i
++) {
1223 hw_p
->rx
[i
].ctrl
= 0;
1224 hw_p
->rx
[i
].data_len
= 0;
1225 hw_p
->rx
[i
].data_ptr
= (char *)NetRxPackets
[i
];
1226 if ((NUM_RX_BUFF
- 1) == i
)
1227 hw_p
->rx
[i
].ctrl
|= MAL_RX_CTRL_WRAP
;
1228 hw_p
->rx
[i
].ctrl
|= MAL_RX_CTRL_EMPTY
| MAL_RX_CTRL_INTR
;
1229 hw_p
->rx_ready
[i
] = -1;
1230 debug("RX_BUFF %d @ 0x%08lx\n", i
, (u32
)hw_p
->rx
[i
].data_ptr
);
1235 reg
|= dev
->enetaddr
[0]; /* set high address */
1237 reg
|= dev
->enetaddr
[1];
1239 out_be32((void *)EMAC_IAH
+ hw_p
->hw_addr
, reg
);
1242 reg
|= dev
->enetaddr
[2]; /* set low address */
1244 reg
|= dev
->enetaddr
[3];
1246 reg
|= dev
->enetaddr
[4];
1248 reg
|= dev
->enetaddr
[5];
1250 out_be32((void *)EMAC_IAL
+ hw_p
->hw_addr
, reg
);
1254 /* setup MAL tx & rx channel pointers */
1255 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
1256 mtdcr (maltxctp2r
, hw_p
->tx_phys
);
1258 mtdcr (maltxctp1r
, hw_p
->tx_phys
);
1260 #if defined(CONFIG_440)
1261 mtdcr (maltxbattr
, 0x0);
1262 mtdcr (malrxbattr
, 0x0);
1265 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1266 mtdcr (malrxctp8r
, hw_p
->rx_phys
);
1267 /* set RX buffer size */
1268 mtdcr (malrcbs8
, ENET_MAX_MTU_ALIGNED
/ 16);
1270 mtdcr (malrxctp1r
, hw_p
->rx_phys
);
1271 /* set RX buffer size */
1272 mtdcr (malrcbs1
, ENET_MAX_MTU_ALIGNED
/ 16);
1275 #if defined (CONFIG_440GX)
1277 /* setup MAL tx & rx channel pointers */
1278 mtdcr (maltxbattr
, 0x0);
1279 mtdcr (malrxbattr
, 0x0);
1280 mtdcr (maltxctp2r
, hw_p
->tx_phys
);
1281 mtdcr (malrxctp2r
, hw_p
->rx_phys
);
1282 /* set RX buffer size */
1283 mtdcr (malrcbs2
, ENET_MAX_MTU_ALIGNED
/ 16);
1286 /* setup MAL tx & rx channel pointers */
1287 mtdcr (maltxbattr
, 0x0);
1288 mtdcr (maltxctp3r
, hw_p
->tx_phys
);
1289 mtdcr (malrxbattr
, 0x0);
1290 mtdcr (malrxctp3r
, hw_p
->rx_phys
);
1291 /* set RX buffer size */
1292 mtdcr (malrcbs3
, ENET_MAX_MTU_ALIGNED
/ 16);
1294 #endif /* CONFIG_440GX */
1295 #if defined (CONFIG_460GT)
1297 /* setup MAL tx & rx channel pointers */
1298 mtdcr (maltxbattr
, 0x0);
1299 mtdcr (malrxbattr
, 0x0);
1300 mtdcr (maltxctp2r
, hw_p
->tx_phys
);
1301 mtdcr (malrxctp16r
, hw_p
->rx_phys
);
1302 /* set RX buffer size */
1303 mtdcr (malrcbs16
, ENET_MAX_MTU_ALIGNED
/ 16);
1306 /* setup MAL tx & rx channel pointers */
1307 mtdcr (maltxbattr
, 0x0);
1308 mtdcr (malrxbattr
, 0x0);
1309 mtdcr (maltxctp3r
, hw_p
->tx_phys
);
1310 mtdcr (malrxctp24r
, hw_p
->rx_phys
);
1311 /* set RX buffer size */
1312 mtdcr (malrcbs24
, ENET_MAX_MTU_ALIGNED
/ 16);
1314 #endif /* CONFIG_460GT */
1317 /* setup MAL tx & rx channel pointers */
1318 #if defined(CONFIG_440)
1319 mtdcr (maltxbattr
, 0x0);
1320 mtdcr (malrxbattr
, 0x0);
1322 mtdcr (maltxctp0r
, hw_p
->tx_phys
);
1323 mtdcr (malrxctp0r
, hw_p
->rx_phys
);
1324 /* set RX buffer size */
1325 mtdcr (malrcbs0
, ENET_MAX_MTU_ALIGNED
/ 16);
1329 /* Enable MAL transmit and receive channels */
1330 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
1331 mtdcr (maltxcasr
, (MAL_TXRX_CASR
>> (hw_p
->devnum
*2)));
1333 mtdcr (maltxcasr
, (MAL_TXRX_CASR
>> hw_p
->devnum
));
1335 mtdcr (malrxcasr
, (MAL_TXRX_CASR
>> hw_p
->devnum
));
1337 /* set transmit enable & receive enable */
1338 out_be32((void *)EMAC_M0
+ hw_p
->hw_addr
, EMAC_M0_TXE
| EMAC_M0_RXE
);
1340 mode_reg
= in_be32((void *)EMAC_M1
+ hw_p
->hw_addr
);
1342 /* set rx-/tx-fifo size */
1343 mode_reg
= (mode_reg
& ~EMAC_MR1_FIFO_MASK
) | EMAC_MR1_FIFO_SIZE
;
1346 if (speed
== _1000BASET
) {
1347 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1348 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1351 mfsdr (sdr_pfc1
, pfc1
);
1352 pfc1
|= SDR0_PFC1_EM_1000
;
1353 mtsdr (sdr_pfc1
, pfc1
);
1355 mode_reg
= mode_reg
| EMAC_M1_MF_1000MBPS
| EMAC_M1_IST
;
1356 } else if (speed
== _100BASET
)
1357 mode_reg
= mode_reg
| EMAC_M1_MF_100MBPS
| EMAC_M1_IST
;
1359 mode_reg
= mode_reg
& ~0x00C00000; /* 10 MBPS */
1361 mode_reg
= mode_reg
| 0x80000000 | EMAC_M1_IST
;
1363 out_be32((void *)EMAC_M1
+ hw_p
->hw_addr
, mode_reg
);
1365 /* Enable broadcast and indvidual address */
1366 /* TBS: enabling runts as some misbehaved nics will send runts */
1367 out_be32((void *)EMAC_RXM
+ hw_p
->hw_addr
, EMAC_RMR_BAE
| EMAC_RMR_IAE
);
1369 /* we probably need to set the tx mode1 reg? maybe at tx time */
1371 /* set transmit request threshold register */
1372 out_be32((void *)EMAC_TRTR
+ hw_p
->hw_addr
, 0x18000000); /* 256 byte threshold */
1374 /* set receive low/high water mark register */
1375 #if defined(CONFIG_440)
1376 /* 440s has a 64 byte burst length */
1377 out_be32((void *)EMAC_RX_HI_LO_WMARK
+ hw_p
->hw_addr
, 0x80009000);
1379 /* 405s have a 16 byte burst length */
1380 out_be32((void *)EMAC_RX_HI_LO_WMARK
+ hw_p
->hw_addr
, 0x0f002000);
1381 #endif /* defined(CONFIG_440) */
1382 out_be32((void *)EMAC_TXM1
+ hw_p
->hw_addr
, 0xf8640000);
1384 /* Set fifo limit entry in tx mode 0 */
1385 out_be32((void *)EMAC_TXM0
+ hw_p
->hw_addr
, 0x00000003);
1387 out_be32((void *)EMAC_I_FRAME_GAP_REG
+ hw_p
->hw_addr
, 0x00000008);
1390 hw_p
->emac_ier
= EMAC_ISR_PTLE
| EMAC_ISR_BFCS
| EMAC_ISR_ORE
| EMAC_ISR_IRE
;
1391 if (speed
== _100BASET
)
1392 hw_p
->emac_ier
= hw_p
->emac_ier
| EMAC_ISR_SYE
;
1394 out_be32((void *)EMAC_ISR
+ hw_p
->hw_addr
, 0xffffffff); /* clear pending interrupts */
1395 out_be32((void *)EMAC_IER
+ hw_p
->hw_addr
, hw_p
->emac_ier
);
1397 if (hw_p
->first_init
== 0) {
1399 * Connect interrupt service routines
1401 irq_install_handler(ETH_IRQ_NUM(hw_p
->devnum
),
1402 (interrupt_handler_t
*) enetInt
, dev
);
1405 mtmsr (msr
); /* enable interrupts again */
1408 hw_p
->first_init
= 1;
1414 static int ppc_4xx_eth_send (struct eth_device
*dev
, volatile void *ptr
,
1417 struct enet_frame
*ef_ptr
;
1418 ulong time_start
, time_now
;
1419 unsigned long temp_txm0
;
1420 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
1422 ef_ptr
= (struct enet_frame
*) ptr
;
1424 /*-----------------------------------------------------------------------+
1425 * Copy in our address into the frame.
1426 *-----------------------------------------------------------------------*/
1427 (void) memcpy (ef_ptr
->source_addr
, dev
->enetaddr
, ENET_ADDR_LENGTH
);
1429 /*-----------------------------------------------------------------------+
1430 * If frame is too long or too short, modify length.
1431 *-----------------------------------------------------------------------*/
1432 /* TBS: where does the fragment go???? */
1433 if (len
> ENET_MAX_MTU
)
1436 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1437 memcpy ((void *) hw_p
->txbuf_ptr
, (const void *) ptr
, len
);
1438 flush_dcache_range((u32
)hw_p
->txbuf_ptr
, (u32
)hw_p
->txbuf_ptr
+ len
);
1440 /*-----------------------------------------------------------------------+
1441 * set TX Buffer busy, and send it
1442 *-----------------------------------------------------------------------*/
1443 hw_p
->tx
[hw_p
->tx_slot
].ctrl
= (MAL_TX_CTRL_LAST
|
1444 EMAC_TX_CTRL_GFCS
| EMAC_TX_CTRL_GP
) &
1445 ~(EMAC_TX_CTRL_ISA
| EMAC_TX_CTRL_RSA
);
1446 if ((NUM_TX_BUFF
- 1) == hw_p
->tx_slot
)
1447 hw_p
->tx
[hw_p
->tx_slot
].ctrl
|= MAL_TX_CTRL_WRAP
;
1449 hw_p
->tx
[hw_p
->tx_slot
].data_len
= (short) len
;
1450 hw_p
->tx
[hw_p
->tx_slot
].ctrl
|= MAL_TX_CTRL_READY
;
1454 out_be32((void *)EMAC_TXM0
+ hw_p
->hw_addr
,
1455 in_be32((void *)EMAC_TXM0
+ hw_p
->hw_addr
) | EMAC_TXM0_GNP0
);
1456 #ifdef INFO_4XX_ENET
1457 hw_p
->stats
.pkts_tx
++;
1460 /*-----------------------------------------------------------------------+
1461 * poll unitl the packet is sent and then make sure it is OK
1462 *-----------------------------------------------------------------------*/
1463 time_start
= get_timer (0);
1465 temp_txm0
= in_be32((void *)EMAC_TXM0
+ hw_p
->hw_addr
);
1466 /* loop until either TINT turns on or 3 seconds elapse */
1467 if ((temp_txm0
& EMAC_TXM0_GNP0
) != 0) {
1468 /* transmit is done, so now check for errors
1469 * If there is an error, an interrupt should
1470 * happen when we return
1472 time_now
= get_timer (0);
1473 if ((time_now
- time_start
) > 3000) {
1482 int enetInt (struct eth_device
*dev
)
1485 int rc
= -1; /* default to not us */
1493 EMAC_4XX_HW_PST hw_p
;
1496 * Because the mal is generic, we need to get the current
1499 #if defined(CONFIG_NET_MULTI)
1500 dev
= eth_get_dev();
1507 /* enter loop that stays in interrupt code until nothing to service */
1511 uic_mal
= mfdcr(UIC_BASE_MAL
+ UIC_MSR
);
1512 uic_mal_err
= mfdcr(UIC_BASE_MAL_ERR
+ UIC_MSR
);
1513 uic_emac
= mfdcr(UIC_BASE_EMAC
+ UIC_MSR
);
1514 uic_emac_b
= mfdcr(UIC_BASE_EMAC_B
+ UIC_MSR
);
1516 if (!(uic_mal
& (UIC_MAL_RXEOB
| UIC_MAL_TXEOB
))
1517 && !(uic_mal_err
& (UIC_MAL_SERR
| UIC_MAL_TXDE
| UIC_MAL_RXDE
))
1518 && !(uic_emac
& UIC_ETHx
) && !(uic_emac_b
& UIC_ETHxB
)) {
1523 /* get and clear controller status interrupts */
1524 /* look at MAL and EMAC error interrupts */
1525 if (uic_mal_err
& (UIC_MAL_SERR
| UIC_MAL_TXDE
| UIC_MAL_RXDE
)) {
1526 /* we have a MAL error interrupt */
1527 mal_isr
= mfdcr(malesr
);
1528 mal_err(dev
, mal_isr
, uic_mal_err
,
1529 MAL_UIC_DEF
, MAL_UIC_ERR
);
1531 /* clear MAL error interrupt status bits */
1532 mtdcr(UIC_BASE_MAL_ERR
+ UIC_SR
,
1533 UIC_MAL_SERR
| UIC_MAL_TXDE
| UIC_MAL_RXDE
);
1538 /* look for EMAC errors */
1539 if ((uic_emac
& UIC_ETHx
) || (uic_emac_b
& UIC_ETHxB
)) {
1540 emac_isr
= in_be32((void *)EMAC_ISR
+ hw_p
->hw_addr
);
1541 emac_err(dev
, emac_isr
);
1543 /* clear EMAC error interrupt status bits */
1544 mtdcr(UIC_BASE_EMAC
+ UIC_SR
, UIC_ETHx
);
1545 mtdcr(UIC_BASE_EMAC_B
+ UIC_SR
, UIC_ETHxB
);
1550 /* handle MAX TX EOB interrupt from a tx */
1551 if (uic_mal
& UIC_MAL_TXEOB
) {
1552 /* clear MAL interrupt status bits */
1553 mal_eob
= mfdcr(maltxeobisr
);
1554 mtdcr(maltxeobisr
, mal_eob
);
1555 mtdcr(UIC_BASE_MAL
+ UIC_SR
, UIC_MAL_TXEOB
);
1557 /* indicate that we serviced an interrupt */
1562 /* handle MAL RX EOB interupt from a receive */
1563 /* check for EOB on valid channels */
1564 if (uic_mal
& UIC_MAL_RXEOB
) {
1565 mal_eob
= mfdcr(malrxeobisr
);
1567 (0x80000000 >> (hw_p
->devnum
* MAL_RX_CHAN_MUL
))) {
1568 /* push packet to upper layer */
1569 enet_rcv(dev
, emac_isr
);
1571 /* clear MAL interrupt status bits */
1572 mtdcr(UIC_BASE_MAL
+ UIC_SR
, UIC_MAL_RXEOB
);
1574 /* indicate that we serviced an interrupt */
1584 /*-----------------------------------------------------------------------------+
1586 *-----------------------------------------------------------------------------*/
1587 static void mal_err (struct eth_device
*dev
, unsigned long isr
,
1588 unsigned long uic
, unsigned long maldef
,
1589 unsigned long mal_errr
)
1591 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
1593 mtdcr (malesr
, isr
); /* clear interrupt */
1595 /* clear DE interrupt */
1596 mtdcr (maltxdeir
, 0xC0000000);
1597 mtdcr (malrxdeir
, 0x80000000);
1599 #ifdef INFO_4XX_ENET
1600 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr
, uic
, maldef
, mal_errr
);
1603 eth_init (hw_p
->bis
); /* start again... */
1606 /*-----------------------------------------------------------------------------+
1607 * EMAC Error Routine
1608 *-----------------------------------------------------------------------------*/
1609 static void emac_err (struct eth_device
*dev
, unsigned long isr
)
1611 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
1613 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p
->devnum
, isr
);
1614 out_be32((void *)EMAC_ISR
+ hw_p
->hw_addr
, isr
);
1617 /*-----------------------------------------------------------------------------+
1618 * enet_rcv() handles the ethernet receive data
1619 *-----------------------------------------------------------------------------*/
1620 static void enet_rcv (struct eth_device
*dev
, unsigned long malisr
)
1622 struct enet_frame
*ef_ptr
;
1623 unsigned long data_len
;
1624 unsigned long rx_eob_isr
;
1625 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
1631 rx_eob_isr
= mfdcr (malrxeobisr
);
1632 if ((0x80000000 >> (hw_p
->devnum
* MAL_RX_CHAN_MUL
)) & rx_eob_isr
) {
1634 mtdcr (malrxeobisr
, rx_eob_isr
);
1637 while (1) { /* do all */
1640 if ((MAL_RX_CTRL_EMPTY
& hw_p
->rx
[i
].ctrl
)
1641 || (loop_count
>= NUM_RX_BUFF
))
1646 data_len
= (unsigned long) hw_p
->rx
[i
].data_len
& 0x0fff; /* Get len */
1648 if (data_len
> ENET_MAX_MTU
) /* Check len */
1651 if (EMAC_RX_ERRORS
& hw_p
->rx
[i
].ctrl
) { /* Check Errors */
1653 hw_p
->stats
.rx_err_log
[hw_p
->
1656 hw_p
->rx_err_index
++;
1657 if (hw_p
->rx_err_index
==
1659 hw_p
->rx_err_index
=
1662 } /* data_len < max mtu */
1664 if (!data_len
) { /* no data */
1665 hw_p
->rx
[i
].ctrl
|= MAL_RX_CTRL_EMPTY
; /* Free Recv Buffer */
1667 hw_p
->stats
.data_len_err
++; /* Error at Rx */
1672 /* Check if user has already eaten buffer */
1673 /* if not => ERROR */
1674 else if (hw_p
->rx_ready
[hw_p
->rx_i_index
] != -1) {
1675 if (hw_p
->is_receiving
)
1676 printf ("ERROR : Receive buffers are full!\n");
1679 hw_p
->stats
.rx_frames
++;
1680 hw_p
->stats
.rx
+= data_len
;
1681 ef_ptr
= (struct enet_frame
*) hw_p
->rx
[i
].
1683 #ifdef INFO_4XX_ENET
1684 hw_p
->stats
.pkts_rx
++;
1689 hw_p
->rx_ready
[hw_p
->rx_i_index
] = i
;
1691 if (NUM_RX_BUFF
== hw_p
->rx_i_index
)
1692 hw_p
->rx_i_index
= 0;
1695 if (NUM_RX_BUFF
== hw_p
->rx_slot
)
1699 * free receive buffer only when
1700 * buffer has been handled (eth_rx)
1701 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1705 } /* if EMACK_RXCHL */
1709 static int ppc_4xx_eth_rx (struct eth_device
*dev
)
1714 EMAC_4XX_HW_PST hw_p
= dev
->priv
;
1716 hw_p
->is_receiving
= 1; /* tell driver */
1720 * use ring buffer and
1721 * get index from rx buffer desciptor queue
1723 user_index
= hw_p
->rx_ready
[hw_p
->rx_u_index
];
1724 if (user_index
== -1) {
1726 break; /* nothing received - leave for() loop */
1730 mtmsr (msr
& ~(MSR_EE
));
1732 length
= hw_p
->rx
[user_index
].data_len
& 0x0fff;
1734 /* Pass the packet up to the protocol layers. */
1735 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1736 /* NetReceive(NetRxPackets[i], length); */
1737 invalidate_dcache_range((u32
)hw_p
->rx
[user_index
].data_ptr
,
1738 (u32
)hw_p
->rx
[user_index
].data_ptr
+
1740 NetReceive (NetRxPackets
[user_index
], length
- 4);
1741 /* Free Recv Buffer */
1742 hw_p
->rx
[user_index
].ctrl
|= MAL_RX_CTRL_EMPTY
;
1743 /* Free rx buffer descriptor queue */
1744 hw_p
->rx_ready
[hw_p
->rx_u_index
] = -1;
1746 if (NUM_RX_BUFF
== hw_p
->rx_u_index
)
1747 hw_p
->rx_u_index
= 0;
1749 #ifdef INFO_4XX_ENET
1750 hw_p
->stats
.pkts_handled
++;
1753 mtmsr (msr
); /* Enable IRQ's */
1756 hw_p
->is_receiving
= 0; /* tell driver */
1761 int ppc_4xx_eth_initialize (bd_t
* bis
)
1763 static int virgin
= 0;
1764 struct eth_device
*dev
;
1766 EMAC_4XX_HW_PST hw
= NULL
;
1767 u8 ethaddr
[4 + CONFIG_EMAC_NR_START
][6];
1771 #if defined(CONFIG_440GX)
1774 mfsdr (sdr_pfc1
, pfc1
);
1775 pfc1
&= ~(0x01e00000);
1777 mtsdr (sdr_pfc1
, pfc1
);
1780 /* first clear all mac-addresses */
1781 for (eth_num
= 0; eth_num
< LAST_EMAC_NUM
; eth_num
++)
1782 memcpy(ethaddr
[eth_num
], "\0\0\0\0\0\0", 6);
1784 for (eth_num
= 0; eth_num
< LAST_EMAC_NUM
; eth_num
++) {
1786 default: /* fall through */
1788 memcpy(ethaddr
[eth_num
+ CONFIG_EMAC_NR_START
],
1789 bis
->bi_enetaddr
, 6);
1790 hw_addr
[eth_num
] = 0x0;
1792 #ifdef CONFIG_HAS_ETH1
1794 memcpy(ethaddr
[eth_num
+ CONFIG_EMAC_NR_START
],
1795 bis
->bi_enet1addr
, 6);
1796 hw_addr
[eth_num
] = 0x100;
1799 #ifdef CONFIG_HAS_ETH2
1801 memcpy(ethaddr
[eth_num
+ CONFIG_EMAC_NR_START
],
1802 bis
->bi_enet2addr
, 6);
1803 #if defined(CONFIG_460GT)
1804 hw_addr
[eth_num
] = 0x300;
1806 hw_addr
[eth_num
] = 0x400;
1810 #ifdef CONFIG_HAS_ETH3
1812 memcpy(ethaddr
[eth_num
+ CONFIG_EMAC_NR_START
],
1813 bis
->bi_enet3addr
, 6);
1814 #if defined(CONFIG_460GT)
1815 hw_addr
[eth_num
] = 0x400;
1817 hw_addr
[eth_num
] = 0x600;
1824 /* set phy num and mode */
1825 bis
->bi_phynum
[0] = CONFIG_PHY_ADDR
;
1826 bis
->bi_phymode
[0] = 0;
1828 #if defined(CONFIG_PHY1_ADDR)
1829 bis
->bi_phynum
[1] = CONFIG_PHY1_ADDR
;
1830 bis
->bi_phymode
[1] = 0;
1832 #if defined(CONFIG_440GX)
1833 bis
->bi_phynum
[2] = CONFIG_PHY2_ADDR
;
1834 bis
->bi_phynum
[3] = CONFIG_PHY3_ADDR
;
1835 bis
->bi_phymode
[2] = 2;
1836 bis
->bi_phymode
[3] = 2;
1839 #if defined(CONFIG_440GX) || \
1840 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1841 defined(CONFIG_405EX)
1842 ppc_4xx_eth_setup_bridge(0, bis
);
1845 for (eth_num
= 0; eth_num
< LAST_EMAC_NUM
; eth_num
++) {
1847 * See if we can actually bring up the interface,
1848 * otherwise, skip it
1850 if (memcmp (ethaddr
[eth_num
], "\0\0\0\0\0\0", 6) == 0) {
1851 bis
->bi_phymode
[eth_num
] = BI_PHYMODE_NONE
;
1855 /* Allocate device structure */
1856 dev
= (struct eth_device
*) malloc (sizeof (*dev
));
1858 printf ("ppc_4xx_eth_initialize: "
1859 "Cannot allocate eth_device %d\n", eth_num
);
1862 memset(dev
, 0, sizeof(*dev
));
1864 /* Allocate our private use data */
1865 hw
= (EMAC_4XX_HW_PST
) malloc (sizeof (*hw
));
1867 printf ("ppc_4xx_eth_initialize: "
1868 "Cannot allocate private hw data for eth_device %d",
1873 memset(hw
, 0, sizeof(*hw
));
1875 hw
->hw_addr
= hw_addr
[eth_num
];
1876 memcpy (dev
->enetaddr
, ethaddr
[eth_num
], 6);
1877 hw
->devnum
= eth_num
;
1878 hw
->print_speed
= 1;
1880 sprintf (dev
->name
, "ppc_4xx_eth%d", eth_num
- CONFIG_EMAC_NR_START
);
1881 dev
->priv
= (void *) hw
;
1882 dev
->init
= ppc_4xx_eth_init
;
1883 dev
->halt
= ppc_4xx_eth_halt
;
1884 dev
->send
= ppc_4xx_eth_send
;
1885 dev
->recv
= ppc_4xx_eth_rx
;
1888 /* set the MAL IER ??? names may change with new spec ??? */
1889 #if defined(CONFIG_440SPE) || \
1890 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1891 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1892 defined(CONFIG_405EX)
1894 MAL_IER_PT
| MAL_IER_PRE
| MAL_IER_PWE
|
1895 MAL_IER_DE
| MAL_IER_OTE
| MAL_IER_OE
| MAL_IER_PE
;
1898 MAL_IER_DE
| MAL_IER_NE
| MAL_IER_TE
|
1899 MAL_IER_OPBE
| MAL_IER_PLBE
;
1901 mtdcr (malesr
, 0xffffffff); /* clear pending interrupts */
1902 mtdcr (maltxdeir
, 0xffffffff); /* clear pending interrupts */
1903 mtdcr (malrxdeir
, 0xffffffff); /* clear pending interrupts */
1904 mtdcr (malier
, mal_ier
);
1906 /* install MAL interrupt handler */
1907 irq_install_handler (VECNUM_MAL_SERR
,
1908 (interrupt_handler_t
*) enetInt
,
1910 irq_install_handler (VECNUM_MAL_TXEOB
,
1911 (interrupt_handler_t
*) enetInt
,
1913 irq_install_handler (VECNUM_MAL_RXEOB
,
1914 (interrupt_handler_t
*) enetInt
,
1916 irq_install_handler (VECNUM_MAL_TXDE
,
1917 (interrupt_handler_t
*) enetInt
,
1919 irq_install_handler (VECNUM_MAL_RXDE
,
1920 (interrupt_handler_t
*) enetInt
,
1925 #if defined(CONFIG_NET_MULTI)
1931 #if defined(CONFIG_NET_MULTI)
1932 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1933 miiphy_register (dev
->name
,
1934 emac4xx_miiphy_read
, emac4xx_miiphy_write
);
1937 } /* end for each supported device */
1942 #if !defined(CONFIG_NET_MULTI)
1943 void eth_halt (void) {
1945 ppc_4xx_eth_halt(emac0_dev
);
1951 int eth_init (bd_t
*bis
)
1953 ppc_4xx_eth_initialize(bis
);
1955 return ppc_4xx_eth_init(emac0_dev
, bis
);
1957 printf("ERROR: ethaddr not set!\n");
1962 int eth_send(volatile void *packet
, int length
)
1964 return (ppc_4xx_eth_send(emac0_dev
, packet
, length
));
1969 return (ppc_4xx_eth_rx(emac0_dev
));
1972 int emac4xx_miiphy_initialize (bd_t
* bis
)
1974 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1975 miiphy_register ("ppc_4xx_eth0",
1976 emac4xx_miiphy_read
, emac4xx_miiphy_write
);
1981 #endif /* !defined(CONFIG_NET_MULTI) */