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[people/ms/u-boot.git] / cpu / ppc4xx / 4xx_enet.c
1 /*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
22 *
23 * File Name: enetemac.c
24 *
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
26 *
27 * Author: Mark Wisner
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
74 * (2 EMACs) also
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
79
80 #include <config.h>
81 #include <common.h>
82 #include <net.h>
83 #include <asm/processor.h>
84 #include <asm/io.h>
85 #include <asm/cache.h>
86 #include <asm/mmu.h>
87 #include <commproc.h>
88 #include <ppc4xx.h>
89 #include <ppc4xx_enet.h>
90 #include <405_mal.h>
91 #include <miiphy.h>
92 #include <malloc.h>
93
94 /*
95 * Only compile for platform with AMCC EMAC ethernet controller and
96 * network support enabled.
97 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
98 */
99 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
100
101 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
102 #error "CONFIG_MII has to be defined!"
103 #endif
104
105 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
106 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
107 #endif
108
109 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
110 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
111
112 /* Ethernet Transmit and Receive Buffers */
113 /* AS.HARNOIS
114 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
115 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
116 */
117 #define ENET_MAX_MTU PKTSIZE
118 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
119
120 /*-----------------------------------------------------------------------------+
121 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
122 * Interrupt Controller).
123 *-----------------------------------------------------------------------------*/
124 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
125
126 #if defined(CONFIG_HAS_ETH3)
127 #if !defined(CONFIG_440GX)
128 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
129 UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
130 #else
131 /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
132 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
133 #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
134 #endif /* !defined(CONFIG_440GX) */
135 #elif defined(CONFIG_HAS_ETH2)
136 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
137 UIC_MASK(ETH_IRQ_NUM(2)))
138 #elif defined(CONFIG_HAS_ETH1)
139 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
140 #else
141 #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
142 #endif
143
144 /*
145 * Define a default version for UIC_ETHxB for non 440GX so that we can
146 * use common code for all 4xx variants
147 */
148 #if !defined(UIC_ETHxB)
149 #define UIC_ETHxB 0
150 #endif
151
152 #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
153 #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
154 #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
155 #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
156 #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
157
158 #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
159 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
160
161 /*
162 * We have 3 different interrupt types:
163 * - MAL interrupts indicating successful transfer
164 * - MAL error interrupts indicating MAL related errors
165 * - EMAC interrupts indicating EMAC related errors
166 *
167 * All those interrupts can be on different UIC's, but since
168 * now at least all interrupts from one type are on the same
169 * UIC. Only exception is 440GX where the EMAC interrupts are
170 * spread over two UIC's!
171 */
172 #if defined(CONFIG_440GX)
173 #define UIC_BASE_MAL UIC1_DCR_BASE
174 #define UIC_BASE_MAL_ERR UIC2_DCR_BASE
175 #define UIC_BASE_EMAC UIC2_DCR_BASE
176 #define UIC_BASE_EMAC_B UIC3_DCR_BASE
177 #else
178 #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
179 #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
180 #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
181 #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
182 #endif
183
184 #undef INFO_4XX_ENET
185
186 #define BI_PHYMODE_NONE 0
187 #define BI_PHYMODE_ZMII 1
188 #define BI_PHYMODE_RGMII 2
189 #define BI_PHYMODE_GMII 3
190 #define BI_PHYMODE_RTBI 4
191 #define BI_PHYMODE_TBI 5
192 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
193 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
194 defined(CONFIG_405EX)
195 #define BI_PHYMODE_SMII 6
196 #define BI_PHYMODE_MII 7
197 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
198 #define BI_PHYMODE_RMII 8
199 #endif
200 #endif
201
202 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
203 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
204 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
205 defined(CONFIG_405EX)
206 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
207 #endif
208
209 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
210 #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
211 #endif
212
213 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
214 #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
215 #else
216 #define MAL_RX_CHAN_MUL 1
217 #endif
218
219 /*-----------------------------------------------------------------------------+
220 * Global variables. TX and RX descriptors and buffers.
221 *-----------------------------------------------------------------------------*/
222 #if !defined(CONFIG_NET_MULTI)
223 struct eth_device *emac0_dev = NULL;
224 #endif
225
226 /*
227 * Get count of EMAC devices (doesn't have to be the max. possible number
228 * supported by the cpu)
229 *
230 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
231 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
232 * 405EX/405EXr eval board, using the same binary.
233 */
234 #if defined(CONFIG_BOARD_EMAC_COUNT)
235 #define LAST_EMAC_NUM board_emac_count()
236 #else /* CONFIG_BOARD_EMAC_COUNT */
237 #if defined(CONFIG_HAS_ETH3)
238 #define LAST_EMAC_NUM 4
239 #elif defined(CONFIG_HAS_ETH2)
240 #define LAST_EMAC_NUM 3
241 #elif defined(CONFIG_HAS_ETH1)
242 #define LAST_EMAC_NUM 2
243 #else
244 #define LAST_EMAC_NUM 1
245 #endif
246 #endif /* CONFIG_BOARD_EMAC_COUNT */
247
248 /* normal boards start with EMAC0 */
249 #if !defined(CONFIG_EMAC_NR_START)
250 #define CONFIG_EMAC_NR_START 0
251 #endif
252
253 #define MAL_RX_DESC_SIZE 2048
254 #define MAL_TX_DESC_SIZE 2048
255 #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
256
257 /*-----------------------------------------------------------------------------+
258 * Prototypes and externals.
259 *-----------------------------------------------------------------------------*/
260 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
261
262 int enetInt (struct eth_device *dev);
263 static void mal_err (struct eth_device *dev, unsigned long isr,
264 unsigned long uic, unsigned long maldef,
265 unsigned long mal_errr);
266 static void emac_err (struct eth_device *dev, unsigned long isr);
267
268 extern int phy_setup_aneg (char *devname, unsigned char addr);
269 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
270 unsigned char reg, unsigned short *value);
271 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
272 unsigned char reg, unsigned short value);
273
274 int board_emac_count(void);
275
276 static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
277 {
278 #if defined(CONFIG_440SPE) || \
279 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
280 defined(CONFIG_405EX)
281 u32 val;
282
283 mfsdr(sdr_mfr, val);
284 val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
285 mtsdr(sdr_mfr, val);
286 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
287 u32 val;
288
289 mfsdr(SDR0_ETH_CFG, val);
290 val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
291 mtsdr(SDR0_ETH_CFG, val);
292 #endif
293 }
294
295 static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
296 {
297 #if defined(CONFIG_440SPE) || \
298 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
299 defined(CONFIG_405EX)
300 u32 val;
301
302 mfsdr(sdr_mfr, val);
303 val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
304 mtsdr(sdr_mfr, val);
305 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
306 u32 val;
307
308 mfsdr(SDR0_ETH_CFG, val);
309 val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
310 mtsdr(SDR0_ETH_CFG, val);
311 #endif
312 }
313
314 /*-----------------------------------------------------------------------------+
315 | ppc_4xx_eth_halt
316 | Disable MAL channel, and EMACn
317 +-----------------------------------------------------------------------------*/
318 static void ppc_4xx_eth_halt (struct eth_device *dev)
319 {
320 EMAC_4XX_HW_PST hw_p = dev->priv;
321 u32 val = 10000;
322
323 out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
324
325 /* 1st reset MAL channel */
326 /* Note: writing a 0 to a channel has no effect */
327 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
328 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
329 #else
330 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
331 #endif
332 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
333
334 /* wait for reset */
335 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
336 udelay (1000); /* Delay 1 MS so as not to hammer the register */
337 val--;
338 if (val == 0)
339 break;
340 }
341
342 /* provide clocks for EMAC internal loopback */
343 emac_loopback_enable(hw_p);
344
345 /* EMAC RESET */
346 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
347
348 /* remove clocks for EMAC internal loopback */
349 emac_loopback_disable(hw_p);
350
351 #ifndef CONFIG_NETCONSOLE
352 hw_p->print_speed = 1; /* print speed message again next time */
353 #endif
354
355 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
356 /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
357 mfsdr(SDR0_ETH_CFG, val);
358 val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
359 mtsdr(SDR0_ETH_CFG, val);
360 #endif
361
362 return;
363 }
364
365 #if defined (CONFIG_440GX)
366 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
367 {
368 unsigned long pfc1;
369 unsigned long zmiifer;
370 unsigned long rmiifer;
371
372 mfsdr(sdr_pfc1, pfc1);
373 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
374
375 zmiifer = 0;
376 rmiifer = 0;
377
378 switch (pfc1) {
379 case 1:
380 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
381 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
382 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
383 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
384 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
385 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
386 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
387 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
388 break;
389 case 2:
390 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
391 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
392 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
393 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
394 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
395 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
396 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
397 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
398 break;
399 case 3:
400 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
401 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
402 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
403 bis->bi_phymode[1] = BI_PHYMODE_NONE;
404 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
405 bis->bi_phymode[3] = BI_PHYMODE_NONE;
406 break;
407 case 4:
408 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
409 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
410 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
411 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
412 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
413 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
414 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
415 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
416 break;
417 case 5:
418 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
419 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
420 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
421 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
422 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
423 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
424 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
425 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
426 break;
427 case 6:
428 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
429 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
430 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
431 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
432 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
433 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
434 break;
435 case 0:
436 default:
437 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
438 rmiifer = 0x0;
439 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
440 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
441 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
442 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
443 break;
444 }
445
446 /* Ensure we setup mdio for this devnum and ONLY this devnum */
447 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
448
449 out_be32((void *)ZMII_FER, zmiifer);
450 out_be32((void *)RGMII_FER, rmiifer);
451
452 return ((int)pfc1);
453 }
454 #endif /* CONFIG_440_GX */
455
456 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
457 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
458 {
459 unsigned long zmiifer=0x0;
460 unsigned long pfc1;
461
462 mfsdr(sdr_pfc1, pfc1);
463 pfc1 &= SDR0_PFC1_SELECT_MASK;
464
465 switch (pfc1) {
466 case SDR0_PFC1_SELECT_CONFIG_2:
467 /* 1 x GMII port */
468 out_be32((void *)ZMII_FER, 0x00);
469 out_be32((void *)RGMII_FER, 0x00000037);
470 bis->bi_phymode[0] = BI_PHYMODE_GMII;
471 bis->bi_phymode[1] = BI_PHYMODE_NONE;
472 break;
473 case SDR0_PFC1_SELECT_CONFIG_4:
474 /* 2 x RGMII ports */
475 out_be32((void *)ZMII_FER, 0x00);
476 out_be32((void *)RGMII_FER, 0x00000055);
477 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
478 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
479 break;
480 case SDR0_PFC1_SELECT_CONFIG_6:
481 /* 2 x SMII ports */
482 out_be32((void *)ZMII_FER,
483 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
484 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
485 out_be32((void *)RGMII_FER, 0x00000000);
486 bis->bi_phymode[0] = BI_PHYMODE_SMII;
487 bis->bi_phymode[1] = BI_PHYMODE_SMII;
488 break;
489 case SDR0_PFC1_SELECT_CONFIG_1_2:
490 /* only 1 x MII supported */
491 out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
492 out_be32((void *)RGMII_FER, 0x00000000);
493 bis->bi_phymode[0] = BI_PHYMODE_MII;
494 bis->bi_phymode[1] = BI_PHYMODE_NONE;
495 break;
496 default:
497 break;
498 }
499
500 /* Ensure we setup mdio for this devnum and ONLY this devnum */
501 zmiifer = in_be32((void *)ZMII_FER);
502 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
503 out_be32((void *)ZMII_FER, zmiifer);
504
505 return ((int)0x0);
506 }
507 #endif /* CONFIG_440EPX */
508
509 #if defined(CONFIG_405EX)
510 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
511 {
512 u32 rgmiifer = 0;
513
514 /*
515 * The 405EX(r)'s RGMII bridge can operate in one of several
516 * modes, only one of which (2 x RGMII) allows the
517 * simultaneous use of both EMACs on the 405EX.
518 */
519
520 switch (CONFIG_EMAC_PHY_MODE) {
521
522 case EMAC_PHY_MODE_NONE:
523 /* No ports */
524 rgmiifer |= RGMII_FER_DIS << 0;
525 rgmiifer |= RGMII_FER_DIS << 4;
526 out_be32((void *)RGMII_FER, rgmiifer);
527 bis->bi_phymode[0] = BI_PHYMODE_NONE;
528 bis->bi_phymode[1] = BI_PHYMODE_NONE;
529 break;
530 case EMAC_PHY_MODE_NONE_RGMII:
531 /* 1 x RGMII port on channel 0 */
532 rgmiifer |= RGMII_FER_RGMII << 0;
533 rgmiifer |= RGMII_FER_DIS << 4;
534 out_be32((void *)RGMII_FER, rgmiifer);
535 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
536 bis->bi_phymode[1] = BI_PHYMODE_NONE;
537 break;
538 case EMAC_PHY_MODE_RGMII_NONE:
539 /* 1 x RGMII port on channel 1 */
540 rgmiifer |= RGMII_FER_DIS << 0;
541 rgmiifer |= RGMII_FER_RGMII << 4;
542 out_be32((void *)RGMII_FER, rgmiifer);
543 bis->bi_phymode[0] = BI_PHYMODE_NONE;
544 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
545 break;
546 case EMAC_PHY_MODE_RGMII_RGMII:
547 /* 2 x RGMII ports */
548 rgmiifer |= RGMII_FER_RGMII << 0;
549 rgmiifer |= RGMII_FER_RGMII << 4;
550 out_be32((void *)RGMII_FER, rgmiifer);
551 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
552 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
553 break;
554 case EMAC_PHY_MODE_NONE_GMII:
555 /* 1 x GMII port on channel 0 */
556 rgmiifer |= RGMII_FER_GMII << 0;
557 rgmiifer |= RGMII_FER_DIS << 4;
558 out_be32((void *)RGMII_FER, rgmiifer);
559 bis->bi_phymode[0] = BI_PHYMODE_GMII;
560 bis->bi_phymode[1] = BI_PHYMODE_NONE;
561 break;
562 case EMAC_PHY_MODE_NONE_MII:
563 /* 1 x MII port on channel 0 */
564 rgmiifer |= RGMII_FER_MII << 0;
565 rgmiifer |= RGMII_FER_DIS << 4;
566 out_be32((void *)RGMII_FER, rgmiifer);
567 bis->bi_phymode[0] = BI_PHYMODE_MII;
568 bis->bi_phymode[1] = BI_PHYMODE_NONE;
569 break;
570 case EMAC_PHY_MODE_GMII_NONE:
571 /* 1 x GMII port on channel 1 */
572 rgmiifer |= RGMII_FER_DIS << 0;
573 rgmiifer |= RGMII_FER_GMII << 4;
574 out_be32((void *)RGMII_FER, rgmiifer);
575 bis->bi_phymode[0] = BI_PHYMODE_NONE;
576 bis->bi_phymode[1] = BI_PHYMODE_GMII;
577 break;
578 case EMAC_PHY_MODE_MII_NONE:
579 /* 1 x MII port on channel 1 */
580 rgmiifer |= RGMII_FER_DIS << 0;
581 rgmiifer |= RGMII_FER_MII << 4;
582 out_be32((void *)RGMII_FER, rgmiifer);
583 bis->bi_phymode[0] = BI_PHYMODE_NONE;
584 bis->bi_phymode[1] = BI_PHYMODE_MII;
585 break;
586 default:
587 break;
588 }
589
590 /* Ensure we setup mdio for this devnum and ONLY this devnum */
591 rgmiifer = in_be32((void *)RGMII_FER);
592 rgmiifer |= (1 << (19-devnum));
593 out_be32((void *)RGMII_FER, rgmiifer);
594
595 return ((int)0x0);
596 }
597 #endif /* CONFIG_405EX */
598
599 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
600 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
601 {
602 u32 eth_cfg;
603 u32 zmiifer; /* ZMII0_FER reg. */
604 u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
605 u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
606 int mode;
607
608 zmiifer = 0;
609 rmiifer = 0;
610 rmiifer1 = 0;
611
612 #if defined(CONFIG_460EX)
613 mode = 9;
614 #else
615 mode = 10;
616 #endif
617
618 /* TODO:
619 * NOTE: 460GT has 2 RGMII bridge cores:
620 * emac0 ------ RGMII0_BASE
621 * |
622 * emac1 -----+
623 *
624 * emac2 ------ RGMII1_BASE
625 * |
626 * emac3 -----+
627 *
628 * 460EX has 1 RGMII bridge core:
629 * and RGMII1_BASE is disabled
630 * emac0 ------ RGMII0_BASE
631 * |
632 * emac1 -----+
633 */
634
635 /*
636 * Right now only 2*RGMII is supported. Please extend when needed.
637 * sr - 2008-02-19
638 */
639 switch (mode) {
640 case 1:
641 /* 1 MII - 460EX */
642 /* GMC0 EMAC4_0, ZMII Bridge */
643 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
644 bis->bi_phymode[0] = BI_PHYMODE_MII;
645 bis->bi_phymode[1] = BI_PHYMODE_NONE;
646 bis->bi_phymode[2] = BI_PHYMODE_NONE;
647 bis->bi_phymode[3] = BI_PHYMODE_NONE;
648 break;
649 case 2:
650 /* 2 MII - 460GT */
651 /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
652 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
653 zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
654 bis->bi_phymode[0] = BI_PHYMODE_MII;
655 bis->bi_phymode[1] = BI_PHYMODE_NONE;
656 bis->bi_phymode[2] = BI_PHYMODE_MII;
657 bis->bi_phymode[3] = BI_PHYMODE_NONE;
658 break;
659 case 3:
660 /* 2 RMII - 460EX */
661 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
662 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
663 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
664 bis->bi_phymode[0] = BI_PHYMODE_RMII;
665 bis->bi_phymode[1] = BI_PHYMODE_RMII;
666 bis->bi_phymode[2] = BI_PHYMODE_NONE;
667 bis->bi_phymode[3] = BI_PHYMODE_NONE;
668 break;
669 case 4:
670 /* 4 RMII - 460GT */
671 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
672 /* ZMII Bridge */
673 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
674 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
675 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
676 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
677 bis->bi_phymode[0] = BI_PHYMODE_RMII;
678 bis->bi_phymode[1] = BI_PHYMODE_RMII;
679 bis->bi_phymode[2] = BI_PHYMODE_RMII;
680 bis->bi_phymode[3] = BI_PHYMODE_RMII;
681 break;
682 case 5:
683 /* 2 SMII - 460EX */
684 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
685 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
686 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
687 bis->bi_phymode[0] = BI_PHYMODE_SMII;
688 bis->bi_phymode[1] = BI_PHYMODE_SMII;
689 bis->bi_phymode[2] = BI_PHYMODE_NONE;
690 bis->bi_phymode[3] = BI_PHYMODE_NONE;
691 break;
692 case 6:
693 /* 4 SMII - 460GT */
694 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
695 /* ZMII Bridge */
696 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
697 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
698 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
699 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
700 bis->bi_phymode[0] = BI_PHYMODE_SMII;
701 bis->bi_phymode[1] = BI_PHYMODE_SMII;
702 bis->bi_phymode[2] = BI_PHYMODE_SMII;
703 bis->bi_phymode[3] = BI_PHYMODE_SMII;
704 break;
705 case 7:
706 /* This is the default mode that we want for board bringup - Maple */
707 /* 1 GMII - 460EX */
708 /* GMC0 EMAC4_0, RGMII Bridge 0 */
709 rmiifer |= RGMII_FER_MDIO(0);
710
711 if (devnum == 0) {
712 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
713 bis->bi_phymode[0] = BI_PHYMODE_GMII;
714 bis->bi_phymode[1] = BI_PHYMODE_NONE;
715 bis->bi_phymode[2] = BI_PHYMODE_NONE;
716 bis->bi_phymode[3] = BI_PHYMODE_NONE;
717 } else {
718 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
719 bis->bi_phymode[0] = BI_PHYMODE_NONE;
720 bis->bi_phymode[1] = BI_PHYMODE_GMII;
721 bis->bi_phymode[2] = BI_PHYMODE_NONE;
722 bis->bi_phymode[3] = BI_PHYMODE_NONE;
723 }
724 break;
725 case 8:
726 /* 2 GMII - 460GT */
727 /* GMC0 EMAC4_0, RGMII Bridge 0 */
728 /* GMC1 EMAC4_2, RGMII Bridge 1 */
729 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
730 rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
731 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
732 rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
733
734 bis->bi_phymode[0] = BI_PHYMODE_GMII;
735 bis->bi_phymode[1] = BI_PHYMODE_NONE;
736 bis->bi_phymode[2] = BI_PHYMODE_GMII;
737 bis->bi_phymode[3] = BI_PHYMODE_NONE;
738 break;
739 case 9:
740 /* 2 RGMII - 460EX */
741 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
742 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
743 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
744 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
745
746 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
747 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
748 bis->bi_phymode[2] = BI_PHYMODE_NONE;
749 bis->bi_phymode[3] = BI_PHYMODE_NONE;
750 break;
751 case 10:
752 /* 4 RGMII - 460GT */
753 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
754 /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
755 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
756 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
757 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
758 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
759 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
760 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
761 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
762 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
763 break;
764 default:
765 break;
766 }
767
768 /* Set EMAC for MDIO */
769 mfsdr(SDR0_ETH_CFG, eth_cfg);
770 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
771 mtsdr(SDR0_ETH_CFG, eth_cfg);
772
773 out_be32((void *)RGMII_FER, rmiifer);
774 #if defined(CONFIG_460GT)
775 out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
776 #endif
777
778 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
779 mfsdr(SDR0_ETH_CFG, eth_cfg);
780 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
781 mtsdr(SDR0_ETH_CFG, eth_cfg);
782
783 return 0;
784 }
785 #endif /* CONFIG_460EX || CONFIG_460GT */
786
787 static inline void *malloc_aligned(u32 size, u32 align)
788 {
789 return (void *)(((u32)malloc(size + align) + align - 1) &
790 ~(align - 1));
791 }
792
793 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
794 {
795 int i;
796 unsigned long reg = 0;
797 unsigned long msr;
798 unsigned long speed;
799 unsigned long duplex;
800 unsigned long failsafe;
801 unsigned mode_reg;
802 unsigned short devnum;
803 unsigned short reg_short;
804 #if defined(CONFIG_440GX) || \
805 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
806 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
807 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
808 defined(CONFIG_405EX)
809 sys_info_t sysinfo;
810 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
811 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
812 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
813 defined(CONFIG_405EX)
814 int ethgroup = -1;
815 #endif
816 #endif
817 u32 bd_cached;
818 u32 bd_uncached = 0;
819 #ifdef CONFIG_4xx_DCACHE
820 static u32 last_used_ea = 0;
821 #endif
822 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
823 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
824 defined(CONFIG_405EX)
825 int rgmii_channel;
826 #endif
827
828 EMAC_4XX_HW_PST hw_p = dev->priv;
829
830 /* before doing anything, figure out if we have a MAC address */
831 /* if not, bail */
832 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
833 printf("ERROR: ethaddr not set!\n");
834 return -1;
835 }
836
837 #if defined(CONFIG_440GX) || \
838 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
839 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
840 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
841 defined(CONFIG_405EX)
842 /* Need to get the OPB frequency so we can access the PHY */
843 get_sys_info (&sysinfo);
844 #endif
845
846 msr = mfmsr ();
847 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
848
849 devnum = hw_p->devnum;
850
851 #ifdef INFO_4XX_ENET
852 /* AS.HARNOIS
853 * We should have :
854 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
855 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
856 * is possible that new packets (without relationship with
857 * current transfer) have got the time to arrived before
858 * netloop calls eth_halt
859 */
860 printf ("About preceeding transfer (eth%d):\n"
861 "- Sent packet number %d\n"
862 "- Received packet number %d\n"
863 "- Handled packet number %d\n",
864 hw_p->devnum,
865 hw_p->stats.pkts_tx,
866 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
867
868 hw_p->stats.pkts_tx = 0;
869 hw_p->stats.pkts_rx = 0;
870 hw_p->stats.pkts_handled = 0;
871 hw_p->print_speed = 1; /* print speed message again next time */
872 #endif
873
874 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
875 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
876
877 hw_p->rx_slot = 0; /* MAL Receive Slot */
878 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
879 hw_p->rx_u_index = 0; /* Receive User Queue Index */
880
881 hw_p->tx_slot = 0; /* MAL Transmit Slot */
882 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
883 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
884
885 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
886 /* set RMII mode */
887 /* NOTE: 440GX spec states that mode is mutually exclusive */
888 /* NOTE: Therefore, disable all other EMACS, since we handle */
889 /* NOTE: only one emac at a time */
890 reg = 0;
891 out_be32((void *)ZMII_FER, 0);
892 udelay (100);
893
894 #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
895 out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
896 #elif defined(CONFIG_440GX) || \
897 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
898 defined(CONFIG_460EX) || defined(CONFIG_460GT)
899 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
900 #endif
901
902 out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
903 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
904 #if defined(CONFIG_405EX)
905 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
906 #endif
907
908 sync();
909
910 /* provide clocks for EMAC internal loopback */
911 emac_loopback_enable(hw_p);
912
913 /* EMAC RESET */
914 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
915
916 /* remove clocks for EMAC internal loopback */
917 emac_loopback_disable(hw_p);
918
919 failsafe = 1000;
920 while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
921 udelay (1000);
922 failsafe--;
923 }
924 if (failsafe <= 0)
925 printf("\nProblem resetting EMAC!\n");
926
927 #if defined(CONFIG_440GX) || \
928 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
929 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
930 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
931 defined(CONFIG_405EX)
932 /* Whack the M1 register */
933 mode_reg = 0x0;
934 mode_reg &= ~0x00000038;
935 if (sysinfo.freqOPB <= 50000000);
936 else if (sysinfo.freqOPB <= 66666667)
937 mode_reg |= EMAC_M1_OBCI_66;
938 else if (sysinfo.freqOPB <= 83333333)
939 mode_reg |= EMAC_M1_OBCI_83;
940 else if (sysinfo.freqOPB <= 100000000)
941 mode_reg |= EMAC_M1_OBCI_100;
942 else
943 mode_reg |= EMAC_M1_OBCI_GT100;
944
945 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
946 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
947
948 /* wait for PHY to complete auto negotiation */
949 reg_short = 0;
950 #ifndef CONFIG_CS8952_PHY
951 switch (devnum) {
952 case 0:
953 reg = CONFIG_PHY_ADDR;
954 break;
955 #if defined (CONFIG_PHY1_ADDR)
956 case 1:
957 reg = CONFIG_PHY1_ADDR;
958 break;
959 #endif
960 #if defined (CONFIG_PHY2_ADDR)
961 case 2:
962 reg = CONFIG_PHY2_ADDR;
963 break;
964 #endif
965 #if defined (CONFIG_PHY3_ADDR)
966 case 3:
967 reg = CONFIG_PHY3_ADDR;
968 break;
969 #endif
970 default:
971 reg = CONFIG_PHY_ADDR;
972 break;
973 }
974
975 bis->bi_phynum[devnum] = reg;
976
977 #if defined(CONFIG_PHY_RESET)
978 /*
979 * Reset the phy, only if its the first time through
980 * otherwise, just check the speeds & feeds
981 */
982 if (hw_p->first_init == 0) {
983 #if defined(CONFIG_M88E1111_PHY)
984 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
985 miiphy_write (dev->name, reg, 0x18, 0x4101);
986 miiphy_write (dev->name, reg, 0x09, 0x0e00);
987 miiphy_write (dev->name, reg, 0x04, 0x01e1);
988 #endif
989 miiphy_reset (dev->name, reg);
990
991 #if defined(CONFIG_440GX) || \
992 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
993 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
994 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
995 defined(CONFIG_405EX)
996
997 #if defined(CONFIG_CIS8201_PHY)
998 /*
999 * Cicada 8201 PHY needs to have an extended register whacked
1000 * for RGMII mode.
1001 */
1002 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
1003 #if defined(CONFIG_CIS8201_SHORT_ETCH)
1004 miiphy_write (dev->name, reg, 23, 0x1300);
1005 #else
1006 miiphy_write (dev->name, reg, 23, 0x1000);
1007 #endif
1008 /*
1009 * Vitesse VSC8201/Cicada CIS8201 errata:
1010 * Interoperability problem with Intel 82547EI phys
1011 * This work around (provided by Vitesse) changes
1012 * the default timer convergence from 8ms to 12ms
1013 */
1014 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1015 miiphy_write (dev->name, reg, 0x08, 0x0200);
1016 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
1017 miiphy_write (dev->name, reg, 0x02, 0x0004);
1018 miiphy_write (dev->name, reg, 0x01, 0x0671);
1019 miiphy_write (dev->name, reg, 0x00, 0x8fae);
1020 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1021 miiphy_write (dev->name, reg, 0x08, 0x0000);
1022 miiphy_write (dev->name, reg, 0x1f, 0x0000);
1023 /* end Vitesse/Cicada errata */
1024 }
1025 #endif
1026
1027 #if defined(CONFIG_ET1011C_PHY)
1028 /*
1029 * Agere ET1011c PHY needs to have an extended register whacked
1030 * for RGMII mode.
1031 */
1032 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
1033 miiphy_read (dev->name, reg, 0x16, &reg_short);
1034 reg_short &= ~(0x7);
1035 reg_short |= 0x6; /* RGMII DLL Delay*/
1036 miiphy_write (dev->name, reg, 0x16, reg_short);
1037
1038 miiphy_read (dev->name, reg, 0x17, &reg_short);
1039 reg_short &= ~(0x40);
1040 miiphy_write (dev->name, reg, 0x17, reg_short);
1041
1042 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
1043 }
1044 #endif
1045
1046 #endif
1047 /* Start/Restart autonegotiation */
1048 phy_setup_aneg (dev->name, reg);
1049 udelay (1000);
1050 }
1051 #endif /* defined(CONFIG_PHY_RESET) */
1052
1053 miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
1054
1055 /*
1056 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
1057 */
1058 if ((reg_short & PHY_BMSR_AUTN_ABLE)
1059 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
1060 puts ("Waiting for PHY auto negotiation to complete");
1061 i = 0;
1062 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
1063 /*
1064 * Timeout reached ?
1065 */
1066 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
1067 puts (" TIMEOUT !\n");
1068 break;
1069 }
1070
1071 if ((i++ % 1000) == 0) {
1072 putc ('.');
1073 }
1074 udelay (1000); /* 1 ms */
1075 miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
1076
1077 }
1078 puts (" done\n");
1079 udelay (500000); /* another 500 ms (results in faster booting) */
1080 }
1081 #endif /* #ifndef CONFIG_CS8952_PHY */
1082
1083 speed = miiphy_speed (dev->name, reg);
1084 duplex = miiphy_duplex (dev->name, reg);
1085
1086 if (hw_p->print_speed) {
1087 hw_p->print_speed = 0;
1088 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
1089 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
1090 hw_p->devnum);
1091 }
1092
1093 #if defined(CONFIG_440) && \
1094 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
1095 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1096 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
1097 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
1098 mfsdr(sdr_mfr, reg);
1099 if (speed == 100) {
1100 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
1101 } else {
1102 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1103 }
1104 mtsdr(sdr_mfr, reg);
1105 #endif
1106
1107 /* Set ZMII/RGMII speed according to the phy link speed */
1108 reg = in_be32((void *)ZMII_SSR);
1109 if ( (speed == 100) || (speed == 1000) )
1110 out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
1111 else
1112 out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
1113
1114 if ((devnum == 2) || (devnum == 3)) {
1115 if (speed == 1000)
1116 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
1117 else if (speed == 100)
1118 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
1119 else if (speed == 10)
1120 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
1121 else {
1122 printf("Error in RGMII Speed\n");
1123 return -1;
1124 }
1125 out_be32((void *)RGMII_SSR, reg);
1126 }
1127 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
1128
1129 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1130 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1131 defined(CONFIG_405EX)
1132 if (devnum >= 2)
1133 rgmii_channel = devnum - 2;
1134 else
1135 rgmii_channel = devnum;
1136
1137 if (speed == 1000)
1138 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
1139 else if (speed == 100)
1140 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
1141 else if (speed == 10)
1142 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
1143 else {
1144 printf("Error in RGMII Speed\n");
1145 return -1;
1146 }
1147 out_be32((void *)RGMII_SSR, reg);
1148 #if defined(CONFIG_460GT)
1149 if ((devnum == 2) || (devnum == 3))
1150 out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
1151 #endif
1152 #endif
1153
1154 /* set the Mal configuration reg */
1155 #if defined(CONFIG_440GX) || \
1156 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1157 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1158 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1159 defined(CONFIG_405EX)
1160 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
1161 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
1162 #else
1163 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
1164 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
1165 if (get_pvr() == PVR_440GP_RB) {
1166 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
1167 }
1168 #endif
1169
1170 /*
1171 * Malloc MAL buffer desciptors, make sure they are
1172 * aligned on cache line boundary size
1173 * (401/403/IOP480 = 16, 405 = 32)
1174 * and doesn't cross cache block boundaries.
1175 */
1176 if (hw_p->first_init == 0) {
1177 debug("*** Allocating descriptor memory ***\n");
1178
1179 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
1180 if (!bd_cached) {
1181 printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
1182 return -1;
1183 }
1184
1185 #ifdef CONFIG_4xx_DCACHE
1186 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
1187 if (!last_used_ea)
1188 #if defined(CFG_MEM_TOP_HIDE)
1189 bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE;
1190 #else
1191 bd_uncached = bis->bi_memsize;
1192 #endif
1193 else
1194 bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
1195
1196 last_used_ea = bd_uncached;
1197 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
1198 TLB_WORD2_I_ENABLE);
1199 #else
1200 bd_uncached = bd_cached;
1201 #endif
1202 hw_p->tx_phys = bd_cached;
1203 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
1204 hw_p->tx = (mal_desc_t *)(bd_uncached);
1205 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
1206 debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
1207 }
1208
1209 for (i = 0; i < NUM_TX_BUFF; i++) {
1210 hw_p->tx[i].ctrl = 0;
1211 hw_p->tx[i].data_len = 0;
1212 if (hw_p->first_init == 0)
1213 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
1214 L1_CACHE_BYTES);
1215 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
1216 if ((NUM_TX_BUFF - 1) == i)
1217 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
1218 hw_p->tx_run[i] = -1;
1219 debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
1220 }
1221
1222 for (i = 0; i < NUM_RX_BUFF; i++) {
1223 hw_p->rx[i].ctrl = 0;
1224 hw_p->rx[i].data_len = 0;
1225 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
1226 if ((NUM_RX_BUFF - 1) == i)
1227 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
1228 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
1229 hw_p->rx_ready[i] = -1;
1230 debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
1231 }
1232
1233 reg = 0x00000000;
1234
1235 reg |= dev->enetaddr[0]; /* set high address */
1236 reg = reg << 8;
1237 reg |= dev->enetaddr[1];
1238
1239 out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
1240
1241 reg = 0x00000000;
1242 reg |= dev->enetaddr[2]; /* set low address */
1243 reg = reg << 8;
1244 reg |= dev->enetaddr[3];
1245 reg = reg << 8;
1246 reg |= dev->enetaddr[4];
1247 reg = reg << 8;
1248 reg |= dev->enetaddr[5];
1249
1250 out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
1251
1252 switch (devnum) {
1253 case 1:
1254 /* setup MAL tx & rx channel pointers */
1255 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
1256 mtdcr (maltxctp2r, hw_p->tx_phys);
1257 #else
1258 mtdcr (maltxctp1r, hw_p->tx_phys);
1259 #endif
1260 #if defined(CONFIG_440)
1261 mtdcr (maltxbattr, 0x0);
1262 mtdcr (malrxbattr, 0x0);
1263 #endif
1264
1265 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1266 mtdcr (malrxctp8r, hw_p->rx_phys);
1267 /* set RX buffer size */
1268 mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
1269 #else
1270 mtdcr (malrxctp1r, hw_p->rx_phys);
1271 /* set RX buffer size */
1272 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
1273 #endif
1274 break;
1275 #if defined (CONFIG_440GX)
1276 case 2:
1277 /* setup MAL tx & rx channel pointers */
1278 mtdcr (maltxbattr, 0x0);
1279 mtdcr (malrxbattr, 0x0);
1280 mtdcr (maltxctp2r, hw_p->tx_phys);
1281 mtdcr (malrxctp2r, hw_p->rx_phys);
1282 /* set RX buffer size */
1283 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
1284 break;
1285 case 3:
1286 /* setup MAL tx & rx channel pointers */
1287 mtdcr (maltxbattr, 0x0);
1288 mtdcr (maltxctp3r, hw_p->tx_phys);
1289 mtdcr (malrxbattr, 0x0);
1290 mtdcr (malrxctp3r, hw_p->rx_phys);
1291 /* set RX buffer size */
1292 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
1293 break;
1294 #endif /* CONFIG_440GX */
1295 #if defined (CONFIG_460GT)
1296 case 2:
1297 /* setup MAL tx & rx channel pointers */
1298 mtdcr (maltxbattr, 0x0);
1299 mtdcr (malrxbattr, 0x0);
1300 mtdcr (maltxctp2r, hw_p->tx_phys);
1301 mtdcr (malrxctp16r, hw_p->rx_phys);
1302 /* set RX buffer size */
1303 mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
1304 break;
1305 case 3:
1306 /* setup MAL tx & rx channel pointers */
1307 mtdcr (maltxbattr, 0x0);
1308 mtdcr (malrxbattr, 0x0);
1309 mtdcr (maltxctp3r, hw_p->tx_phys);
1310 mtdcr (malrxctp24r, hw_p->rx_phys);
1311 /* set RX buffer size */
1312 mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
1313 break;
1314 #endif /* CONFIG_460GT */
1315 case 0:
1316 default:
1317 /* setup MAL tx & rx channel pointers */
1318 #if defined(CONFIG_440)
1319 mtdcr (maltxbattr, 0x0);
1320 mtdcr (malrxbattr, 0x0);
1321 #endif
1322 mtdcr (maltxctp0r, hw_p->tx_phys);
1323 mtdcr (malrxctp0r, hw_p->rx_phys);
1324 /* set RX buffer size */
1325 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
1326 break;
1327 }
1328
1329 /* Enable MAL transmit and receive channels */
1330 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
1331 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
1332 #else
1333 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
1334 #endif
1335 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
1336
1337 /* set transmit enable & receive enable */
1338 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
1339
1340 mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
1341
1342 /* set rx-/tx-fifo size */
1343 mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
1344
1345 /* set speed */
1346 if (speed == _1000BASET) {
1347 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1348 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1349 unsigned long pfc1;
1350
1351 mfsdr (sdr_pfc1, pfc1);
1352 pfc1 |= SDR0_PFC1_EM_1000;
1353 mtsdr (sdr_pfc1, pfc1);
1354 #endif
1355 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
1356 } else if (speed == _100BASET)
1357 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
1358 else
1359 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
1360 if (duplex == FULL)
1361 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
1362
1363 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
1364
1365 /* Enable broadcast and indvidual address */
1366 /* TBS: enabling runts as some misbehaved nics will send runts */
1367 out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
1368
1369 /* we probably need to set the tx mode1 reg? maybe at tx time */
1370
1371 /* set transmit request threshold register */
1372 out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
1373
1374 /* set receive low/high water mark register */
1375 #if defined(CONFIG_440)
1376 /* 440s has a 64 byte burst length */
1377 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
1378 #else
1379 /* 405s have a 16 byte burst length */
1380 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
1381 #endif /* defined(CONFIG_440) */
1382 out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
1383
1384 /* Set fifo limit entry in tx mode 0 */
1385 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
1386 /* Frame gap set */
1387 out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
1388
1389 /* Set EMAC IER */
1390 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1391 if (speed == _100BASET)
1392 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1393
1394 out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1395 out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
1396
1397 if (hw_p->first_init == 0) {
1398 /*
1399 * Connect interrupt service routines
1400 */
1401 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1402 (interrupt_handler_t *) enetInt, dev);
1403 }
1404
1405 mtmsr (msr); /* enable interrupts again */
1406
1407 hw_p->bis = bis;
1408 hw_p->first_init = 1;
1409
1410 return 0;
1411 }
1412
1413
1414 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
1415 int len)
1416 {
1417 struct enet_frame *ef_ptr;
1418 ulong time_start, time_now;
1419 unsigned long temp_txm0;
1420 EMAC_4XX_HW_PST hw_p = dev->priv;
1421
1422 ef_ptr = (struct enet_frame *) ptr;
1423
1424 /*-----------------------------------------------------------------------+
1425 * Copy in our address into the frame.
1426 *-----------------------------------------------------------------------*/
1427 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1428
1429 /*-----------------------------------------------------------------------+
1430 * If frame is too long or too short, modify length.
1431 *-----------------------------------------------------------------------*/
1432 /* TBS: where does the fragment go???? */
1433 if (len > ENET_MAX_MTU)
1434 len = ENET_MAX_MTU;
1435
1436 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1437 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
1438 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
1439
1440 /*-----------------------------------------------------------------------+
1441 * set TX Buffer busy, and send it
1442 *-----------------------------------------------------------------------*/
1443 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1444 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1445 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1446 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1447 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1448
1449 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1450 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1451
1452 sync();
1453
1454 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
1455 in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
1456 #ifdef INFO_4XX_ENET
1457 hw_p->stats.pkts_tx++;
1458 #endif
1459
1460 /*-----------------------------------------------------------------------+
1461 * poll unitl the packet is sent and then make sure it is OK
1462 *-----------------------------------------------------------------------*/
1463 time_start = get_timer (0);
1464 while (1) {
1465 temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
1466 /* loop until either TINT turns on or 3 seconds elapse */
1467 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1468 /* transmit is done, so now check for errors
1469 * If there is an error, an interrupt should
1470 * happen when we return
1471 */
1472 time_now = get_timer (0);
1473 if ((time_now - time_start) > 3000) {
1474 return (-1);
1475 }
1476 } else {
1477 return (len);
1478 }
1479 }
1480 }
1481
1482 int enetInt (struct eth_device *dev)
1483 {
1484 int serviced;
1485 int rc = -1; /* default to not us */
1486 u32 mal_isr;
1487 u32 emac_isr = 0;
1488 u32 mal_eob;
1489 u32 uic_mal;
1490 u32 uic_mal_err;
1491 u32 uic_emac;
1492 u32 uic_emac_b;
1493 EMAC_4XX_HW_PST hw_p;
1494
1495 /*
1496 * Because the mal is generic, we need to get the current
1497 * eth device
1498 */
1499 #if defined(CONFIG_NET_MULTI)
1500 dev = eth_get_dev();
1501 #else
1502 dev = emac0_dev;
1503 #endif
1504
1505 hw_p = dev->priv;
1506
1507 /* enter loop that stays in interrupt code until nothing to service */
1508 do {
1509 serviced = 0;
1510
1511 uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
1512 uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
1513 uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
1514 uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
1515
1516 if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
1517 && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
1518 && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
1519 /* not for us */
1520 return (rc);
1521 }
1522
1523 /* get and clear controller status interrupts */
1524 /* look at MAL and EMAC error interrupts */
1525 if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
1526 /* we have a MAL error interrupt */
1527 mal_isr = mfdcr(malesr);
1528 mal_err(dev, mal_isr, uic_mal_err,
1529 MAL_UIC_DEF, MAL_UIC_ERR);
1530
1531 /* clear MAL error interrupt status bits */
1532 mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
1533 UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
1534
1535 return -1;
1536 }
1537
1538 /* look for EMAC errors */
1539 if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
1540 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1541 emac_err(dev, emac_isr);
1542
1543 /* clear EMAC error interrupt status bits */
1544 mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
1545 mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
1546
1547 return -1;
1548 }
1549
1550 /* handle MAX TX EOB interrupt from a tx */
1551 if (uic_mal & UIC_MAL_TXEOB) {
1552 /* clear MAL interrupt status bits */
1553 mal_eob = mfdcr(maltxeobisr);
1554 mtdcr(maltxeobisr, mal_eob);
1555 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
1556
1557 /* indicate that we serviced an interrupt */
1558 serviced = 1;
1559 rc = 0;
1560 }
1561
1562 /* handle MAL RX EOB interupt from a receive */
1563 /* check for EOB on valid channels */
1564 if (uic_mal & UIC_MAL_RXEOB) {
1565 mal_eob = mfdcr(malrxeobisr);
1566 if (mal_eob &
1567 (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
1568 /* push packet to upper layer */
1569 enet_rcv(dev, emac_isr);
1570
1571 /* clear MAL interrupt status bits */
1572 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
1573
1574 /* indicate that we serviced an interrupt */
1575 serviced = 1;
1576 rc = 0;
1577 }
1578 }
1579 } while (serviced);
1580
1581 return (rc);
1582 }
1583
1584 /*-----------------------------------------------------------------------------+
1585 * MAL Error Routine
1586 *-----------------------------------------------------------------------------*/
1587 static void mal_err (struct eth_device *dev, unsigned long isr,
1588 unsigned long uic, unsigned long maldef,
1589 unsigned long mal_errr)
1590 {
1591 EMAC_4XX_HW_PST hw_p = dev->priv;
1592
1593 mtdcr (malesr, isr); /* clear interrupt */
1594
1595 /* clear DE interrupt */
1596 mtdcr (maltxdeir, 0xC0000000);
1597 mtdcr (malrxdeir, 0x80000000);
1598
1599 #ifdef INFO_4XX_ENET
1600 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1601 #endif
1602
1603 eth_init (hw_p->bis); /* start again... */
1604 }
1605
1606 /*-----------------------------------------------------------------------------+
1607 * EMAC Error Routine
1608 *-----------------------------------------------------------------------------*/
1609 static void emac_err (struct eth_device *dev, unsigned long isr)
1610 {
1611 EMAC_4XX_HW_PST hw_p = dev->priv;
1612
1613 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1614 out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
1615 }
1616
1617 /*-----------------------------------------------------------------------------+
1618 * enet_rcv() handles the ethernet receive data
1619 *-----------------------------------------------------------------------------*/
1620 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1621 {
1622 struct enet_frame *ef_ptr;
1623 unsigned long data_len;
1624 unsigned long rx_eob_isr;
1625 EMAC_4XX_HW_PST hw_p = dev->priv;
1626
1627 int handled = 0;
1628 int i;
1629 int loop_count = 0;
1630
1631 rx_eob_isr = mfdcr (malrxeobisr);
1632 if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
1633 /* clear EOB */
1634 mtdcr (malrxeobisr, rx_eob_isr);
1635
1636 /* EMAC RX done */
1637 while (1) { /* do all */
1638 i = hw_p->rx_slot;
1639
1640 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1641 || (loop_count >= NUM_RX_BUFF))
1642 break;
1643
1644 loop_count++;
1645 handled++;
1646 data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
1647 if (data_len) {
1648 if (data_len > ENET_MAX_MTU) /* Check len */
1649 data_len = 0;
1650 else {
1651 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1652 data_len = 0;
1653 hw_p->stats.rx_err_log[hw_p->
1654 rx_err_index]
1655 = hw_p->rx[i].ctrl;
1656 hw_p->rx_err_index++;
1657 if (hw_p->rx_err_index ==
1658 MAX_ERR_LOG)
1659 hw_p->rx_err_index =
1660 0;
1661 } /* emac_erros */
1662 } /* data_len < max mtu */
1663 } /* if data_len */
1664 if (!data_len) { /* no data */
1665 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1666
1667 hw_p->stats.data_len_err++; /* Error at Rx */
1668 }
1669
1670 /* !data_len */
1671 /* AS.HARNOIS */
1672 /* Check if user has already eaten buffer */
1673 /* if not => ERROR */
1674 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1675 if (hw_p->is_receiving)
1676 printf ("ERROR : Receive buffers are full!\n");
1677 break;
1678 } else {
1679 hw_p->stats.rx_frames++;
1680 hw_p->stats.rx += data_len;
1681 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1682 data_ptr;
1683 #ifdef INFO_4XX_ENET
1684 hw_p->stats.pkts_rx++;
1685 #endif
1686 /* AS.HARNOIS
1687 * use ring buffer
1688 */
1689 hw_p->rx_ready[hw_p->rx_i_index] = i;
1690 hw_p->rx_i_index++;
1691 if (NUM_RX_BUFF == hw_p->rx_i_index)
1692 hw_p->rx_i_index = 0;
1693
1694 hw_p->rx_slot++;
1695 if (NUM_RX_BUFF == hw_p->rx_slot)
1696 hw_p->rx_slot = 0;
1697
1698 /* AS.HARNOIS
1699 * free receive buffer only when
1700 * buffer has been handled (eth_rx)
1701 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1702 */
1703 } /* if data_len */
1704 } /* while */
1705 } /* if EMACK_RXCHL */
1706 }
1707
1708
1709 static int ppc_4xx_eth_rx (struct eth_device *dev)
1710 {
1711 int length;
1712 int user_index;
1713 unsigned long msr;
1714 EMAC_4XX_HW_PST hw_p = dev->priv;
1715
1716 hw_p->is_receiving = 1; /* tell driver */
1717
1718 for (;;) {
1719 /* AS.HARNOIS
1720 * use ring buffer and
1721 * get index from rx buffer desciptor queue
1722 */
1723 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1724 if (user_index == -1) {
1725 length = -1;
1726 break; /* nothing received - leave for() loop */
1727 }
1728
1729 msr = mfmsr ();
1730 mtmsr (msr & ~(MSR_EE));
1731
1732 length = hw_p->rx[user_index].data_len & 0x0fff;
1733
1734 /* Pass the packet up to the protocol layers. */
1735 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1736 /* NetReceive(NetRxPackets[i], length); */
1737 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1738 (u32)hw_p->rx[user_index].data_ptr +
1739 length - 4);
1740 NetReceive (NetRxPackets[user_index], length - 4);
1741 /* Free Recv Buffer */
1742 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1743 /* Free rx buffer descriptor queue */
1744 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1745 hw_p->rx_u_index++;
1746 if (NUM_RX_BUFF == hw_p->rx_u_index)
1747 hw_p->rx_u_index = 0;
1748
1749 #ifdef INFO_4XX_ENET
1750 hw_p->stats.pkts_handled++;
1751 #endif
1752
1753 mtmsr (msr); /* Enable IRQ's */
1754 }
1755
1756 hw_p->is_receiving = 0; /* tell driver */
1757
1758 return length;
1759 }
1760
1761 int ppc_4xx_eth_initialize (bd_t * bis)
1762 {
1763 static int virgin = 0;
1764 struct eth_device *dev;
1765 int eth_num = 0;
1766 EMAC_4XX_HW_PST hw = NULL;
1767 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1768 u32 hw_addr[4];
1769 u32 mal_ier;
1770
1771 #if defined(CONFIG_440GX)
1772 unsigned long pfc1;
1773
1774 mfsdr (sdr_pfc1, pfc1);
1775 pfc1 &= ~(0x01e00000);
1776 pfc1 |= 0x01200000;
1777 mtsdr (sdr_pfc1, pfc1);
1778 #endif
1779
1780 /* first clear all mac-addresses */
1781 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1782 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1783
1784 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1785 switch (eth_num) {
1786 default: /* fall through */
1787 case 0:
1788 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1789 bis->bi_enetaddr, 6);
1790 hw_addr[eth_num] = 0x0;
1791 break;
1792 #ifdef CONFIG_HAS_ETH1
1793 case 1:
1794 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1795 bis->bi_enet1addr, 6);
1796 hw_addr[eth_num] = 0x100;
1797 break;
1798 #endif
1799 #ifdef CONFIG_HAS_ETH2
1800 case 2:
1801 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1802 bis->bi_enet2addr, 6);
1803 #if defined(CONFIG_460GT)
1804 hw_addr[eth_num] = 0x300;
1805 #else
1806 hw_addr[eth_num] = 0x400;
1807 #endif
1808 break;
1809 #endif
1810 #ifdef CONFIG_HAS_ETH3
1811 case 3:
1812 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1813 bis->bi_enet3addr, 6);
1814 #if defined(CONFIG_460GT)
1815 hw_addr[eth_num] = 0x400;
1816 #else
1817 hw_addr[eth_num] = 0x600;
1818 #endif
1819 break;
1820 #endif
1821 }
1822 }
1823
1824 /* set phy num and mode */
1825 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1826 bis->bi_phymode[0] = 0;
1827
1828 #if defined(CONFIG_PHY1_ADDR)
1829 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1830 bis->bi_phymode[1] = 0;
1831 #endif
1832 #if defined(CONFIG_440GX)
1833 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1834 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1835 bis->bi_phymode[2] = 2;
1836 bis->bi_phymode[3] = 2;
1837 #endif
1838
1839 #if defined(CONFIG_440GX) || \
1840 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1841 defined(CONFIG_405EX)
1842 ppc_4xx_eth_setup_bridge(0, bis);
1843 #endif
1844
1845 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1846 /*
1847 * See if we can actually bring up the interface,
1848 * otherwise, skip it
1849 */
1850 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1851 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1852 continue;
1853 }
1854
1855 /* Allocate device structure */
1856 dev = (struct eth_device *) malloc (sizeof (*dev));
1857 if (dev == NULL) {
1858 printf ("ppc_4xx_eth_initialize: "
1859 "Cannot allocate eth_device %d\n", eth_num);
1860 return (-1);
1861 }
1862 memset(dev, 0, sizeof(*dev));
1863
1864 /* Allocate our private use data */
1865 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1866 if (hw == NULL) {
1867 printf ("ppc_4xx_eth_initialize: "
1868 "Cannot allocate private hw data for eth_device %d",
1869 eth_num);
1870 free (dev);
1871 return (-1);
1872 }
1873 memset(hw, 0, sizeof(*hw));
1874
1875 hw->hw_addr = hw_addr[eth_num];
1876 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
1877 hw->devnum = eth_num;
1878 hw->print_speed = 1;
1879
1880 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
1881 dev->priv = (void *) hw;
1882 dev->init = ppc_4xx_eth_init;
1883 dev->halt = ppc_4xx_eth_halt;
1884 dev->send = ppc_4xx_eth_send;
1885 dev->recv = ppc_4xx_eth_rx;
1886
1887 if (0 == virgin) {
1888 /* set the MAL IER ??? names may change with new spec ??? */
1889 #if defined(CONFIG_440SPE) || \
1890 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1891 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1892 defined(CONFIG_405EX)
1893 mal_ier =
1894 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1895 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1896 #else
1897 mal_ier =
1898 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1899 MAL_IER_OPBE | MAL_IER_PLBE;
1900 #endif
1901 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1902 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1903 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1904 mtdcr (malier, mal_ier);
1905
1906 /* install MAL interrupt handler */
1907 irq_install_handler (VECNUM_MAL_SERR,
1908 (interrupt_handler_t *) enetInt,
1909 dev);
1910 irq_install_handler (VECNUM_MAL_TXEOB,
1911 (interrupt_handler_t *) enetInt,
1912 dev);
1913 irq_install_handler (VECNUM_MAL_RXEOB,
1914 (interrupt_handler_t *) enetInt,
1915 dev);
1916 irq_install_handler (VECNUM_MAL_TXDE,
1917 (interrupt_handler_t *) enetInt,
1918 dev);
1919 irq_install_handler (VECNUM_MAL_RXDE,
1920 (interrupt_handler_t *) enetInt,
1921 dev);
1922 virgin = 1;
1923 }
1924
1925 #if defined(CONFIG_NET_MULTI)
1926 eth_register (dev);
1927 #else
1928 emac0_dev = dev;
1929 #endif
1930
1931 #if defined(CONFIG_NET_MULTI)
1932 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1933 miiphy_register (dev->name,
1934 emac4xx_miiphy_read, emac4xx_miiphy_write);
1935 #endif
1936 #endif
1937 } /* end for each supported device */
1938
1939 return 0;
1940 }
1941
1942 #if !defined(CONFIG_NET_MULTI)
1943 void eth_halt (void) {
1944 if (emac0_dev) {
1945 ppc_4xx_eth_halt(emac0_dev);
1946 free(emac0_dev);
1947 emac0_dev = NULL;
1948 }
1949 }
1950
1951 int eth_init (bd_t *bis)
1952 {
1953 ppc_4xx_eth_initialize(bis);
1954 if (emac0_dev) {
1955 return ppc_4xx_eth_init(emac0_dev, bis);
1956 } else {
1957 printf("ERROR: ethaddr not set!\n");
1958 return -1;
1959 }
1960 }
1961
1962 int eth_send(volatile void *packet, int length)
1963 {
1964 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1965 }
1966
1967 int eth_rx(void)
1968 {
1969 return (ppc_4xx_eth_rx(emac0_dev));
1970 }
1971
1972 int emac4xx_miiphy_initialize (bd_t * bis)
1973 {
1974 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1975 miiphy_register ("ppc_4xx_eth0",
1976 emac4xx_miiphy_read, emac4xx_miiphy_write);
1977 #endif
1978
1979 return 0;
1980 }
1981 #endif /* !defined(CONFIG_NET_MULTI) */
1982
1983 #endif
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