cpu/ppc4xx/4xx_pci.c

   1 /*-----------------------------------------------------------------------------+
   2  *
   3  *       This source code has been made available to you by IBM on an AS-IS
   4  *       basis.  Anyone receiving this source is licensed under IBM
   5  *       copyrights to use it in any way he or she deems fit, including
   6  *       copying it, modifying it, compiling it, and redistributing it either
   7  *       with or without modifications.  No license under IBM patents or
   8  *       patent applications is to be implied by the copyright license.
   9  *
  10  *       Any user of this software should understand that IBM cannot provide
  11  *       technical support for this software and will not be responsible for
  12  *       any consequences resulting from the use of this software.
  13  *
  14  *       Any person who transfers this source code or any derivative work
  15  *       must include the IBM copyright notice, this paragraph, and the
  16  *       preceding two paragraphs in the transferred software.
  17  *
  18  *       COPYRIGHT   I B M   CORPORATION 1995
  19  *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20  *-----------------------------------------------------------------------------*/
  21 /*----------------------------------------------------------------------------+
  22  *
  23  *  File Name:   405gp_pci.c
  24  *
  25  *  Function:    Initialization code for the 405GP PCI Configuration regs.
  26  *
  27  *  Author:      Mark Game
  28  *
  29  *  Change Activity-
  30  *
  31  *  Date        Description of Change                                       BY
  32  *  ---------   ---------------------                                       ---
  33  *  09-Sep-98   Created                                                     MCG
  34  *  02-Nov-98   Removed External arbiter selected message                   JWB
  35  *  27-Nov-98   Zero out PTMBAR2 and disable in PTM2MS                      JWB
  36  *  04-Jan-99   Zero out other unused PMM and PTM regs. Change bus scan     MCG
  37  *              from (0 to n) to (1 to n).
  38  *  17-May-99   Port to Walnut                                              JWB
  39  *  17-Jun-99   Updated for VGA support                                     JWB
  40  *  21-Jun-99   Updated to allow SRAM region to be a target from PCI bus    JWB
  41  *  19-Jul-99   Updated for 405GP pass 1 errata #26 (Low PCI subsequent     MCG
  42  *              target latency timer values are not supported).
  43  *              Should be fixed in pass 2.
  44  *  09-Sep-99   Removed use of PTM2 since the SRAM region no longer needs   JWB
  45  *              to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
  46  *  10-Dec-99   Updated PCI_Write_CFG_Reg for pass2 errata #6               JWB
  47  *  11-Jan-00   Ensure PMMxMAs disabled before setting PMMxLAs. This is not
  48  *              really required after a reset since PMMxMAs are already
  49  *              disabled but is a good practice nonetheless.                JWB
  50  *  12-Jun-01   stefan.roese@esd-electronics.com
  51  *              - PCI host/adapter handling reworked
  52  *  09-Jul-01   stefan.roese@esd-electronics.com
  53  *              - PCI host now configures from device 0 (not 1) to max_dev,
  54  *                (host configures itself)
  55  *              - On CPCI-405 pci base address and size is generated from
  56  *                SDRAM and FLASH size (CFG regs not used anymore)
  57  *              - Some minor changes for CPCI-405-A (adapter version)
  58  *  14-Sep-01   stefan.roese@esd-electronics.com
  59  *              - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
  60  *  28-Sep-01   stefan.roese@esd-electronics.com
  61  *              - Changed pci master configuration for linux compatibility
  62  *                (no need for bios_fixup() anymore)
  63  *  26-Feb-02   stefan.roese@esd-electronics.com
  64  *              - Bug fixed in pci configuration (Andrew May)
  65  *              - Removed pci class code init for CPCI405 board
  66  *  15-May-02   stefan.roese@esd-electronics.com
  67  *              - New vga device handling
  68  *  29-May-02   stefan.roese@esd-electronics.com
  69  *              - PCI class code init added (if defined)
  70  *----------------------------------------------------------------------------*/
  71
  72 #include <common.h>
  73 #include <command.h>
  74 #if !defined(CONFIG_440)
  75 #include <asm/4xx_pci.h>
  76 #endif
  77 #include <asm/processor.h>
  78 #include <pci.h>
  79
  80 #ifdef CONFIG_PCI
  81
  82 DECLARE_GLOBAL_DATA_PTR;
  83
  84 /*
  85  * Board-specific pci initialization
  86  * Platform code can reimplement pci_pre_init() if needed
  87  */
  88 int __pci_pre_init(struct pci_controller *hose)
  89 {
  90         return 1;
  91 }
  92 int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
  93
  94 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
  95
  96 #if defined(CONFIG_PMC405)
  97 ushort pmc405_pci_subsys_deviceid(void);
  98 #endif
  99
 100 /*#define DEBUG*/
 101
 102 /*-----------------------------------------------------------------------------+
 103  * pci_init.  Initializes the 405GP PCI Configuration regs.
 104  *-----------------------------------------------------------------------------*/
 105 void pci_405gp_init(struct pci_controller *hose)
 106 {
 107         int i, reg_num = 0;
 108         bd_t *bd = gd->bd;
 109
 110         unsigned short temp_short;
 111         unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
 112 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
 113         char *ptmla_str, *ptmms_str;
 114 #endif
 115         unsigned long ptmla[2]    = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
 116         unsigned long ptmms[2]    = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
 117 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
 118         unsigned long pmmla[3]    = {0x80000000, 0xA0000000, 0};
 119         unsigned long pmmma[3]    = {0xE0000001, 0xE0000001, 0};
 120         unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
 121         unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
 122 #else
 123         unsigned long pmmla[3]    = {0x80000000, 0,0};
 124         unsigned long pmmma[3]    = {0xC0000001, 0,0};
 125         unsigned long pmmpcila[3] = {0x80000000, 0,0};
 126         unsigned long pmmpciha[3] = {0x00000000, 0,0};
 127 #endif
 128 #ifdef CONFIG_PCI_PNP
 129 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
 130         char *s;
 131 #endif
 132 #endif
 133
 134 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
 135         ptmla_str = getenv("ptm1la");
 136         ptmms_str = getenv("ptm1ms");
 137         if(NULL != ptmla_str && NULL != ptmms_str ) {
 138                 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
 139                 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
 140         }
 141
 142         ptmla_str = getenv("ptm2la");
 143         ptmms_str = getenv("ptm2ms");
 144         if(NULL != ptmla_str && NULL != ptmms_str ) {
 145                 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
 146                 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
 147         }
 148 #endif
 149
 150         /*
 151          * Register the hose
 152          */
 153         hose->first_busno = 0;
 154         hose->last_busno = 0xff;
 155
 156         /* ISA/PCI I/O space */
 157         pci_set_region(hose->regions + reg_num++,
 158                        MIN_PCI_PCI_IOADDR,
 159                        MIN_PLB_PCI_IOADDR,
 160                        0x10000,
 161                        PCI_REGION_IO);
 162
 163         /* PCI I/O space */
 164         pci_set_region(hose->regions + reg_num++,
 165                        0x00800000,
 166                        0xe8800000,
 167                        0x03800000,
 168                        PCI_REGION_IO);
 169
 170         reg_num = 2;
 171
 172         /* Memory spaces */
 173         for (i=0; i<2; i++)
 174                 if (ptmms[i] & 1)
 175                 {
 176                         if (!i) hose->pci_fb = hose->regions + reg_num;
 177
 178                         pci_set_region(hose->regions + reg_num++,
 179                                        ptmpcila[i], ptmla[i],
 180                                        ~(ptmms[i] & 0xfffff000) + 1,
 181                                        PCI_REGION_MEM |
 182                                        PCI_REGION_MEMORY);
 183                 }
 184
 185         /* PCI memory spaces */
 186         for (i=0; i<3; i++)
 187                 if (pmmma[i] & 1)
 188                 {
 189                         pci_set_region(hose->regions + reg_num++,
 190                                        pmmpcila[i], pmmla[i],
 191                                        ~(pmmma[i] & 0xfffff000) + 1,
 192                                        PCI_REGION_MEM);
 193                 }
 194
 195         hose->region_count = reg_num;
 196
 197         pci_setup_indirect(hose,
 198                            PCICFGADR,
 199                            PCICFGDATA);
 200
 201         if (hose->pci_fb)
 202                 pciauto_region_init(hose->pci_fb);
 203
 204         /* Let board change/modify hose & do initial checks */
 205         if (pci_pre_init (hose) == 0) {
 206                 printf("PCI: Board-specific initialization failed.\n");
 207                 printf("PCI: Configuration aborted.\n");
 208                 return;
 209         }
 210
 211         pci_register_hose(hose);
 212
 213         /*--------------------------------------------------------------------------+
 214          * 405GP PCI Master configuration.
 215          * Map one 512 MB range of PLB/processor addresses to PCI memory space.
 216          * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
 217          * Use byte reversed out routines to handle endianess.
 218          *--------------------------------------------------------------------------*/
 219         out32r(PMM0MA,    (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
 220         out32r(PMM0LA,    pmmla[0]);
 221         out32r(PMM0PCILA, pmmpcila[0]);
 222         out32r(PMM0PCIHA, pmmpciha[0]);
 223         out32r(PMM0MA,    pmmma[0]);
 224
 225         /*--------------------------------------------------------------------------+
 226          * PMM1 is not used.  Initialize them to zero.
 227          *--------------------------------------------------------------------------*/
 228         out32r(PMM1MA,    (pmmma[1]&~0x1));
 229         out32r(PMM1LA,    pmmla[1]);
 230         out32r(PMM1PCILA, pmmpcila[1]);
 231         out32r(PMM1PCIHA, pmmpciha[1]);
 232         out32r(PMM1MA,    pmmma[1]);
 233
 234         /*--------------------------------------------------------------------------+
 235          * PMM2 is not used.  Initialize them to zero.
 236          *--------------------------------------------------------------------------*/
 237         out32r(PMM2MA,    (pmmma[2]&~0x1));
 238         out32r(PMM2LA,    pmmla[2]);
 239         out32r(PMM2PCILA, pmmpcila[2]);
 240         out32r(PMM2PCIHA, pmmpciha[2]);
 241         out32r(PMM2MA,    pmmma[2]);
 242
 243         /*--------------------------------------------------------------------------+
 244          * 405GP PCI Target configuration.  (PTM1)
 245          * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
 246          *--------------------------------------------------------------------------*/
 247         out32r(PTM1LA,    ptmla[0]);         /* insert address                     */
 248         out32r(PTM1MS,    ptmms[0]);         /* insert size, enable bit is 1       */
 249         pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
 250
 251         /*--------------------------------------------------------------------------+
 252          * 405GP PCI Target configuration.  (PTM2)
 253          *--------------------------------------------------------------------------*/
 254         out32r(PTM2LA, ptmla[1]);            /* insert address                     */
 255         pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
 256
 257         if (ptmms[1] == 0)
 258         {
 259                 out32r(PTM2MS,    0x00000001);   /* set enable bit                     */
 260                 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
 261                 out32r(PTM2MS,    0x00000000);   /* disable                            */
 262         }
 263         else
 264         {
 265                 out32r(PTM2MS, ptmms[1]);        /* insert size, enable bit is 1       */
 266         }
 267
 268         /*
 269          * Insert Subsystem Vendor and Device ID
 270          */
 271         pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
 272 #ifdef CONFIG_CPCI405
 273         if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
 274                 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
 275         else
 276                 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
 277 #else
 278         pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
 279 #endif
 280
 281         /*
 282          * Insert Class-code
 283          */
 284 #ifdef CFG_PCI_CLASSCODE
 285         pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
 286 #endif /* CFG_PCI_CLASSCODE */
 287
 288         /*--------------------------------------------------------------------------+
 289          * If PCI speed = 66Mhz, set 66Mhz capable bit.
 290          *--------------------------------------------------------------------------*/
 291         if (bd->bi_pci_busfreq >= 66000000) {
 292                 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
 293                 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
 294         }
 295
 296 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
 297 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
 298         if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
 299             (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
 300 #endif
 301         {
 302                 /*--------------------------------------------------------------------------+
 303                  * Write the 405GP PCI Configuration regs.
 304                  * Enable 405GP to be a master on the PCI bus (PMM).
 305                  * Enable 405GP to act as a PCI memory target (PTM).
 306                  *--------------------------------------------------------------------------*/
 307                 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
 308                 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
 309                                       PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 310         }
 311 #endif
 312
 313 #if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
 314         pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
 315 #endif
 316
 317         /*
 318          * Set HCE bit (Host Configuration Enabled)
 319          */
 320         pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
 321         pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
 322
 323 #ifdef CONFIG_PCI_PNP
 324         /*--------------------------------------------------------------------------+
 325          * Scan the PCI bus and configure devices found.
 326          *--------------------------------------------------------------------------*/
 327 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
 328         if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
 329             (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
 330 #endif
 331         {
 332 #ifdef CONFIG_PCI_SCAN_SHOW
 333                 printf("PCI:   Bus Dev VenId DevId Class Int\n");
 334 #endif
 335                 hose->last_busno = pci_hose_scan(hose);
 336         }
 337 #endif  /* CONFIG_PCI_PNP */
 338
 339 }
 340
 341 /*
 342  * drivers/pci.c skips every host bridge but the 405GP since it could
 343  * be set as an Adapter.
 344  *
 345  * I (Andrew May) don't know what we should do here, but I don't want
 346  * the auto setup of a PCI device disabling what is done pci_405gp_init
 347  * as has happened before.
 348  */
 349 void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
 350                             struct pci_config_table *entry)
 351 {
 352 #ifdef DEBUG
 353         printf("405gp_setup_bridge\n");
 354 #endif
 355 }
 356
 357 /*
 358  *
 359  */
 360
 361 void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 362 {
 363         unsigned char int_line = 0xff;
 364
 365         /*
 366          * Write pci interrupt line register (cpci405 specific)
 367          */
 368         switch (PCI_DEV(dev) & 0x03)
 369         {
 370         case 0:
 371                 int_line = 27 + 2;
 372                 break;
 373         case 1:
 374                 int_line = 27 + 3;
 375                 break;
 376         case 2:
 377                 int_line = 27 + 0;
 378                 break;
 379         case 3:
 380                 int_line = 27 + 1;
 381                 break;
 382         }
 383
 384         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
 385 }
 386
 387 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
 388                          struct pci_config_table *entry)
 389 {
 390         unsigned int cmdstat = 0;
 391
 392         pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
 393
 394         /* always enable io space on vga boards */
 395         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
 396         cmdstat |= PCI_COMMAND_IO;
 397         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
 398 }
 399
 400 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
 401
 402 /*
 403  *As is these functs get called out of flash Not a horrible
 404  *thing, but something to keep in mind. (no statics?)
 405  */
 406 static struct pci_config_table pci_405gp_config_table[] = {
 407 /*if VendID is 0 it terminates the table search (ie Walnut)*/
 408 #ifdef CFG_PCI_SUBSYS_VENDORID
 409         {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
 410          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
 411 #endif
 412         {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
 413          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
 414
 415         {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
 416          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
 417
 418         { }
 419 };
 420
 421 static struct pci_controller hose = {
 422         fixup_irq: pci_405gp_fixup_irq,
 423         config_table: pci_405gp_config_table,
 424 };
 425
 426 void pci_init_board(void)
 427 {
 428         /*we want the ptrs to RAM not flash (ie don't use init list)*/
 429         hose.fixup_irq    = pci_405gp_fixup_irq;
 430         hose.config_table = pci_405gp_config_table;
 431         pci_405gp_init(&hose);
 432 }
 433
 434 #endif
 435
 436 #endif /* CONFIG_405GP */
 437
 438 /*-----------------------------------------------------------------------------+
 439  * CONFIG_440
 440  *-----------------------------------------------------------------------------*/
 441 #if defined(CONFIG_440)
 442
 443 static struct pci_controller ppc440_hose = {0};
 444
 445
 446 int pci_440_init (struct pci_controller *hose)
 447 {
 448         int reg_num = 0;
 449
 450 #ifndef CONFIG_DISABLE_PISE_TEST
 451         /*--------------------------------------------------------------------------+
 452          * The PCI initialization sequence enable bit must be set ... if not abort
 453          * pci setup since updating the bit requires chip reset.
 454          *--------------------------------------------------------------------------*/
 455 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 456         unsigned long strap;
 457
 458         mfsdr(sdr_sdstp1,strap);
 459         if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
 460                 printf("PCI: SDR0_STRP1[PISE] not set.\n");
 461                 printf("PCI: Configuration aborted.\n");
 462                 return -1;
 463         }
 464 #elif defined(CONFIG_440GP)
 465         unsigned long strap;
 466
 467         strap = mfdcr(cpc0_strp1);
 468         if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
 469                 printf("PCI: CPC0_STRP1[PISE] not set.\n");
 470                 printf("PCI: Configuration aborted.\n");
 471                 return -1;
 472         }
 473 #endif
 474 #endif /* CONFIG_DISABLE_PISE_TEST */
 475
 476         /*--------------------------------------------------------------------------+
 477          * PCI controller init
 478          *--------------------------------------------------------------------------*/
 479         hose->first_busno = 0;
 480         hose->last_busno = 0;
 481
 482         /* PCI I/O space */
 483         pci_set_region(hose->regions + reg_num++,
 484                        0x00000000,
 485                        PCIX0_IOBASE,
 486                        0x10000,
 487                        PCI_REGION_IO);
 488
 489         /* PCI memory space */
 490         pci_set_region(hose->regions + reg_num++,
 491                        CFG_PCI_TARGBASE,
 492                        CFG_PCI_MEMBASE,
 493 #ifdef CFG_PCI_MEMSIZE
 494                        CFG_PCI_MEMSIZE,
 495 #else
 496                        0x10000000,
 497 #endif
 498                        PCI_REGION_MEM );
 499
 500 #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
 501         defined(CONFIG_PCI_SYS_MEM_SIZE)
 502         /* System memory space */
 503         pci_set_region(hose->regions + reg_num++,
 504                        CONFIG_PCI_SYS_MEM_BUS,
 505                        CONFIG_PCI_SYS_MEM_PHYS,
 506                        CONFIG_PCI_SYS_MEM_SIZE,
 507                        PCI_REGION_MEM | PCI_REGION_MEMORY );
 508 #endif
 509
 510         hose->region_count = reg_num;
 511
 512         pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
 513
 514         /* Let board change/modify hose & do initial checks */
 515         if (pci_pre_init (hose) == 0) {
 516                 printf("PCI: Board-specific initialization failed.\n");
 517                 printf("PCI: Configuration aborted.\n");
 518                 return -1;
 519         }
 520
 521         pci_register_hose( hose );
 522
 523         /*--------------------------------------------------------------------------+
 524          * PCI target init
 525          *--------------------------------------------------------------------------*/
 526 #if defined(CFG_PCI_TARGET_INIT)
 527         pci_target_init(hose);                /* Let board setup pci target */
 528 #else
 529         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 530         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
 531         out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 532 #endif
 533
 534 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
 535         out32r( PCIX0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
 536         out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
 537 #elif defined(PCIX0_BRDGOPT1)
 538         out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
 539         out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */
 540 #endif
 541
 542         /*--------------------------------------------------------------------------+
 543          * PCI master init: default is one 256MB region for PCI memory:
 544          * 0x3_00000000 - 0x3_0FFFFFFF  ==> CFG_PCI_MEMBASE
 545          *--------------------------------------------------------------------------*/
 546 #if defined(CFG_PCI_MASTER_INIT)
 547         pci_master_init(hose);          /* Let board setup pci master */
 548 #else
 549         out32r( PCIX0_POM0SA, 0 ); /* disable */
 550         out32r( PCIX0_POM1SA, 0 ); /* disable */
 551         out32r( PCIX0_POM2SA, 0 ); /* disable */
 552 #if defined(CONFIG_440SPE)
 553         out32r( PCIX0_POM0LAL, 0x10000000 );
 554         out32r( PCIX0_POM0LAH, 0x0000000c );
 555 #else
 556         out32r( PCIX0_POM0LAL, 0x00000000 );
 557         out32r( PCIX0_POM0LAH, 0x00000003 );
 558 #endif
 559         out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
 560         out32r( PCIX0_POM0PCIAH, 0x00000000 );
 561         out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
 562         out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
 563 #endif
 564
 565         /*--------------------------------------------------------------------------+
 566          * PCI host configuration -- we don't make any assumptions here ... the
 567          * _board_must_indicate_ what to do -- there's just too many runtime
 568          * scenarios in environments like cPCI, PPMC, etc. to make a determination
 569          * based on hard-coded values or state of arbiter enable.
 570          *--------------------------------------------------------------------------*/
 571         if (is_pci_host(hose)) {
 572 #ifdef CONFIG_PCI_SCAN_SHOW
 573                 printf("PCI:   Bus Dev VenId DevId Class Int\n");
 574 #endif
 575 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
 576     !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 577                 out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
 578 #endif
 579                 hose->last_busno = pci_hose_scan(hose);
 580         }
 581         return hose->last_busno;
 582 }
 583
 584 void pci_init_board(void)
 585 {
 586         int busno;
 587
 588         busno = pci_440_init (&ppc440_hose);
 589 #if defined(CONFIG_440SPE)
 590         pcie_setup_hoses(busno + 1);
 591 #endif
 592 }
 593
 594 #endif /* CONFIG_440 */
 595 #endif /* CONFIG_PCI */