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[people/ms/u-boot.git] / cpu / ppc4xx / 4xx_pcie.c
1 /*
2 * (C) Copyright 2006 - 2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23 /* define DEBUG for debugging output (obviously ;-)) */
24 #if 0
25 #define DEBUG
26 #endif
27
28 #include <asm/processor.h>
29 #include <asm-ppc/io.h>
30 #include <ppc4xx.h>
31 #include <common.h>
32 #include <pci.h>
33
34 #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
35 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
36 defined(CONFIG_PCI)
37
38 #include <asm/4xx_pcie.h>
39
40 enum {
41 PTYPE_ENDPOINT = 0x0,
42 PTYPE_LEGACY_ENDPOINT = 0x1,
43 PTYPE_ROOT_PORT = 0x4,
44
45 LNKW_X1 = 0x1,
46 LNKW_X4 = 0x4,
47 LNKW_X8 = 0x8
48 };
49
50 static int validate_endpoint(struct pci_controller *hose)
51 {
52 if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE)
53 return (is_end_point(0));
54 else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE)
55 return (is_end_point(1));
56 #if CFG_PCIE_NR_PORTS > 2
57 else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE)
58 return (is_end_point(2));
59 #endif
60
61 return 0;
62 }
63
64 static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
65 {
66 u8 *base = (u8*)hose->cfg_data;
67
68 /* use local configuration space for the first bus */
69 if (PCI_BUS(devfn) == 0) {
70 if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
71 base = (u8*)CFG_PCIE0_XCFGBASE;
72 if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
73 base = (u8*)CFG_PCIE1_XCFGBASE;
74 #if CFG_PCIE_NR_PORTS > 2
75 if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
76 base = (u8*)CFG_PCIE2_XCFGBASE;
77 #endif
78 }
79
80 return base;
81 }
82
83 static void pcie_dmer_disable(void)
84 {
85 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
86 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
87 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
88 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
89 #if CFG_PCIE_NR_PORTS > 2
90 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
91 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
92 #endif
93 }
94
95 static void pcie_dmer_enable(void)
96 {
97 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
98 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
99 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
100 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
101 #if CFG_PCIE_NR_PORTS > 2
102 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
103 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
104 #endif
105 }
106
107 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
108 int offset, int len, u32 *val) {
109
110 u8 *address;
111 *val = 0;
112
113 if (validate_endpoint(hose))
114 return 0; /* No upstream config access */
115
116 /*
117 * Bus numbers are relative to hose->first_busno
118 */
119 devfn -= PCI_BDF(hose->first_busno, 0, 0);
120
121 /*
122 * NOTICE: configuration space ranges are currenlty mapped only for
123 * the first 16 buses, so such limit must be imposed. In case more
124 * buses are required the TLB settings in board/amcc/<board>/init.S
125 * need to be altered accordingly (one bus takes 1 MB of memory space).
126 */
127 if (PCI_BUS(devfn) >= 16)
128 return 0;
129
130 /*
131 * Only single device/single function is supported for the primary and
132 * secondary buses of the 440SPe host bridge.
133 */
134 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
135 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
136 return 0;
137
138 address = pcie_get_base(hose, devfn);
139 offset += devfn << 4;
140
141 /*
142 * Reading from configuration space of non-existing device can
143 * generate transaction errors. For the read duration we suppress
144 * assertion of machine check exceptions to avoid those.
145 */
146 pcie_dmer_disable ();
147
148 debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
149 switch (len) {
150 case 1:
151 *val = in_8(hose->cfg_data + offset);
152 break;
153 case 2:
154 *val = in_le16((u16 *)(hose->cfg_data + offset));
155 break;
156 default:
157 *val = in_le32((u32*)(hose->cfg_data + offset));
158 break;
159 }
160
161 pcie_dmer_enable ();
162
163 return 0;
164 }
165
166 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
167 int offset, int len, u32 val) {
168
169 u8 *address;
170
171 if (validate_endpoint(hose))
172 return 0; /* No upstream config access */
173
174 /*
175 * Bus numbers are relative to hose->first_busno
176 */
177 devfn -= PCI_BDF(hose->first_busno, 0, 0);
178
179 /*
180 * Same constraints as in pcie_read_config().
181 */
182 if (PCI_BUS(devfn) >= 16)
183 return 0;
184
185 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
186 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
187 return 0;
188
189 address = pcie_get_base(hose, devfn);
190 offset += devfn << 4;
191
192 /*
193 * Suppress MCK exceptions, similar to pcie_read_config()
194 */
195 pcie_dmer_disable ();
196
197 switch (len) {
198 case 1:
199 out_8(hose->cfg_data + offset, val);
200 break;
201 case 2:
202 out_le16((u16 *)(hose->cfg_data + offset), val);
203 break;
204 default:
205 out_le32((u32 *)(hose->cfg_data + offset), val);
206 break;
207 }
208
209 pcie_dmer_enable ();
210
211 return 0;
212 }
213
214 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
215 {
216 u32 v;
217 int rv;
218
219 rv = pcie_read_config(hose, dev, offset, 1, &v);
220 *val = (u8)v;
221 return rv;
222 }
223
224 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
225 {
226 u32 v;
227 int rv;
228
229 rv = pcie_read_config(hose, dev, offset, 2, &v);
230 *val = (u16)v;
231 return rv;
232 }
233
234 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
235 {
236 u32 v;
237 int rv;
238
239 rv = pcie_read_config(hose, dev, offset, 3, &v);
240 *val = (u32)v;
241 return rv;
242 }
243
244 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
245 {
246 return pcie_write_config(hose,(u32)dev,offset,1,val);
247 }
248
249 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
250 {
251 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
252 }
253
254 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
255 {
256 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
257 }
258
259 #if defined(CONFIG_440SPE)
260 static void ppc4xx_setup_utl(u32 port) {
261
262 volatile void *utl_base = NULL;
263
264 /*
265 * Map UTL registers
266 */
267 switch (port) {
268 case 0:
269 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
270 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
271 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
272 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
273 break;
274
275 case 1:
276 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
277 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
278 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
279 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
280 break;
281
282 case 2:
283 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
284 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
285 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
286 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
287 break;
288 }
289 utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
290
291 /*
292 * Set buffer allocations and then assert VRB and TXE.
293 */
294 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
295 out_be32(utl_base + PEUTL_INTR, 0x02000000);
296 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
297 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
298 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
299 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
300 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
301 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
302 }
303
304 static int check_error(void)
305 {
306 u32 valPE0, valPE1, valPE2;
307 int err = 0;
308
309 /* SDR0_PEGPLLLCT1 reset */
310 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000))
311 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
312
313 valPE0 = SDR_READ(PESDR0_RCSSET);
314 valPE1 = SDR_READ(PESDR1_RCSSET);
315 valPE2 = SDR_READ(PESDR2_RCSSET);
316
317 /* SDR0_PExRCSSET rstgu */
318 if (!(valPE0 & 0x01000000) ||
319 !(valPE1 & 0x01000000) ||
320 !(valPE2 & 0x01000000)) {
321 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
322 err = -1;
323 }
324
325 /* SDR0_PExRCSSET rstdl */
326 if (!(valPE0 & 0x00010000) ||
327 !(valPE1 & 0x00010000) ||
328 !(valPE2 & 0x00010000)) {
329 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
330 err = -1;
331 }
332
333 /* SDR0_PExRCSSET rstpyn */
334 if ((valPE0 & 0x00001000) ||
335 (valPE1 & 0x00001000) ||
336 (valPE2 & 0x00001000)) {
337 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
338 err = -1;
339 }
340
341 /* SDR0_PExRCSSET hldplb */
342 if ((valPE0 & 0x10000000) ||
343 (valPE1 & 0x10000000) ||
344 (valPE2 & 0x10000000)) {
345 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
346 err = -1;
347 }
348
349 /* SDR0_PExRCSSET rdy */
350 if ((valPE0 & 0x00100000) ||
351 (valPE1 & 0x00100000) ||
352 (valPE2 & 0x00100000)) {
353 printf("PCIE: SDR0_PExRCSSET rdy error\n");
354 err = -1;
355 }
356
357 /* SDR0_PExRCSSET shutdown */
358 if ((valPE0 & 0x00000100) ||
359 (valPE1 & 0x00000100) ||
360 (valPE2 & 0x00000100)) {
361 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
362 err = -1;
363 }
364 return err;
365 }
366
367 /*
368 * Initialize PCI Express core
369 */
370 int ppc4xx_init_pcie(void)
371 {
372 int time_out = 20;
373
374 /* Set PLL clock receiver to LVPECL */
375 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
376
377 if (check_error())
378 return -1;
379
380 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
381 {
382 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
383 SDR_READ(PESDR0_PLLLCT2));
384 return -1;
385 }
386 /* De-assert reset of PCIe PLL, wait for lock */
387 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
388 udelay(3);
389
390 while (time_out) {
391 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
392 time_out--;
393 udelay(1);
394 } else
395 break;
396 }
397 if (!time_out) {
398 printf("PCIE: VCO output not locked\n");
399 return -1;
400 }
401 return 0;
402 }
403 #endif
404
405 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
406 static void ppc4xx_setup_utl(u32 port)
407 {
408 volatile void *utl_base = NULL;
409
410 /*
411 * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK
412 */
413 switch (port) {
414 case 0:
415 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE));
416 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE));
417 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */
418 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
419 break;
420
421 case 1:
422 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE));
423 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE)
424 + 0x1000);
425 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */
426 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
427 break;
428 }
429 utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
430
431 /*
432 * Set buffer allocations and then assert VRB and TXE.
433 */
434 out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */
435 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
436 out_be32(utl_base + PEUTL_INTR, 0x02000000);
437 out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */
438 out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */
439 out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000);
440 out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */
441 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
442 out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */
443 }
444
445 /*
446 * TODO: double check PCI express SDR based on the latest user manual
447 * Some registers specified here no longer exist.. has to be
448 * updated based on the final EAS spec.
449 */
450 static int check_error(void)
451 {
452 u32 valPE0, valPE1;
453 int err = 0;
454
455 valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0));
456 valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1));
457
458 /* SDR0_PExRCSSET rstgu */
459 if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) {
460 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
461 err = -1;
462 }
463
464 /* SDR0_PExRCSSET rstdl */
465 if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) {
466 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
467 err = -1;
468 }
469
470 /* SDR0_PExRCSSET rstpyn */
471 if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) {
472 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
473 err = -1;
474 }
475
476 /* SDR0_PExRCSSET hldplb */
477 if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) {
478 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
479 err = -1;
480 }
481
482 /* SDR0_PExRCSSET rdy */
483 if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) {
484 printf("PCIE: SDR0_PExRCSSET rdy error\n");
485 err = -1;
486 }
487
488 return err;
489 }
490
491 /*
492 * Initialize PCI Express core as described in User Manual
493 * TODO: double check PE SDR PLL Register with the updated user manual.
494 */
495 int ppc4xx_init_pcie(void)
496 {
497 if (check_error())
498 return -1;
499
500 return 0;
501 }
502 #endif /* CONFIG_460EX */
503
504 #if defined(CONFIG_405EX)
505 static void ppc4xx_setup_utl(u32 port)
506 {
507 u32 utl_base;
508
509 /*
510 * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
511 */
512 switch (port) {
513 case 0:
514 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
515 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
516 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
517 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
518 break;
519
520 case 1:
521 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
522 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
523 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
524 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
525
526 break;
527 }
528 utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE;
529
530 /*
531 * Set buffer allocations and then assert VRB and TXE.
532 */
533 out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000);
534 out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000);
535 out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
536 out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
537 out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
538 out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
539 out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
540 out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
541
542 out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
543 out_be32((u32 *)(utl_base + PEUTL_RCSTA),
544 in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
545 }
546
547 int ppc4xx_init_pcie(void)
548 {
549 /*
550 * Nothing to do on 405EX
551 */
552 return 0;
553 }
554 #endif /* CONFIG_405EX */
555
556 /*
557 * Board-specific pcie initialization
558 * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
559 */
560
561 /*
562 * Initialize various parts of the PCI Express core for our port:
563 *
564 * - Set as a root port and enable max width
565 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
566 * - Set up UTL configuration.
567 * - Increase SERDES drive strength to levels suggested by AMCC.
568 * - De-assert RSTPYN, RSTDL and RSTGU.
569 *
570 * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
571 * with default setting 0x11310000. The register has new fields,
572 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
573 * hang.
574 */
575 #if defined(CONFIG_440SPE)
576 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
577 {
578 u32 val = 1 << 24;
579 u32 utlset1;
580
581 if (rootport) {
582 val = PTYPE_ROOT_PORT << 20;
583 utlset1 = 0x21222222;
584 } else {
585 val = PTYPE_LEGACY_ENDPOINT << 20;
586 utlset1 = 0x20222222;
587 }
588
589 if (port == 0)
590 val |= LNKW_X8 << 12;
591 else
592 val |= LNKW_X4 << 12;
593
594 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
595 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
596 if (!ppc440spe_revB())
597 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
598 SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
599 SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
600 SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
601 SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
602 if (port == 0) {
603 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
604 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
605 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
606 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
607 }
608 SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
609 ~(1 << 24 | 1 << 16)) | 1 << 12);
610
611 return 0;
612 }
613 #endif /* CONFIG_440SPE */
614
615 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
616 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
617 {
618 u32 val = 1 << 24;
619 u32 utlset1;
620
621 if (rootport) {
622 val = PTYPE_ROOT_PORT << 20;
623 utlset1 = 0x21222222;
624 } else {
625 val = PTYPE_LEGACY_ENDPOINT << 20;
626 utlset1 = 0x20222222;
627 }
628
629 if (port == 0) {
630 val |= LNKW_X1 << 12;
631 } else {
632 val |= LNKW_X4 << 12;
633 utlset1 |= 0x00101101;
634 }
635
636 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
637 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
638 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000);
639
640 switch (port) {
641 case 0:
642 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
643 SDR_WRITE(PESDR0_L0DRV, 0x00000136);
644 SDR_WRITE(PESDR0_L0CLK, 0x00000006);
645
646 SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
647 break;
648
649 case 1:
650 SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230);
651 SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
652 SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
653 SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
654 SDR_WRITE(PESDR1_L0DRV, 0x00000136);
655 SDR_WRITE(PESDR1_L1DRV, 0x00000136);
656 SDR_WRITE(PESDR1_L2DRV, 0x00000136);
657 SDR_WRITE(PESDR1_L3DRV, 0x00000136);
658 SDR_WRITE(PESDR1_L0CLK, 0x00000006);
659 SDR_WRITE(PESDR1_L1CLK, 0x00000006);
660 SDR_WRITE(PESDR1_L2CLK, 0x00000006);
661 SDR_WRITE(PESDR1_L3CLK, 0x00000006);
662
663 SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000);
664 break;
665 }
666
667 SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) |
668 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
669
670 /* Poll for PHY reset */
671 switch (port) {
672 case 0:
673 while (!(SDR_READ(PESDR0_RSTSTA) & 0x1))
674 udelay(10);
675 break;
676 case 1:
677 while (!(SDR_READ(PESDR1_RSTSTA) & 0x1))
678 udelay(10);
679 break;
680 }
681
682 SDR_WRITE(SDRN_PESDR_RCSSET(port),
683 (SDR_READ(SDRN_PESDR_RCSSET(port)) &
684 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
685 PESDRx_RCSSET_RSTPYN);
686
687 return 0;
688 }
689 #endif /* CONFIG_440SPE */
690
691 #if defined(CONFIG_405EX)
692 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
693 {
694 u32 val;
695
696 if (rootport)
697 val = 0x00401000;
698 else
699 val = 0x00101000;
700
701 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
702 SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
703 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
704 SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
705 SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
706
707 /* Assert the PE0_PHY reset */
708 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
709 udelay(1000);
710
711 /* deassert the PE0_hotreset */
712 if (is_end_point(port))
713 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
714 else
715 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
716
717 /* poll for phy !reset */
718 while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
719 ;
720
721 /* deassert the PE0_gpl_utl_reset */
722 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
723
724 if (port == 0)
725 mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
726 else
727 mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
728
729 return 0;
730 }
731 #endif /* CONFIG_405EX */
732
733 int ppc4xx_init_pcie_port_hw(int port, int rootport)
734 __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
735
736 /*
737 * We map PCI Express configuration access into the 512MB regions
738 *
739 * NOTICE: revB is very strict about PLB real addressess and ranges to
740 * be mapped for config space; it seems to only work with d_nnnn_nnnn
741 * range (hangs the core upon config transaction attempts when set
742 * otherwise) while revA uses c_nnnn_nnnn.
743 *
744 * For 440SPe revA:
745 * PCIE0: 0xc_4000_0000
746 * PCIE1: 0xc_8000_0000
747 * PCIE2: 0xc_c000_0000
748 *
749 * For 440SPe revB:
750 * PCIE0: 0xd_0000_0000
751 * PCIE1: 0xd_2000_0000
752 * PCIE2: 0xd_4000_0000
753 *
754 * For 405EX:
755 * PCIE0: 0xa000_0000
756 * PCIE1: 0xc000_0000
757 *
758 * For 460EX/GT:
759 * PCIE0: 0xd_0000_0000
760 * PCIE1: 0xd_2000_0000
761 */
762 static inline u64 ppc4xx_get_cfgaddr(int port)
763 {
764 #if defined(CONFIG_405EX)
765 if (port == 0)
766 return (u64)CFG_PCIE0_CFGBASE;
767 else
768 return (u64)CFG_PCIE1_CFGBASE;
769 #endif
770 #if defined(CONFIG_440SPE)
771 if (ppc440spe_revB()) {
772 switch (port) {
773 default: /* to satisfy compiler */
774 case 0:
775 return 0x0000000d00000000ULL;
776 case 1:
777 return 0x0000000d20000000ULL;
778 case 2:
779 return 0x0000000d40000000ULL;
780 }
781 } else {
782 switch (port) {
783 default: /* to satisfy compiler */
784 case 0:
785 return 0x0000000c40000000ULL;
786 case 1:
787 return 0x0000000c80000000ULL;
788 case 2:
789 return 0x0000000cc0000000ULL;
790 }
791 }
792 #endif
793 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
794 if (port == 0)
795 return 0x0000000d00000000ULL;
796 else
797 return 0x0000000d20000000ULL;
798 #endif
799 }
800
801 /*
802 * 4xx boards as end point and root point setup
803 * and
804 * testing inbound and out bound windows
805 *
806 * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
807 * cable which can be used to setup loop back from one port to another port.
808 * Please rememeber that unless there is a endpoint plugged in to root port it
809 * will not initialize. It is the same in case of endpoint , unless there is
810 * root port attached it will not initialize.
811 *
812 * In this release of software all the PCI-E ports are configured as either
813 * endpoint or rootpoint.In future we will have support for selective ports
814 * setup as endpoint and root point in single board.
815 *
816 * Once your board came up as root point , you can verify by reading
817 * /proc/bus/pci/devices. Where you can see the configuration registers
818 * of end point device attached to the port.
819 *
820 * Enpoint cofiguration can be verified by connecting 4xx board to any
821 * host or another 4xx board. Then try to scan the device. In case of
822 * linux use "lspci" or appripriate os command.
823 *
824 * How do I verify the inbound and out bound windows ? (4xx to 4xx)
825 * in this configuration inbound and outbound windows are setup to access
826 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
827 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
828 * This is waere your POM(PLB out bound memory window) mapped. then
829 * read the data from other 4xx board's u-boot prompt at address
830 * 0x9000 0000(SRAM). Data should match.
831 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
832 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
833 * data at 0x9000 0000(SRAM).Data should match.
834 */
835 int ppc4xx_init_pcie_port(int port, int rootport)
836 {
837 static int core_init;
838 volatile u32 val = 0;
839 int attempts;
840 u64 addr;
841 u32 low, high;
842
843 if (!core_init) {
844 if (ppc4xx_init_pcie())
845 return -1;
846 ++core_init;
847 }
848
849 /*
850 * Initialize various parts of the PCI Express core for our port
851 */
852 ppc4xx_init_pcie_port_hw(port, rootport);
853
854 /*
855 * Notice: the following delay has critical impact on device
856 * initialization - if too short (<50ms) the link doesn't get up.
857 */
858 mdelay(100);
859
860 val = SDR_READ(SDRN_PESDR_RCSSTS(port));
861 if (val & (1 << 20)) {
862 printf("PCIE%d: PGRST failed %08x\n", port, val);
863 return -1;
864 }
865
866 /*
867 * Verify link is up
868 */
869 val = SDR_READ(SDRN_PESDR_LOOP(port));
870 if (!(val & 0x00001000)) {
871 printf("PCIE%d: link is not up.\n", port);
872 return -1;
873 }
874
875 /*
876 * Setup UTL registers - but only on revA!
877 * We use default settings for revB chip.
878 */
879 if (!ppc440spe_revB())
880 ppc4xx_setup_utl(port);
881
882 /*
883 * We map PCI Express configuration access into the 512MB regions
884 */
885 addr = ppc4xx_get_cfgaddr(port);
886 low = U64_TO_U32_LOW(addr);
887 high = U64_TO_U32_HIGH(addr);
888
889 switch (port) {
890 case 0:
891 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
892 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
893 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
894 break;
895 case 1:
896 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
897 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
898 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
899 break;
900 #if CFG_PCIE_NR_PORTS > 2
901 case 2:
902 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
903 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
904 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
905 break;
906 #endif
907 }
908
909 /*
910 * Check for VC0 active and assert RDY.
911 */
912 attempts = 10;
913 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
914 if (!(attempts--)) {
915 printf("PCIE%d: VC0 not active\n", port);
916 return -1;
917 }
918 mdelay(1000);
919 }
920 SDR_WRITE(SDRN_PESDR_RCSSET(port),
921 SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
922 mdelay(100);
923
924 return 0;
925 }
926
927 int ppc4xx_init_pcie_rootport(int port)
928 {
929 return ppc4xx_init_pcie_port(port, 1);
930 }
931
932 int ppc4xx_init_pcie_endport(int port)
933 {
934 return ppc4xx_init_pcie_port(port, 0);
935 }
936
937 void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
938 {
939 volatile void *mbase = NULL;
940 volatile void *rmbase = NULL;
941
942 pci_set_ops(hose,
943 pcie_read_config_byte,
944 pcie_read_config_word,
945 pcie_read_config_dword,
946 pcie_write_config_byte,
947 pcie_write_config_word,
948 pcie_write_config_dword);
949
950 switch (port) {
951 case 0:
952 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
953 rmbase = (u32 *)CFG_PCIE0_CFGBASE;
954 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
955 break;
956 case 1:
957 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
958 rmbase = (u32 *)CFG_PCIE1_CFGBASE;
959 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
960 break;
961 #if CFG_PCIE_NR_PORTS > 2
962 case 2:
963 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
964 rmbase = (u32 *)CFG_PCIE2_CFGBASE;
965 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
966 break;
967 #endif
968 }
969
970 /*
971 * Set bus numbers on our root port
972 */
973 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
974 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
975 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
976
977 /*
978 * Set up outbound translation to hose->mem_space from PLB
979 * addresses at an offset of 0xd_0000_0000. We set the low
980 * bits of the mask to 11 to turn off splitting into 8
981 * subregions and to enable the outbound translation.
982 */
983 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
984 out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE +
985 port * CFG_PCIE_MEMSIZE);
986 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
987 in_le32(mbase + PECFG_POM0LAL));
988
989 switch (port) {
990 case 0:
991 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
992 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
993 port * CFG_PCIE_MEMSIZE);
994 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
995 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
996 ~(CFG_PCIE_MEMSIZE - 1) | 3);
997 debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
998 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
999 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
1000 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
1001 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
1002 break;
1003 case 1:
1004 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
1005 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
1006 port * CFG_PCIE_MEMSIZE);
1007 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1008 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1009 ~(CFG_PCIE_MEMSIZE - 1) | 3);
1010 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1011 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
1012 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
1013 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
1014 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
1015 break;
1016 #if CFG_PCIE_NR_PORTS > 2
1017 case 2:
1018 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
1019 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
1020 port * CFG_PCIE_MEMSIZE);
1021 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1022 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1023 ~(CFG_PCIE_MEMSIZE - 1) | 3);
1024 debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1025 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
1026 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
1027 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
1028 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
1029 break;
1030 #endif
1031 }
1032
1033 /* Set up 16GB inbound memory window at 0 */
1034 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1035 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1036 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
1037 out_le32(mbase + PECFG_BAR0LMPA, 0);
1038
1039 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1040 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1041 out_le32(mbase + PECFG_PIM0LAL, 0);
1042 out_le32(mbase + PECFG_PIM0LAH, 0);
1043 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1044 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
1045 out_le32(mbase + PECFG_PIMEN, 0x1);
1046
1047 /* Enable I/O, Mem, and Busmaster cycles */
1048 out_le16((u16 *)(mbase + PCI_COMMAND),
1049 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1050 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1051
1052 /* Set Device and Vendor Id */
1053 out_le16(mbase + 0x200, 0xaaa0 + port);
1054 out_le16(mbase + 0x202, 0xbed0 + port);
1055
1056 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1057 out_le32(mbase + 0x208, 0x06040001);
1058
1059 printf("PCIE%d: successfully set as root-complex\n", port);
1060 }
1061
1062 int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
1063 {
1064 volatile void *mbase = NULL;
1065 int attempts = 0;
1066
1067 pci_set_ops(hose,
1068 pcie_read_config_byte,
1069 pcie_read_config_word,
1070 pcie_read_config_dword,
1071 pcie_write_config_byte,
1072 pcie_write_config_word,
1073 pcie_write_config_dword);
1074
1075 switch (port) {
1076 case 0:
1077 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
1078 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
1079 break;
1080 case 1:
1081 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
1082 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
1083 break;
1084 #if defined(CFG_PCIE2_CFGBASE)
1085 case 2:
1086 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
1087 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
1088 break;
1089 #endif
1090 }
1091
1092 /*
1093 * Set up outbound translation to hose->mem_space from PLB
1094 * addresses at an offset of 0xd_0000_0000. We set the low
1095 * bits of the mask to 11 to turn off splitting into 8
1096 * subregions and to enable the outbound translation.
1097 */
1098 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
1099 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
1100
1101 switch (port) {
1102 case 0:
1103 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
1104 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
1105 port * CFG_PCIE_MEMSIZE);
1106 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
1107 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
1108 ~(CFG_PCIE_MEMSIZE - 1) | 3);
1109 break;
1110 case 1:
1111 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
1112 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
1113 port * CFG_PCIE_MEMSIZE);
1114 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1115 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1116 ~(CFG_PCIE_MEMSIZE - 1) | 3);
1117 break;
1118 #if CFG_PCIE_NR_PORTS > 2
1119 case 2:
1120 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
1121 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
1122 port * CFG_PCIE_MEMSIZE);
1123 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1124 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1125 ~(CFG_PCIE_MEMSIZE - 1) | 3);
1126 break;
1127 #endif
1128 }
1129
1130 /* Set up 64MB inbound memory window at 0 */
1131 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1132 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1133
1134 out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
1135 out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
1136
1137 /* Setup BAR0 */
1138 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
1139 out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
1140
1141 /* Disable BAR1 & BAR2 */
1142 out_le32(mbase + PECFG_BAR1MPA, 0);
1143 out_le32(mbase + PECFG_BAR2HMPA, 0);
1144 out_le32(mbase + PECFG_BAR2LMPA, 0);
1145
1146 out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE));
1147 out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE));
1148 out_le32(mbase + PECFG_PIMEN, 0x1);
1149
1150 /* Enable I/O, Mem, and Busmaster cycles */
1151 out_le16((u16 *)(mbase + PCI_COMMAND),
1152 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1153 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1154 out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
1155 out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
1156
1157 /* Set Class Code to Processor/PPC */
1158 out_le32(mbase + 0x208, 0x0b200001);
1159
1160 attempts = 10;
1161 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
1162 if (!(attempts--)) {
1163 printf("PCIE%d: BME not active\n", port);
1164 return -1;
1165 }
1166 mdelay(1000);
1167 }
1168
1169 printf("PCIE%d: successfully set as endpoint\n", port);
1170
1171 return 0;
1172 }
1173 #endif /* CONFIG_440SPE && CONFIG_PCI */
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