]>
git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/ppc4xx/cpu.c
0ad99b889c98b406d2381068acce1bdb3440f9c9
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
41 #if defined(CONFIG_440)
42 static int do_chip_reset( unsigned long sys0
, unsigned long sys1
);
45 /* ------------------------------------------------------------------------- */
49 #if defined(CONFIG_405GP) || \
50 defined(CONFIG_405CR) || \
51 defined(CONFIG_405EP) || \
52 defined(CONFIG_440) || \
53 defined(CONFIG_IOP480)
56 #if defined(CONFIG_405GP) || \
57 defined(CONFIG_405CR) || \
58 defined(CONFIG_405EP) || \
59 defined(CONFIG_IOP480)
60 DECLARE_GLOBAL_DATA_PTR
;
62 ulong clock
= gd
->cpu_clk
;
66 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
67 PPC405_SYS_INFO sys_info
;
71 get_sys_info(&sys_info
);
74 puts ("IBM PowerPC 405GP");
75 if (pvr
== PVR_405GPR_RB
) {
81 puts ("IBM PowerPC 405CR Rev. ");
84 puts ("IBM PowerPC 405EP Rev. ");
113 printf ("? (PVR=%08x)", pvr
);
117 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf
, clock
),
118 sys_info
.freqPLB
/ 1000000,
119 sys_info
.freqPLB
/ sys_info
.pllOpbDiv
/ 1000000,
120 sys_info
.freqPLB
/ sys_info
.pllExtBusDiv
/ 1000000);
122 #if defined(CONFIG_405GP)
123 if (mfdcr(strap
) & PSR_PCI_ASYNC_EN
) {
124 printf (" PCI async ext clock used, ");
126 printf (" PCI sync clock at %lu MHz, ",
127 sys_info
.freqPLB
/ sys_info
.pllPciDiv
/ 1000000);
129 printf ("%sternal PCI arbiter enabled\n",
130 (mfdcr(strap
) & PSR_PCI_ARBIT_EN
) ? "in" : "ex");
131 #elif defined(CONFIG_405EP)
132 printf (" IIC Boot EEPROM %sabled\n",
133 (mfdcr(cpc0_boot
) & CPC0_BOOT_SEP
) ? "en" : "dis");
134 printf (" PCI async ext clock used, ");
135 printf ("%sternal PCI arbiter enabled\n",
136 (mfdcr(cpc0_pci
) & CPC0_PCI_ARBIT_EN
) ? "in" : "ex");
139 #if defined(CONFIG_405EP)
140 printf (" 16 kB I-Cache 16 kB D-Cache");
142 printf (" 16 kB I-Cache %d kB D-Cache",
143 ((pvr
| 0x00000001) == PVR_405GPR_RB
) ? 16 : 8);
145 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
148 printf ("PLX IOP480 (PVR=%08x)", pvr
);
149 printf (" at %s MHz:", strmhz(buf
, clock
));
150 printf (" %u kB I-Cache", 4);
151 printf (" %u kB D-Cache", 2);
154 #if defined(CONFIG_440)
155 puts ("IBM PowerPC 440 Rev. ");
159 /* See errata 1.12: CHIP_4 */
160 if ((mfdcr(cpc0_sys0
) != mfdcr(cpc0_strp0
)) ||
161 (mfdcr(cpc0_sys1
) != mfdcr(cpc0_strp1
)) ){
162 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
163 "Resetting chip ...\n");
164 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
165 do_chip_reset ( mfdcr(cpc0_strp0
),
173 printf ("UNKNOWN (PVR=%08x)", pvr
);
183 /* ------------------------------------------------------------------------- */
185 int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
188 * Initiate system reset in debug control register DBCR
190 __asm__
__volatile__("lis 3, 0x3000" ::: "r3");
191 #if defined(CONFIG_440)
192 __asm__
__volatile__("mtspr 0x134, 3");
194 __asm__
__volatile__("mtspr 0x3f2, 3");
199 #if defined(CONFIG_440)
201 int do_chip_reset (unsigned long sys0
, unsigned long sys1
)
203 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
206 mtdcr (cntrl0
, mfdcr (cntrl0
) | 0x80000000); /* Set SWE */
207 mtdcr (cpc0_sys0
, sys0
);
208 mtdcr (cpc0_sys1
, sys1
);
209 mtdcr (cntrl0
, mfdcr (cntrl0
) & ~0x80000000); /* Clr SWE */
210 mtspr (dbcr0
, 0x20000000); /* Reset the chip */
218 * Get timebase clock frequency
220 unsigned long get_tbclk (void)
222 #if defined(CONFIG_440)
226 get_sys_info(&sys_info
);
227 return (sys_info
.freqProcessor
);
229 #elif defined(CONFIG_405GP) || \
230 defined(CONFIG_405CR) || \
231 defined(CONFIG_405) || \
232 defined(CONFIG_405EP)
234 PPC405_SYS_INFO sys_info
;
236 get_sys_info(&sys_info
);
237 return (sys_info
.freqProcessor
);
239 #elif defined(CONFIG_IOP480)
245 # error get_tbclk() not implemented
252 #if defined(CONFIG_WATCHDOG)
256 int re_enable
= disable_interrupts();
257 reset_4xx_watchdog();
258 if (re_enable
) enable_interrupts();
262 reset_4xx_watchdog(void)
267 mtspr(tsr
, 0x40000000);
269 #endif /* CONFIG_WATCHDOG */