cpu/ppc4xx/cpu.c

   1 /*
   2  * (C) Copyright 2000-2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * CPU specific code
  26  *
  27  * written or collected and sometimes rewritten by
  28  * Magnus Damm <damm@bitsmart.com>
  29  *
  30  * minor modifications by
  31  * Wolfgang Denk <wd@denx.de>
  32  */
  33
  34 #include <common.h>
  35 #include <watchdog.h>
  36 #include <command.h>
  37 #include <asm/cache.h>
  38 #include <ppc4xx.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 void board_reset(void);
  43
  44 #if defined(CONFIG_405GP) || \
  45     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  46     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  47
  48 #define PCI_ASYNC
  49
  50 static int pci_async_enabled(void)
  51 {
  52 #if defined(CONFIG_405GP)
  53         return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
  54 #endif
  55
  56 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  57     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  58     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  59         unsigned long val;
  60
  61         mfsdr(sdr_sdstp1, val);
  62         return (val & SDR0_SDSTP1_PAME_MASK);
  63 #endif
  64 }
  65 #endif
  66
  67 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
  68     !defined(CONFIG_405) && !defined(CONFIG_405EX)
  69 static int pci_arbiter_enabled(void)
  70 {
  71 #if defined(CONFIG_405GP)
  72         return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
  73 #endif
  74
  75 #if defined(CONFIG_405EP)
  76         return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
  77 #endif
  78
  79 #if defined(CONFIG_440GP)
  80         return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
  81 #endif
  82
  83 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  84         unsigned long val;
  85
  86         mfsdr(sdr_xcr, val);
  87         return (val & 0x80000000);
  88 #endif
  89 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  90     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  91     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  92         unsigned long val;
  93
  94         mfsdr(sdr_pci0, val);
  95         return (val & 0x80000000);
  96 #endif
  97 }
  98 #endif
  99
 100 #if defined(CONFIG_405EP)
 101 #define I2C_BOOTROM
 102
 103 static int i2c_bootrom_enabled(void)
 104 {
 105 #if defined(CONFIG_405EP)
 106         return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
 107 #else
 108         unsigned long val;
 109
 110         mfsdr(sdr_sdcs, val);
 111         return (val & SDR0_SDCS_SDD);
 112 #endif
 113 }
 114 #endif
 115
 116 #if defined(CONFIG_440GX)
 117 #define SDR0_PINSTP_SHIFT       29
 118 static char *bootstrap_str[] = {
 119         "EBC (16 bits)",
 120         "EBC (8 bits)",
 121         "EBC (32 bits)",
 122         "EBC (8 bits)",
 123         "PCI",
 124         "I2C (Addr 0x54)",
 125         "Reserved",
 126         "I2C (Addr 0x50)",
 127 };
 128 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
 129 #endif
 130
 131 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 132 #define SDR0_PINSTP_SHIFT       30
 133 static char *bootstrap_str[] = {
 134         "EBC (8 bits)",
 135         "PCI",
 136         "I2C (Addr 0x54)",
 137         "I2C (Addr 0x50)",
 138 };
 139 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
 140 #endif
 141
 142 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 143 #define SDR0_PINSTP_SHIFT       29
 144 static char *bootstrap_str[] = {
 145         "EBC (8 bits)",
 146         "PCI",
 147         "NAND (8 bits)",
 148         "EBC (16 bits)",
 149         "EBC (16 bits)",
 150         "I2C (Addr 0x54)",
 151         "PCI",
 152         "I2C (Addr 0x52)",
 153 };
 154 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 155 #endif
 156
 157 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 158 #define SDR0_PINSTP_SHIFT       29
 159 static char *bootstrap_str[] = {
 160         "EBC (8 bits)",
 161         "EBC (16 bits)",
 162         "EBC (16 bits)",
 163         "NAND (8 bits)",
 164         "PCI",
 165         "I2C (Addr 0x54)",
 166         "PCI",
 167         "I2C (Addr 0x52)",
 168 };
 169 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 170 #endif
 171
 172 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 173 #define SDR0_PINSTP_SHIFT       29
 174 static char *bootstrap_str[] = {
 175         "EBC (8 bits)",
 176         "EBC (16 bits)",
 177         "PCI",
 178         "PCI",
 179         "EBC (16 bits)",
 180         "NAND (8 bits)",
 181         "I2C (Addr 0x54)",      /* A8 */
 182         "I2C (Addr 0x52)",      /* A4 */
 183 };
 184 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 185 #endif
 186
 187 #if defined(CONFIG_460SX)
 188 #define SDR0_PINSTP_SHIFT       29
 189 static char *bootstrap_str[] = {
 190         "EBC (8 bits)",
 191         "EBC (16 bits)",
 192         "EBC (32 bits)",
 193         "NAND (8 bits)",
 194         "I2C (Addr 0x54)",      /* A8 */
 195         "I2C (Addr 0x52)",      /* A4 */
 196 };
 197 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
 198 #endif
 199
 200 #if defined(CONFIG_405EZ)
 201 #define SDR0_PINSTP_SHIFT       28
 202 static char *bootstrap_str[] = {
 203         "EBC (8 bits)",
 204         "SPI (fast)",
 205         "NAND (512 page, 4 addr cycle)",
 206         "I2C (Addr 0x50)",
 207         "EBC (32 bits)",
 208         "I2C (Addr 0x50)",
 209         "NAND (2K page, 5 addr cycle)",
 210         "I2C (Addr 0x50)",
 211         "EBC (16 bits)",
 212         "Reserved",
 213         "NAND (2K page, 4 addr cycle)",
 214         "I2C (Addr 0x50)",
 215         "NAND (512 page, 3 addr cycle)",
 216         "I2C (Addr 0x50)",
 217         "SPI (slow)",
 218         "I2C (Addr 0x50)",
 219 };
 220 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
 221                                  'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
 222 #endif
 223
 224 #if defined(CONFIG_405EX)
 225 #define SDR0_PINSTP_SHIFT       29
 226 static char *bootstrap_str[] = {
 227         "EBC (8 bits)",
 228         "EBC (16 bits)",
 229         "EBC (16 bits)",
 230         "NAND (8 bits)",
 231         "NAND (8 bits)",
 232         "I2C (Addr 0x54)",
 233         "EBC (8 bits)",
 234         "I2C (Addr 0x52)",
 235 };
 236 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 237 #endif
 238
 239 #if defined(SDR0_PINSTP_SHIFT)
 240 static int bootstrap_option(void)
 241 {
 242         unsigned long val;
 243
 244         mfsdr(SDR_PINSTP, val);
 245         return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
 246 }
 247 #endif /* SDR0_PINSTP_SHIFT */
 248
 249
 250 #if defined(CONFIG_440)
 251 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
 252 {
 253         /* Changes to cpc0_sys0 and cpc0_sys1 require chip
 254          * reset.
 255          */
 256         mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000);    /* Set SWE */
 257         mtdcr (cpc0_sys0, sys0);
 258         mtdcr (cpc0_sys1, sys1);
 259         mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000);   /* Clr SWE */
 260         mtspr (dbcr0, 0x20000000);      /* Reset the chip */
 261
 262         return 1;
 263 }
 264 #endif
 265
 266
 267 int checkcpu (void)
 268 {
 269 #if !defined(CONFIG_405)        /* not used on Xilinx 405 FPGA implementations */
 270         uint pvr = get_pvr();
 271         ulong clock = gd->cpu_clk;
 272         char buf[32];
 273
 274 #if !defined(CONFIG_IOP480)
 275         char addstr[64] = "";
 276         sys_info_t sys_info;
 277
 278         puts ("CPU:   ");
 279
 280         get_sys_info(&sys_info);
 281
 282 #if defined(CONFIG_XILINX_440)
 283         puts("IBM PowerPC 4");
 284 #else
 285         puts("AMCC PowerPC 4");
 286 #endif
 287
 288 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
 289     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 290     defined(CONFIG_405EX)
 291         puts("05");
 292 #endif
 293 #if defined(CONFIG_440)
 294 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 295         puts("60");
 296 #else
 297         puts("40");
 298 #endif
 299 #endif
 300
 301         switch (pvr) {
 302         case PVR_405GP_RB:
 303                 puts("GP Rev. B");
 304                 break;
 305
 306         case PVR_405GP_RC:
 307                 puts("GP Rev. C");
 308                 break;
 309
 310         case PVR_405GP_RD:
 311                 puts("GP Rev. D");
 312                 break;
 313
 314 #ifdef CONFIG_405GP
 315         case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
 316                 puts("GP Rev. E");
 317                 break;
 318 #endif
 319
 320         case PVR_405CR_RA:
 321                 puts("CR Rev. A");
 322                 break;
 323
 324         case PVR_405CR_RB:
 325                 puts("CR Rev. B");
 326                 break;
 327
 328 #ifdef CONFIG_405CR
 329         case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
 330                 puts("CR Rev. C");
 331                 break;
 332 #endif
 333
 334         case PVR_405GPR_RB:
 335                 puts("GPr Rev. B");
 336                 break;
 337
 338         case PVR_405EP_RB:
 339                 puts("EP Rev. B");
 340                 break;
 341
 342         case PVR_405EZ_RA:
 343                 puts("EZ Rev. A");
 344                 break;
 345
 346         case PVR_405EX1_RA:
 347                 puts("EX Rev. A");
 348                 strcpy(addstr, "Security support");
 349                 break;
 350
 351         case PVR_405EX2_RA:
 352                 puts("EX Rev. A");
 353                 strcpy(addstr, "No Security support");
 354                 break;
 355
 356         case PVR_405EXR1_RA:
 357                 puts("EXr Rev. A");
 358                 strcpy(addstr, "Security support");
 359                 break;
 360
 361         case PVR_405EXR2_RA:
 362                 puts("EXr Rev. A");
 363                 strcpy(addstr, "No Security support");
 364                 break;
 365
 366         case PVR_405EX1_RC:
 367                 puts("EX Rev. C");
 368                 strcpy(addstr, "Security support");
 369                 break;
 370
 371         case PVR_405EX2_RC:
 372                 puts("EX Rev. C");
 373                 strcpy(addstr, "No Security support");
 374                 break;
 375
 376         case PVR_405EXR1_RC:
 377                 puts("EXr Rev. C");
 378                 strcpy(addstr, "Security support");
 379                 break;
 380
 381         case PVR_405EXR2_RC:
 382                 puts("EXr Rev. C");
 383                 strcpy(addstr, "No Security support");
 384                 break;
 385
 386 #if defined(CONFIG_440)
 387         case PVR_440GP_RB:
 388                 puts("GP Rev. B");
 389                 /* See errata 1.12: CHIP_4 */
 390                 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
 391                     (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
 392                         puts (  "\n\t CPC0_SYSx DCRs corrupted. "
 393                                 "Resetting chip ...\n");
 394                         udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
 395                         do_chip_reset ( mfdcr(cpc0_strp0),
 396                                         mfdcr(cpc0_strp1) );
 397                 }
 398                 break;
 399
 400         case PVR_440GP_RC:
 401                 puts("GP Rev. C");
 402                 break;
 403
 404         case PVR_440GX_RA:
 405                 puts("GX Rev. A");
 406                 break;
 407
 408         case PVR_440GX_RB:
 409                 puts("GX Rev. B");
 410                 break;
 411
 412         case PVR_440GX_RC:
 413                 puts("GX Rev. C");
 414                 break;
 415
 416         case PVR_440GX_RF:
 417                 puts("GX Rev. F");
 418                 break;
 419
 420         case PVR_440EP_RA:
 421                 puts("EP Rev. A");
 422                 break;
 423
 424 #ifdef CONFIG_440EP
 425         case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
 426                 puts("EP Rev. B");
 427                 break;
 428
 429         case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
 430                 puts("EP Rev. C");
 431                 break;
 432 #endif /*  CONFIG_440EP */
 433
 434 #ifdef CONFIG_440GR
 435         case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
 436                 puts("GR Rev. A");
 437                 break;
 438
 439         case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
 440                 puts("GR Rev. B");
 441                 break;
 442 #endif /* CONFIG_440GR */
 443 #endif /* CONFIG_440 */
 444
 445 #ifdef CONFIG_440EPX
 446         case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 447                 puts("EPx Rev. A");
 448                 strcpy(addstr, "Security/Kasumi support");
 449                 break;
 450
 451         case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 452                 puts("EPx Rev. A");
 453                 strcpy(addstr, "No Security/Kasumi support");
 454                 break;
 455 #endif /* CONFIG_440EPX */
 456
 457 #ifdef CONFIG_440GRX
 458         case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 459                 puts("GRx Rev. A");
 460                 strcpy(addstr, "Security/Kasumi support");
 461                 break;
 462
 463         case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 464                 puts("GRx Rev. A");
 465                 strcpy(addstr, "No Security/Kasumi support");
 466                 break;
 467 #endif /* CONFIG_440GRX */
 468
 469         case PVR_440SP_6_RAB:
 470                 puts("SP Rev. A/B");
 471                 strcpy(addstr, "RAID 6 support");
 472                 break;
 473
 474         case PVR_440SP_RAB:
 475                 puts("SP Rev. A/B");
 476                 strcpy(addstr, "No RAID 6 support");
 477                 break;
 478
 479         case PVR_440SP_6_RC:
 480                 puts("SP Rev. C");
 481                 strcpy(addstr, "RAID 6 support");
 482                 break;
 483
 484         case PVR_440SP_RC:
 485                 puts("SP Rev. C");
 486                 strcpy(addstr, "No RAID 6 support");
 487                 break;
 488
 489         case PVR_440SPe_6_RA:
 490                 puts("SPe Rev. A");
 491                 strcpy(addstr, "RAID 6 support");
 492                 break;
 493
 494         case PVR_440SPe_RA:
 495                 puts("SPe Rev. A");
 496                 strcpy(addstr, "No RAID 6 support");
 497                 break;
 498
 499         case PVR_440SPe_6_RB:
 500                 puts("SPe Rev. B");
 501                 strcpy(addstr, "RAID 6 support");
 502                 break;
 503
 504         case PVR_440SPe_RB:
 505                 puts("SPe Rev. B");
 506                 strcpy(addstr, "No RAID 6 support");
 507                 break;
 508
 509         case PVR_460EX_RA:
 510                 puts("EX Rev. A");
 511                 strcpy(addstr, "No Security/Kasumi support");
 512                 break;
 513
 514         case PVR_460EX_SE_RA:
 515                 puts("EX Rev. A");
 516                 strcpy(addstr, "Security/Kasumi support");
 517                 break;
 518
 519         case PVR_460GT_RA:
 520                 puts("GT Rev. A");
 521                 strcpy(addstr, "No Security/Kasumi support");
 522                 break;
 523
 524         case PVR_460GT_SE_RA:
 525                 puts("GT Rev. A");
 526                 strcpy(addstr, "Security/Kasumi support");
 527                 break;
 528
 529         case PVR_460SX_RA:
 530                 puts("SX Rev. A");
 531                 strcpy(addstr, "Security support");
 532                 break;
 533
 534         case PVR_460SX_RA_V1:
 535                 puts("SX Rev. A");
 536                 strcpy(addstr, "No Security support");
 537                 break;
 538
 539         case PVR_460GX_RA:
 540                 puts("GX Rev. A");
 541                 strcpy(addstr, "Security support");
 542                 break;
 543
 544         case PVR_460GX_RA_V1:
 545                 puts("GX Rev. A");
 546                 strcpy(addstr, "No Security support");
 547                 break;
 548
 549         case PVR_VIRTEX5:
 550                 puts("x5 VIRTEX5");
 551                 break;
 552
 553         default:
 554                 printf (" UNKNOWN (PVR=%08x)", pvr);
 555                 break;
 556         }
 557
 558         printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
 559                 sys_info.freqPLB / 1000000,
 560                 get_OPB_freq() / 1000000,
 561                 sys_info.freqEBC / 1000000);
 562
 563         if (addstr[0] != 0)
 564                 printf("       %s\n", addstr);
 565
 566 #if defined(I2C_BOOTROM)
 567         printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
 568 #endif  /* I2C_BOOTROM */
 569 #if defined(SDR0_PINSTP_SHIFT)
 570         printf ("       Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
 571         printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
 572 #endif  /* SDR0_PINSTP_SHIFT */
 573
 574 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
 575         printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
 576 #endif
 577
 578 #if defined(PCI_ASYNC)
 579         if (pci_async_enabled()) {
 580                 printf (", PCI async ext clock used");
 581         } else {
 582                 printf (", PCI sync clock at %lu MHz",
 583                        sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
 584         }
 585 #endif
 586
 587 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
 588         putc('\n');
 589 #endif
 590
 591 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
 592         printf ("       16 kB I-Cache 16 kB D-Cache");
 593 #elif defined(CONFIG_440)
 594         printf ("       32 kB I-Cache 32 kB D-Cache");
 595 #else
 596         printf ("       16 kB I-Cache %d kB D-Cache",
 597                 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
 598 #endif
 599 #endif /* !defined(CONFIG_IOP480) */
 600
 601 #if defined(CONFIG_IOP480)
 602         printf ("PLX IOP480 (PVR=%08x)", pvr);
 603         printf (" at %s MHz:", strmhz(buf, clock));
 604         printf (" %u kB I-Cache", 4);
 605         printf (" %u kB D-Cache", 2);
 606 #endif
 607
 608 #endif /* !defined(CONFIG_405) */
 609
 610         putc ('\n');
 611
 612         return 0;
 613 }
 614
 615 int ppc440spe_revB() {
 616         unsigned int pvr;
 617
 618         pvr = get_pvr();
 619         if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
 620                 return 1;
 621         else
 622                 return 0;
 623 }
 624
 625 /* ------------------------------------------------------------------------- */
 626
 627 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 628 {
 629 #if defined(CONFIG_BOARD_RESET)
 630         board_reset();
 631 #else
 632 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
 633         mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
 634 #else
 635         /*
 636          * Initiate system reset in debug control register DBCR
 637          */
 638         mtspr(dbcr0, 0x30000000);
 639 #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
 640 #endif /* defined(CONFIG_BOARD_RESET) */
 641
 642         return 1;
 643 }
 644
 645
 646 /*
 647  * Get timebase clock frequency
 648  */
 649 unsigned long get_tbclk (void)
 650 {
 651 #if !defined(CONFIG_IOP480)
 652         sys_info_t  sys_info;
 653
 654         get_sys_info(&sys_info);
 655         return (sys_info.freqProcessor);
 656 #else
 657         return (66000000);
 658 #endif
 659
 660 }
 661
 662
 663 #if defined(CONFIG_WATCHDOG)
 664 void watchdog_reset(void)
 665 {
 666         int re_enable = disable_interrupts();
 667         reset_4xx_watchdog();
 668         if (re_enable) enable_interrupts();
 669 }
 670
 671 void reset_4xx_watchdog(void)
 672 {
 673         /*
 674          * Clear TSR(WIS) bit
 675          */
 676         mtspr(tsr, 0x40000000);
 677 }
 678 #endif  /* CONFIG_WATCHDOG */