cpu/ppc4xx/cpu.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * CPU specific code
  26  *
  27  * written or collected and sometimes rewritten by
  28  * Magnus Damm <damm@bitsmart.com>
  29  *
  30  * minor modifications by
  31  * Wolfgang Denk <wd@denx.de>
  32  */
  33
  34 #include <common.h>
  35 #include <watchdog.h>
  36 #include <command.h>
  37 #include <asm/cache.h>
  38 #include <ppc4xx.h>
  39
  40
  41 #if defined(CONFIG_440)
  42 static int do_chip_reset( unsigned long sys0, unsigned long sys1 );
  43 #endif
  44
  45 /* ------------------------------------------------------------------------- */
  46
  47 int checkcpu (void)
  48 {
  49 #if defined(CONFIG_405GP) || \
  50     defined(CONFIG_405CR) || \
  51     defined(CONFIG_405EP) || \
  52     defined(CONFIG_440)   || \
  53     defined(CONFIG_IOP480)
  54         uint pvr = get_pvr();
  55 #endif
  56 #if defined(CONFIG_405GP) || \
  57     defined(CONFIG_405CR) || \
  58     defined(CONFIG_405EP) || \
  59     defined(CONFIG_IOP480)
  60         DECLARE_GLOBAL_DATA_PTR;
  61
  62         ulong clock = gd->cpu_clk;
  63         char buf[32];
  64 #endif
  65
  66 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
  67         PPC405_SYS_INFO sys_info;
  68
  69         puts ("CPU:   ");
  70
  71         get_sys_info(&sys_info);
  72
  73 #ifdef CONFIG_405GP
  74         puts ("AMCC PowerPC 405GP");
  75         if (pvr == PVR_405GPR_RB) {
  76                 putc('r');
  77         }
  78         puts (" Rev. ");
  79 #endif
  80 #ifdef CONFIG_405CR
  81         puts ("AMCC PowerPC 405CR Rev. ");
  82 #endif
  83 #ifdef CONFIG_405EP
  84         puts ("AMCC PowerPC 405EP Rev. ");
  85 #endif
  86         switch (pvr) {
  87         case PVR_405GP_RB:
  88         case PVR_405GPR_RB:
  89                 putc('B');
  90                 break;
  91         case PVR_405GP_RC:
  92 #ifdef CONFIG_405CR
  93         case PVR_405CR_RC:
  94 #endif
  95                 putc('C');
  96                 break;
  97         case PVR_405GP_RD:
  98                 putc('D');
  99                 break;
 100 #ifdef CONFIG_405GP
 101         case PVR_405GP_RE:
 102                 putc('E');
 103                 break;
 104 #endif
 105         case PVR_405CR_RA:
 106                 putc('A');
 107                 break;
 108         case PVR_405CR_RB:
 109         case PVR_405EP_RB:
 110                 putc('B');
 111                 break;
 112         default:
 113                 printf ("? (PVR=%08x)", pvr);
 114                 break;
 115         }
 116
 117         printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
 118                sys_info.freqPLB / 1000000,
 119                sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
 120                sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
 121
 122 #if defined(CONFIG_405GP)
 123         if (mfdcr(strap) & PSR_PCI_ASYNC_EN) {
 124                 printf ("       PCI async ext clock used, ");
 125         } else {
 126                 printf ("       PCI sync clock at %lu MHz, ",
 127                        sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
 128         }
 129         printf ("%sternal PCI arbiter enabled\n",
 130                 (mfdcr(strap) & PSR_PCI_ARBIT_EN) ? "in" : "ex");
 131 #elif defined(CONFIG_405EP)
 132         printf ("       IIC Boot EEPROM %sabled\n",
 133                 (mfdcr(cpc0_boot) & CPC0_BOOT_SEP) ? "en" : "dis");
 134         printf ("       PCI async ext clock used, ");
 135         printf ("%sternal PCI arbiter enabled\n",
 136                 (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) ? "in" : "ex");
 137 #endif
 138
 139 #if defined(CONFIG_405EP)
 140         printf ("       16 kB I-Cache 16 kB D-Cache");
 141 #else
 142         printf ("       16 kB I-Cache %d kB D-Cache",
 143                 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
 144 #endif
 145 #endif  /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
 146
 147 #ifdef CONFIG_IOP480
 148         printf ("PLX IOP480 (PVR=%08x)", pvr);
 149         printf (" at %s MHz:", strmhz(buf, clock));
 150         printf (" %u kB I-Cache", 4);
 151         printf (" %u kB D-Cache", 2);
 152 #endif
 153
 154 #if defined(CONFIG_440)
 155         puts ("AMCC PowerPC 440");
 156         switch(pvr) {
 157         case PVR_440GP_RB:
 158                 puts("GP Rev. B");
 159                 /* See errata 1.12: CHIP_4 */
 160                 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
 161                     (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
 162                         puts (  "\n\t CPC0_SYSx DCRs corrupted. "
 163                                 "Resetting chip ...\n");
 164                         udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
 165                         do_chip_reset ( mfdcr(cpc0_strp0),
 166                                         mfdcr(cpc0_strp1) );
 167                 }
 168                 break;
 169         case PVR_440GP_RC:
 170                 puts("GP Rev. C");
 171                 break;
 172         case PVR_440GX_RA:
 173                 puts("GX Rev. A");
 174                 break;
 175         case PVR_440GX_RB:
 176                 puts("GX Rev. B");
 177                 break;
 178         case PVR_440GX_RC:
 179                 puts("GX Rev. C");
 180                 break;
 181 #if defined(CONFIG_440GR)
 182         case PVR_440EP_RA:
 183                 puts("GR Rev. A");
 184                 break;
 185         case PVR_440EP_RB:
 186                 puts("GR Rev. B");
 187                 break;
 188 #else
 189         case PVR_440EP_RA:
 190                 puts("EP Rev. A");
 191                 break;
 192         case PVR_440EP_RB:
 193                 puts("EP Rev. B");
 194                 break;
 195 #endif
 196
 197         default:
 198                 printf (" UNKNOWN (PVR=%08x)", pvr);
 199                 break;
 200         }
 201 #endif
 202         puts ("\n");
 203
 204         return 0;
 205 }
 206
 207
 208 /* ------------------------------------------------------------------------- */
 209
 210 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 211 {
 212 #if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
 213         /*give reset to BCSR*/
 214         *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
 215
 216 #else
 217
 218         /*
 219          * Initiate system reset in debug control register DBCR
 220          */
 221         __asm__ __volatile__("lis   3, 0x3000" ::: "r3");
 222 #if defined(CONFIG_440)
 223         __asm__ __volatile__("mtspr 0x134, 3");
 224 #else
 225         __asm__ __volatile__("mtspr 0x3f2, 3");
 226 #endif
 227
 228 #endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
 229         return 1;
 230 }
 231
 232 #if defined(CONFIG_440)
 233 static
 234 int do_chip_reset (unsigned long sys0, unsigned long sys1)
 235 {
 236         /* Changes to cpc0_sys0 and cpc0_sys1 require chip
 237          * reset.
 238          */
 239         mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000);    /* Set SWE */
 240         mtdcr (cpc0_sys0, sys0);
 241         mtdcr (cpc0_sys1, sys1);
 242         mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000);   /* Clr SWE */
 243         mtspr (dbcr0, 0x20000000);      /* Reset the chip */
 244
 245         return 1;
 246 }
 247 #endif
 248
 249
 250 /*
 251  * Get timebase clock frequency
 252  */
 253 unsigned long get_tbclk (void)
 254 {
 255 #if defined(CONFIG_440)
 256
 257         sys_info_t  sys_info;
 258
 259         get_sys_info(&sys_info);
 260         return (sys_info.freqProcessor);
 261
 262 #elif defined(CONFIG_405GP) || \
 263       defined(CONFIG_405CR) || \
 264       defined(CONFIG_405) || \
 265       defined(CONFIG_405EP)
 266
 267         PPC405_SYS_INFO sys_info;
 268
 269         get_sys_info(&sys_info);
 270         return (sys_info.freqProcessor);
 271
 272 #elif defined(CONFIG_IOP480)
 273
 274         return (66000000);
 275
 276 #else
 277
 278 # error get_tbclk() not implemented
 279
 280 #endif
 281
 282 }
 283
 284
 285 #if defined(CONFIG_WATCHDOG)
 286 void
 287 watchdog_reset(void)
 288 {
 289         int re_enable = disable_interrupts();
 290         reset_4xx_watchdog();
 291         if (re_enable) enable_interrupts();
 292 }
 293
 294 void
 295 reset_4xx_watchdog(void)
 296 {
 297         /*
 298          * Clear TSR(WIS) bit
 299          */
 300         mtspr(tsr, 0x40000000);
 301 }
 302 #endif  /* CONFIG_WATCHDOG */