cpu/ppc4xx/cpu.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * m8xx.c
  26  *
  27  * CPU specific code
  28  *
  29  * written or collected and sometimes rewritten by
  30  * Magnus Damm <damm@bitsmart.com>
  31  *
  32  * minor modifications by
  33  * Wolfgang Denk <wd@denx.de>
  34  */
  35
  36 #include <common.h>
  37 #include <watchdog.h>
  38 #include <command.h>
  39 #include <asm/cache.h>
  40 #include <ppc4xx.h>
  41
  42
  43 #if defined(CONFIG_440)
  44 static int do_chip_reset( unsigned long sys0, unsigned long sys1 );
  45 #endif
  46
  47 /* ------------------------------------------------------------------------- */
  48
  49 int checkcpu (void)
  50 {
  51 #if defined(CONFIG_405GP) || \
  52     defined(CONFIG_405CR) || \
  53     defined(CONFIG_IOP480) || \
  54     defined(CONFIG_440) || \
  55     defined(CONFIG_405EP)
  56         uint pvr = get_pvr();
  57 #endif
  58 #if defined(CONFIG_405GP) || \
  59     defined(CONFIG_405CR) || \
  60     defined(CONFIG_IOP480) || \
  61     defined(CONFIG_405EP)
  62         DECLARE_GLOBAL_DATA_PTR;
  63
  64         ulong clock = gd->cpu_clk;
  65         char buf[32];
  66 #endif
  67
  68 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
  69         PPC405_SYS_INFO sys_info;
  70
  71         puts ("CPU:   ");
  72
  73         get_sys_info(&sys_info);
  74
  75 #if CONFIG_405GP
  76         puts("IBM PowerPC 405GP");
  77         if (pvr == PVR_405GPR_RB) {
  78                 putc('r');
  79         }
  80         puts(" Rev. ");
  81 #endif
  82 #if CONFIG_405CR
  83         puts("IBM PowerPC 405CR Rev. ");
  84 #endif
  85 #if CONFIG_405EP
  86         puts("IBM PowerPC 405EP Rev. ");
  87 #endif
  88         switch (pvr) {
  89         case PVR_405GP_RB:
  90         case PVR_405GPR_RB:
  91                 putc('B');
  92                 break;
  93         case PVR_405GP_RC:
  94 #if CONFIG_405CR
  95         case PVR_405CR_RC:
  96 #endif
  97                 putc('C');
  98                 break;
  99         case PVR_405GP_RD:
 100                 putc('D');
 101                 break;
 102 #if CONFIG_405GP
 103         case PVR_405GP_RE:
 104                 putc('E');
 105                 break;
 106 #endif
 107         case PVR_405CR_RA:
 108                 putc('A');
 109                 break;
 110         case PVR_405CR_RB:
 111         case PVR_405EP_RB:
 112                 putc('B');
 113                 break;
 114         default:
 115                 printf("? (PVR=%08x)", pvr);
 116                 break;
 117         }
 118
 119         printf(" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
 120                sys_info.freqPLB / 1000000,
 121                sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
 122                sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
 123
 124 #if defined(CONFIG_405GP)
 125         if (mfdcr(strap) & PSR_PCI_ASYNC_EN)
 126                 printf("           PCI async ext clock used, ");
 127         else
 128                 printf("           PCI sync clock at %lu MHz, ",
 129                        sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
 130         if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
 131                 printf("internal PCI arbiter enabled\n");
 132         else
 133                 printf("external PCI arbiter enabled\n");
 134 #elif defined(CONFIG_405EP)
 135         if (mfdcr(cpc0_boot) & CPC0_BOOT_SEP)
 136                 printf("           IIC Boot EEPROM enabled\n");
 137         else
 138                 printf("           IIC Boot EEPROM disabled\n");
 139         printf("           PCI async ext clock used, ");
 140         if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN)
 141                 printf("internal PCI arbiter enabled\n");
 142         else
 143                 printf("external PCI arbiter enabled\n");
 144 #endif
 145
 146 #if defined(CONFIG_405EP)
 147         printf("           16 kB I-Cache 16 kB D-Cache");
 148 #else
 149         if ((pvr | 0x00000001) == PVR_405GPR_RB) {
 150                 printf("           16 kB I-Cache 16 kB D-Cache");
 151         } else {
 152                 printf("           16 kB I-Cache 8 kB D-Cache");
 153         }
 154 #endif
 155 #endif  /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
 156
 157 #ifdef CONFIG_IOP480
 158         printf("PLX IOP480 (PVR=%08x)", pvr);
 159         printf(" at %s MHz:", strmhz(buf, clock));
 160         printf(" %u kB I-Cache", 4);
 161         printf(" %u kB D-Cache", 2);
 162 #endif
 163
 164 #if defined(CONFIG_440)
 165         puts("IBM PowerPC 440 Rev. ");
 166         switch(pvr)
 167         {
 168         case PVR_440GP_RB:
 169                 putc('B');
 170         /* See errata 1.12: CHIP_4 */
 171         if(   ( mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0) )
 172             ||( mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1) ) ){
 173             puts("\n\t CPC0_SYSx DCRs corrupted. Resetting chip ...\n");
 174             udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
 175             do_chip_reset( mfdcr(cpc0_strp0), mfdcr(cpc0_strp1) );
 176         }
 177                 break;
 178         case PVR_440GP_RC:
 179                 putc('C');
 180                 break;
 181         default:
 182                 printf("UNKNOWN (PVR=%08x)", pvr);
 183                 break;
 184         }
 185 #endif
 186
 187         printf("\n");
 188
 189         return 0;
 190 }
 191
 192
 193 /* ------------------------------------------------------------------------- */
 194
 195 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 196 {
 197         /*
 198          * Initiate system reset in debug control register DBCR
 199          */
 200         __asm__ __volatile__("lis   3, 0x3000" ::: "r3");
 201 #if defined(CONFIG_440)
 202         __asm__ __volatile__("mtspr 0x134, 3");
 203 #else
 204         __asm__ __volatile__("mtspr 0x3f2, 3");
 205 #endif
 206         return 1;
 207 }
 208
 209 #if defined(CONFIG_440)
 210 static
 211 int do_chip_reset( unsigned long sys0, unsigned long sys1 )
 212 {
 213     /* Changes to cpc0_sys0 and cpc0_sys1 require chip
 214      * reset.
 215      */
 216     mtdcr( cntrl0, mfdcr(cntrl0) | 0x80000000 ); /* Set SWE */
 217     mtdcr( cpc0_sys0, sys0 );
 218     mtdcr( cpc0_sys1, sys1 );
 219     mtdcr( cntrl0, mfdcr(cntrl0) & ~0x80000000 ); /* Clr SWE */
 220     mtspr( dbcr0, 0x20000000);  /* Reset the chip */
 221
 222     return 1;
 223 }
 224 #endif
 225
 226
 227 /*
 228  * Get timebase clock frequency
 229  */
 230 unsigned long get_tbclk (void)
 231 {
 232 #if defined(CONFIG_440)
 233
 234         sys_info_t  sys_info;
 235
 236         get_sys_info(&sys_info);
 237         return (sys_info.freqProcessor);
 238
 239 #elif defined(CONFIG_405GP) || \
 240       defined(CONFIG_405CR) || \
 241       defined(CONFIG_405) || \
 242       defined(CONFIG_405EP)
 243
 244         PPC405_SYS_INFO sys_info;
 245
 246         get_sys_info(&sys_info);
 247         return (sys_info.freqProcessor);
 248
 249 #elif defined(CONFIG_IOP480)
 250
 251         return (66000000);
 252
 253 #else
 254
 255 # error get_tbclk() not implemented
 256
 257 #endif
 258
 259 }
 260
 261
 262 #if defined(CONFIG_WATCHDOG)
 263 void
 264 watchdog_reset(void)
 265 {
 266         int re_enable = disable_interrupts();
 267         reset_4xx_watchdog();
 268         if (re_enable) enable_interrupts();
 269 }
 270
 271 void
 272 reset_4xx_watchdog(void)
 273 {
 274         /*
 275          * Clear TSR(WIS) bit
 276          */
 277         mtspr(tsr, 0x40000000);
 278 }
 279 #endif  /* CONFIG_WATCHDOG */