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Added support for the SOLIDCARD III board from Eurodesign
[people/ms/u-boot.git] / cpu / ppc4xx / cpu_init.c
1 /*
2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <watchdog.h>
26 #include <ppc4xx_enet.h>
27 #include <asm/processor.h>
28 #include <ppc4xx.h>
29
30 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
31 DECLARE_GLOBAL_DATA_PTR;
32 #endif
33
34 #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
35
36 #ifdef CFG_INIT_DCACHE_CS
37 # if (CFG_INIT_DCACHE_CS == 0)
38 # define PBxAP pb0ap
39 # define PBxCR pb0cr
40 # if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
41 # define PBxAP_VAL CFG_EBC_PB0AP
42 # define PBxCR_VAL CFG_EBC_PB0CR
43 # endif
44 # endif
45 # if (CFG_INIT_DCACHE_CS == 1)
46 # define PBxAP pb1ap
47 # define PBxCR pb1cr
48 # if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
49 # define PBxAP_VAL CFG_EBC_PB1AP
50 # define PBxCR_VAL CFG_EBC_PB1CR
51 # endif
52 # endif
53 # if (CFG_INIT_DCACHE_CS == 2)
54 # define PBxAP pb2ap
55 # define PBxCR pb2cr
56 # if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
57 # define PBxAP_VAL CFG_EBC_PB2AP
58 # define PBxCR_VAL CFG_EBC_PB2CR
59 # endif
60 # endif
61 # if (CFG_INIT_DCACHE_CS == 3)
62 # define PBxAP pb3ap
63 # define PBxCR pb3cr
64 # if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
65 # define PBxAP_VAL CFG_EBC_PB3AP
66 # define PBxCR_VAL CFG_EBC_PB3CR
67 # endif
68 # endif
69 # if (CFG_INIT_DCACHE_CS == 4)
70 # define PBxAP pb4ap
71 # define PBxCR pb4cr
72 # if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
73 # define PBxAP_VAL CFG_EBC_PB4AP
74 # define PBxCR_VAL CFG_EBC_PB4CR
75 # endif
76 # endif
77 # if (CFG_INIT_DCACHE_CS == 5)
78 # define PBxAP pb5ap
79 # define PBxCR pb5cr
80 # if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
81 # define PBxAP_VAL CFG_EBC_PB5AP
82 # define PBxCR_VAL CFG_EBC_PB5CR
83 # endif
84 # endif
85 # if (CFG_INIT_DCACHE_CS == 6)
86 # define PBxAP pb6ap
87 # define PBxCR pb6cr
88 # if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
89 # define PBxAP_VAL CFG_EBC_PB6AP
90 # define PBxCR_VAL CFG_EBC_PB6CR
91 # endif
92 # endif
93 # if (CFG_INIT_DCACHE_CS == 7)
94 # define PBxAP pb7ap
95 # define PBxCR pb7cr
96 # if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
97 # define PBxAP_VAL CFG_EBC_PB7AP
98 # define PBxCR_VAL CFG_EBC_PB7CR
99 # endif
100 # endif
101 #endif /* CFG_INIT_DCACHE_CS */
102
103 #if defined(CFG_440_GPIO_TABLE)
104 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
105
106 void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
107 {
108 unsigned char i=0, j=0, reg_offset = 0, gpio_core;
109 unsigned long gpio_reg, gpio_core_add;
110
111 for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
112 j = 0;
113 reg_offset = 0;
114 /* GPIO config of the GPIOs 0 to 31 */
115 for (i=0; i<GPIO_MAX; i++, j++) {
116 if (i == GPIO_MAX/2) {
117 reg_offset = 4;
118 j = i-16;
119 }
120
121 gpio_core_add = (*gpio_tab)[gpio_core][i].add;
122
123 if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) ||
124 ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
125
126 switch ((*gpio_tab)[gpio_core][i].alt_nb) {
127 case GPIO_SEL:
128 break;
129
130 case GPIO_ALT1:
131 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
132 & ~(GPIO_MASK >> (j*2));
133 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
134 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
135 break;
136
137 case GPIO_ALT2:
138 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
139 & ~(GPIO_MASK >> (j*2));
140 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
141 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
142 break;
143
144 case GPIO_ALT3:
145 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
146 & ~(GPIO_MASK >> (j*2));
147 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
148 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
149 break;
150 }
151 }
152
153 if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) ||
154 ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
155
156 switch ((*gpio_tab)[gpio_core][i].alt_nb) {
157 case GPIO_SEL:
158 if (gpio_core == GPIO0) {
159 gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
160 out32(GPIO0_TCR, gpio_reg);
161 }
162
163 if (gpio_core == GPIO1) {
164 gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
165 out32(GPIO1_TCR, gpio_reg);
166 }
167
168 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
169 & ~(GPIO_MASK >> (j*2));
170 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
171 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
172 & ~(GPIO_MASK >> (j*2));
173 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
174 break;
175
176 case GPIO_ALT1:
177 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
178 & ~(GPIO_MASK >> (j*2));
179 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
180 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
181 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
182 & ~(GPIO_MASK >> (j*2));
183 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
184 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
185 break;
186
187 case GPIO_ALT2:
188 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
189 & ~(GPIO_MASK >> (j*2));
190 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
191 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
192 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
193 & ~(GPIO_MASK >> (j*2));
194 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
195 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
196 break;
197
198 case GPIO_ALT3:
199 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
200 & ~(GPIO_MASK >> (j*2));
201 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
202 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
203 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
204 & ~(GPIO_MASK >> (j*2));
205 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
206 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
207 break;
208 }
209 }
210 }
211 }
212 }
213 #endif /* CFG_440_GPIO_TABLE */
214
215 /*
216 * Breath some life into the CPU...
217 *
218 * Set up the memory map,
219 * initialize a bunch of registers
220 */
221 void
222 cpu_init_f (void)
223 {
224 #if defined(CONFIG_405EP)
225 /*
226 * GPIO0 setup (select GPIO or alternate function)
227 */
228 #if defined(CFG_GPIO0_OR)
229 out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
230 #endif
231 #if defined(CFG_GPIO0_ODR)
232 out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
233 #endif
234 out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
235 out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
236 out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
237 out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
238 out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
239 out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
240 out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
241
242 /*
243 * Set EMAC noise filter bits
244 */
245 mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
246 #endif /* CONFIG_405EP */
247
248 #if defined(CFG_440_GPIO_TABLE)
249 set_chip_gpio_configuration(&gpio_tab);
250 #endif /* CFG_440_GPIO_TABLE */
251
252 /*
253 * External Bus Controller (EBC) Setup
254 */
255 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
256 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
257 defined(CONFIG_405EP) || defined(CONFIG_405))
258 /*
259 * Move the next instructions into icache, since these modify the flash
260 * we are running from!
261 */
262 asm volatile(" bl 0f" ::: "lr");
263 asm volatile("0: mflr 3" ::: "r3");
264 asm volatile(" addi 4, 0, 14" ::: "r4");
265 asm volatile(" mtctr 4" ::: "ctr");
266 asm volatile("1: icbt 0, 3");
267 asm volatile(" addi 3, 3, 32" ::: "r3");
268 asm volatile(" bdnz 1b" ::: "ctr", "cr0");
269 asm volatile(" addis 3, 0, 0x0" ::: "r3");
270 asm volatile(" ori 3, 3, 0xA000" ::: "r3");
271 asm volatile(" mtctr 3" ::: "ctr");
272 asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
273 #endif
274
275 mtebc(pb0ap, CFG_EBC_PB0AP);
276 mtebc(pb0cr, CFG_EBC_PB0CR);
277 #endif
278
279 #if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
280 mtebc(pb1ap, CFG_EBC_PB1AP);
281 mtebc(pb1cr, CFG_EBC_PB1CR);
282 #endif
283
284 #if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
285 mtebc(pb2ap, CFG_EBC_PB2AP);
286 mtebc(pb2cr, CFG_EBC_PB2CR);
287 #endif
288
289 #if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
290 mtebc(pb3ap, CFG_EBC_PB3AP);
291 mtebc(pb3cr, CFG_EBC_PB3CR);
292 #endif
293
294 #if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
295 mtebc(pb4ap, CFG_EBC_PB4AP);
296 mtebc(pb4cr, CFG_EBC_PB4CR);
297 #endif
298
299 #if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
300 mtebc(pb5ap, CFG_EBC_PB5AP);
301 mtebc(pb5cr, CFG_EBC_PB5CR);
302 #endif
303
304 #if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
305 mtebc(pb6ap, CFG_EBC_PB6AP);
306 mtebc(pb6cr, CFG_EBC_PB6CR);
307 #endif
308
309 #if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
310 mtebc(pb7ap, CFG_EBC_PB7AP);
311 mtebc(pb7cr, CFG_EBC_PB7CR);
312 #endif
313
314 #if defined (CONFIG_SOLIDCARD3)
315 mtebc(epcr, 0xb84ef000);
316 *(unsigned long *)0x79000080 = 0x0001;
317 #endif
318 #if defined(CONFIG_WATCHDOG)
319 unsigned long val;
320
321 val = mfspr(tcr);
322 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
323 val |= 0xb8000000; /* generate system reset after 1.34 seconds */
324 #else
325 val |= 0xf0000000; /* generate system reset after 2.684 seconds */
326 #endif
327 #if defined(CFG_4xx_RESET_TYPE)
328 val &= ~0x30000000; /* clear WRC bits */
329 val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
330 #endif
331 mtspr(tcr, val);
332
333 val = mfspr(tsr);
334 val |= 0x80000000; /* enable watchdog timer */
335 mtspr(tsr, val);
336
337 reset_4xx_watchdog();
338 #endif /* CONFIG_WATCHDOG */
339 }
340
341 /*
342 * initialize higher level parts of CPU like time base and timers
343 */
344 int cpu_init_r (void)
345 {
346 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
347 bd_t *bd = gd->bd;
348 unsigned long reg;
349 #if defined(CONFIG_405GP)
350 uint pvr = get_pvr();
351 #endif
352
353 #ifdef CFG_INIT_DCACHE_CS
354 /*
355 * Flush and invalidate dcache, then disable CS for temporary stack.
356 * Afterwards, this CS can be used for other purposes
357 */
358 dcache_disable(); /* flush and invalidate dcache */
359 mtebc(PBxAP, 0);
360 mtebc(PBxCR, 0); /* disable CS for temporary stack */
361
362 #if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
363 /*
364 * Write new value into CS register
365 */
366 mtebc(PBxAP, PBxAP_VAL);
367 mtebc(PBxCR, PBxCR_VAL);
368 #endif
369 #endif /* CFG_INIT_DCACHE_CS */
370
371 /*
372 * Write Ethernetaddress into on-chip register
373 */
374 reg = 0x00000000;
375 reg |= bd->bi_enetaddr[0]; /* set high address */
376 reg = reg << 8;
377 reg |= bd->bi_enetaddr[1];
378 out32 (EMAC_IAH, reg);
379
380 reg = 0x00000000;
381 reg |= bd->bi_enetaddr[2]; /* set low address */
382 reg = reg << 8;
383 reg |= bd->bi_enetaddr[3];
384 reg = reg << 8;
385 reg |= bd->bi_enetaddr[4];
386 reg = reg << 8;
387 reg |= bd->bi_enetaddr[5];
388 out32 (EMAC_IAL, reg);
389
390 #if defined(CONFIG_405GP)
391 /*
392 * Set edge conditioning circuitry on PPC405GPr
393 * for compatibility to existing PPC405GP designs.
394 */
395 if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
396 mtdcr(ecr, 0x60606000);
397 }
398 #endif /* defined(CONFIG_405GP) */
399 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
400 return (0);
401 }
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