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Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2
[people/ms/u-boot.git] / cpu / ppc4xx / kgdb.S
1 /*
2 * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23 #include <config.h>
24 #include <command.h>
25 #include <ppc4xx.h>
26 #include <version.h>
27
28 #define CONFIG_405GP 1 /* needed for Linux kernel header files */
29 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
30
31 #include <ppc_asm.tmpl>
32 #include <ppc_defs.h>
33
34 #include <asm/cache.h>
35 #include <asm/mmu.h>
36
37 #if defined(CONFIG_CMD_KGDB)
38 /*
39 * cache flushing routines for kgdb
40 */
41
42 .globl kgdb_flush_cache_all
43 kgdb_flush_cache_all:
44 /* icache */
45 iccci r0,r0 /* iccci invalidates the entire I cache */
46 /* dcache */
47 addi r6,0,0x0000 /* clear GPR 6 */
48 addi r7,r0, 128 /* do loop for # of dcache lines */
49 /* NOTE: dccci invalidates both */
50 mtctr r7 /* ways in the D cache */
51 ..dcloop:
52 dccci 0,r6 /* invalidate line */
53 addi r6,r6, 32 /* bump to next line */
54 bdnz ..dcloop
55 blr
56
57 .globl kgdb_flush_cache_range
58 kgdb_flush_cache_range:
59 li r5,L1_CACHE_BYTES-1
60 andc r3,r3,r5
61 subf r4,r3,r4
62 add r4,r4,r5
63 srwi. r4,r4,L1_CACHE_SHIFT
64 beqlr
65 mtctr r4
66 mr r6,r3
67 1: dcbst 0,r3
68 addi r3,r3,L1_CACHE_BYTES
69 bdnz 1b
70 sync /* wait for dcbst's to get to ram */
71 mtctr r4
72 2: icbi 0,r6
73 addi r6,r6,L1_CACHE_BYTES
74 bdnz 2b
75 SYNC
76 blr
77
78 #endif