cpu/ppc4xx/start.S

   1 /*
   2  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
   5  *  Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25 /*------------------------------------------------------------------------------+
  26  *
  27  *       This source code has been made available to you by IBM on an AS-IS
  28  *       basis.  Anyone receiving this source is licensed under IBM
  29  *       copyrights to use it in any way he or she deems fit, including
  30  *       copying it, modifying it, compiling it, and redistributing it either
  31  *       with or without modifications.  No license under IBM patents or
  32  *       patent applications is to be implied by the copyright license.
  33  *
  34  *       Any user of this software should understand that IBM cannot provide
  35  *       technical support for this software and will not be responsible for
  36  *       any consequences resulting from the use of this software.
  37  *
  38  *       Any person who transfers this source code or any derivative work
  39  *       must include the IBM copyright notice, this paragraph, and the
  40  *       preceding two paragraphs in the transferred software.
  41  *
  42  *       COPYRIGHT   I B M   CORPORATION 1995
  43  *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  44  *-------------------------------------------------------------------------------
  45  */
  46
  47 /*  U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
  48  *
  49  *
  50  *  The processor starts at 0xfffffffc and the code is executed
  51  *  from flash/rom.
  52  *  in memory, but as long we don't jump around before relocating.
  53  *  board_init lies at a quite high address and when the cpu has
  54  *  jumped there, everything is ok.
  55  *  This works because the cpu gives the FLASH (CS0) the whole
  56  *  address space at startup, and board_init lies as a echo of
  57  *  the flash somewhere up there in the memorymap.
  58  *
  59  *  board_init will change CS0 to be positioned at the correct
  60  *  address and (s)dram will be positioned at address 0
  61  */
  62 #include <config.h>
  63 #include <ppc4xx.h>
  64 #include <version.h>
  65
  66 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  67
  68 #include <ppc_asm.tmpl>
  69 #include <ppc_defs.h>
  70
  71 #include <asm/cache.h>
  72 #include <asm/mmu.h>
  73
  74 #ifndef  CONFIG_IDENT_STRING
  75 #define  CONFIG_IDENT_STRING ""
  76 #endif
  77
  78 #ifdef CFG_INIT_DCACHE_CS
  79 # if (CFG_INIT_DCACHE_CS == 0)
  80 #  define PBxAP pb0ap
  81 #  define PBxCR pb0cr
  82 # endif
  83 # if (CFG_INIT_DCACHE_CS == 1)
  84 #  define PBxAP pb1ap
  85 #  define PBxCR pb1cr
  86 # endif
  87 # if (CFG_INIT_DCACHE_CS == 2)
  88 #  define PBxAP pb2ap
  89 #  define PBxCR pb2cr
  90 # endif
  91 # if (CFG_INIT_DCACHE_CS == 3)
  92 #  define PBxAP pb3ap
  93 #  define PBxCR pb3cr
  94 # endif
  95 # if (CFG_INIT_DCACHE_CS == 4)
  96 #  define PBxAP pb4ap
  97 #  define PBxCR pb4cr
  98 # endif
  99 # if (CFG_INIT_DCACHE_CS == 5)
 100 #  define PBxAP pb5ap
 101 #  define PBxCR pb5cr
 102 # endif
 103 # if (CFG_INIT_DCACHE_CS == 6)
 104 #  define PBxAP pb6ap
 105 #  define PBxCR pb6cr
 106 # endif
 107 # if (CFG_INIT_DCACHE_CS == 7)
 108 #  define PBxAP pb7ap
 109 #  define PBxCR pb7cr
 110 # endif
 111 #endif /* CFG_INIT_DCACHE_CS */
 112
 113 #define function_prolog(func_name)      .text; \
 114                                         .align 2; \
 115                                         .globl func_name; \
 116                                         func_name:
 117 #define function_epilog(func_name)      .type func_name,@function; \
 118                                         .size func_name,.-func_name
 119
 120 /* We don't want the  MMU yet.
 121 */
 122 #undef  MSR_KERNEL
 123 #define MSR_KERNEL ( MSR_ME  )  /* Machine Check */
 124
 125
 126         .extern ext_bus_cntlr_init
 127         .extern sdram_init
 128 #ifdef CONFIG_NAND_U_BOOT
 129         .extern reconfig_tlb0
 130 #endif
 131
 132 /*
 133  * Set up GOT: Global Offset Table
 134  *
 135  * Use r14 to access the GOT
 136  */
 137 #if !defined(CONFIG_NAND_SPL)
 138         START_GOT
 139         GOT_ENTRY(_GOT2_TABLE_)
 140         GOT_ENTRY(_FIXUP_TABLE_)
 141
 142         GOT_ENTRY(_start)
 143         GOT_ENTRY(_start_of_vectors)
 144         GOT_ENTRY(_end_of_vectors)
 145         GOT_ENTRY(transfer_to_handler)
 146
 147         GOT_ENTRY(__init_end)
 148         GOT_ENTRY(_end)
 149         GOT_ENTRY(__bss_start)
 150         END_GOT
 151 #endif /* CONFIG_NAND_SPL */
 152
 153 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 154         /*
 155          * NAND U-Boot image is started from offset 0
 156          */
 157         .text
 158 #if defined(CONFIG_440)
 159         bl      reconfig_tlb0
 160 #endif
 161         GET_GOT
 162         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 163         bl      board_init_f
 164 #endif
 165
 166 /*
 167  * 440 Startup -- on reset only the top 4k of the effective
 168  * address space is mapped in by an entry in the instruction
 169  * and data shadow TLB. The .bootpg section is located in the
 170  * top 4k & does only what's necessary to map in the the rest
 171  * of the boot rom. Once the boot rom is mapped in we can
 172  * proceed with normal startup.
 173  *
 174  * NOTE: CS0 only covers the top 2MB of the effective address
 175  * space after reset.
 176  */
 177
 178 #if defined(CONFIG_440)
 179 #if !defined(CONFIG_NAND_SPL)
 180     .section .bootpg,"ax"
 181 #endif
 182     .globl _start_440
 183
 184 /**************************************************************************/
 185 _start_440:
 186         /*--------------------------------------------------------------------+
 187         | 440EPX BUP Change - Hardware team request
 188         +--------------------------------------------------------------------*/
 189 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 190         sync
 191         nop
 192         nop
 193 #endif
 194         /*----------------------------------------------------------------+
 195         | Core bug fix.  Clear the esr
 196         +-----------------------------------------------------------------*/
 197         li      r0,0
 198         mtspr   esr,r0
 199         /*----------------------------------------------------------------*/
 200         /* Clear and set up some registers. */
 201         /*----------------------------------------------------------------*/
 202         iccci   r0,r0           /* NOTE: operands not used for 440 */
 203         dccci   r0,r0           /* NOTE: operands not used for 440 */
 204         sync
 205         li      r0,0
 206         mtspr   srr0,r0
 207         mtspr   srr1,r0
 208         mtspr   csrr0,r0
 209         mtspr   csrr1,r0
 210         /* NOTE: 440GX adds machine check status regs */
 211 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
 212         mtspr   mcsrr0,r0
 213         mtspr   mcsrr1,r0
 214         mfspr   r1,mcsr
 215         mtspr   mcsr,r1
 216 #endif
 217
 218         /*----------------------------------------------------------------*/
 219         /* CCR0 init */
 220         /*----------------------------------------------------------------*/
 221         /* Disable store gathering & broadcast, guarantee inst/data
 222         * cache block touch, force load/store alignment
 223         * (see errata 1.12: 440_33)
 224         */
 225         lis     r1,0x0030       /* store gathering & broadcast disable */
 226         ori     r1,r1,0x6000    /* cache touch */
 227         mtspr   ccr0,r1
 228
 229         /*----------------------------------------------------------------*/
 230         /* Initialize debug */
 231         /*----------------------------------------------------------------*/
 232         mfspr   r1,dbcr0
 233         andis.  r1, r1, 0x8000  /* test DBCR0[EDM] bit                  */
 234         bne     skip_debug_init /* if set, don't clear debug register   */
 235         mtspr   dbcr0,r0
 236         mtspr   dbcr1,r0
 237         mtspr   dbcr2,r0
 238         mtspr   iac1,r0
 239         mtspr   iac2,r0
 240         mtspr   iac3,r0
 241         mtspr   dac1,r0
 242         mtspr   dac2,r0
 243         mtspr   dvc1,r0
 244         mtspr   dvc2,r0
 245
 246         mfspr   r1,dbsr
 247         mtspr   dbsr,r1         /* Clear all valid bits */
 248 skip_debug_init:
 249
 250 #if defined (CONFIG_440SPE)
 251         /*----------------------------------------------------------------+
 252         | Initialize Core Configuration Reg1.
 253         | a. ICDPEI: Record even parity. Normal operation.
 254         | b. ICTPEI: Record even parity. Normal operation.
 255         | c. DCTPEI: Record even parity. Normal operation.
 256         | d. DCDPEI: Record even parity. Normal operation.
 257         | e. DCUPEI: Record even parity. Normal operation.
 258         | f. DCMPEI: Record even parity. Normal operation.
 259         | g. FCOM:   Normal operation
 260         | h. MMUPEI: Record even parity. Normal operation.
 261         | i. FFF:    Flush only as much data as necessary.
 262         | j. TCS:    Timebase increments from CPU clock.
 263         +-----------------------------------------------------------------*/
 264         li      r0,0
 265         mtspr   ccr1, r0
 266
 267         /*----------------------------------------------------------------+
 268         | Reset the timebase.
 269         | The previous write to CCR1 sets the timebase source.
 270         +-----------------------------------------------------------------*/
 271         mtspr   tbl, r0
 272         mtspr   tbu, r0
 273 #endif
 274
 275         /*----------------------------------------------------------------*/
 276         /* Setup interrupt vectors */
 277         /*----------------------------------------------------------------*/
 278         mtspr   ivpr,r0         /* Vectors start at 0x0000_0000 */
 279         li      r1,0x0100
 280         mtspr   ivor0,r1        /* Critical input */
 281         li      r1,0x0200
 282         mtspr   ivor1,r1        /* Machine check */
 283         li      r1,0x0300
 284         mtspr   ivor2,r1        /* Data storage */
 285         li      r1,0x0400
 286         mtspr   ivor3,r1        /* Instruction storage */
 287         li      r1,0x0500
 288         mtspr   ivor4,r1        /* External interrupt */
 289         li      r1,0x0600
 290         mtspr   ivor5,r1        /* Alignment */
 291         li      r1,0x0700
 292         mtspr   ivor6,r1        /* Program check */
 293         li      r1,0x0800
 294         mtspr   ivor7,r1        /* Floating point unavailable */
 295         li      r1,0x0c00
 296         mtspr   ivor8,r1        /* System call */
 297         li      r1,0x0a00
 298         mtspr   ivor9,r1        /* Auxiliary Processor unavailable */
 299         li      r1,0x0900
 300         mtspr   ivor10,r1       /* Decrementer */
 301         li      r1,0x1300
 302         mtspr   ivor13,r1       /* Data TLB error */
 303         li      r1,0x1400
 304         mtspr   ivor14,r1       /* Instr TLB error */
 305         li      r1,0x2000
 306         mtspr   ivor15,r1       /* Debug */
 307
 308         /*----------------------------------------------------------------*/
 309         /* Configure cache regions  */
 310         /*----------------------------------------------------------------*/
 311         mtspr   inv0,r0
 312         mtspr   inv1,r0
 313         mtspr   inv2,r0
 314         mtspr   inv3,r0
 315         mtspr   dnv0,r0
 316         mtspr   dnv1,r0
 317         mtspr   dnv2,r0
 318         mtspr   dnv3,r0
 319         mtspr   itv0,r0
 320         mtspr   itv1,r0
 321         mtspr   itv2,r0
 322         mtspr   itv3,r0
 323         mtspr   dtv0,r0
 324         mtspr   dtv1,r0
 325         mtspr   dtv2,r0
 326         mtspr   dtv3,r0
 327
 328         /*----------------------------------------------------------------*/
 329         /* Cache victim limits */
 330         /*----------------------------------------------------------------*/
 331         /* floors 0, ceiling max to use the entire cache -- nothing locked
 332         */
 333         lis     r1,0x0001
 334         ori     r1,r1,0xf800
 335         mtspr   ivlim,r1
 336         mtspr   dvlim,r1
 337
 338         /*----------------------------------------------------------------+
 339         |Initialize MMUCR[STID] = 0.
 340         +-----------------------------------------------------------------*/
 341         mfspr   r0,mmucr
 342         addis   r1,0,0xFFFF
 343         ori     r1,r1,0xFF00
 344         and     r0,r0,r1
 345         mtspr   mmucr,r0
 346
 347         /*----------------------------------------------------------------*/
 348         /* Clear all TLB entries -- TID = 0, TS = 0 */
 349         /*----------------------------------------------------------------*/
 350         addis   r0,0,0x0000
 351         li      r1,0x003f       /* 64 TLB entries */
 352         mtctr   r1
 353 rsttlb: tlbwe   r0,r1,0x0000    /* Invalidate all entries (V=0)*/
 354         tlbwe   r0,r1,0x0001
 355         tlbwe   r0,r1,0x0002
 356         subi    r1,r1,0x0001
 357         bdnz    rsttlb
 358
 359         /*----------------------------------------------------------------*/
 360         /* TLB entry setup -- step thru tlbtab */
 361         /*----------------------------------------------------------------*/
 362 #if defined(CONFIG_440SPE)
 363         /*----------------------------------------------------------------*/
 364         /* We have different TLB tables for revA and rev B of 440SPe */
 365         /*----------------------------------------------------------------*/
 366         mfspr   r1, PVR
 367         lis     r0,0x5342
 368         ori     r0,r0,0x1891
 369         cmpw    r7,r1,r0
 370         bne     r7,..revA
 371         bl      tlbtabB
 372         b       ..goon
 373 ..revA:
 374         bl      tlbtabA
 375 ..goon:
 376 #else
 377         bl      tlbtab          /* Get tlbtab pointer */
 378 #endif
 379         mr      r5,r0
 380         li      r1,0x003f       /* 64 TLB entries max */
 381         mtctr   r1
 382         li      r4,0            /* TLB # */
 383
 384         addi    r5,r5,-4
 385 1:      lwzu    r0,4(r5)
 386         cmpwi   r0,0
 387         beq     2f              /* 0 marks end */
 388         lwzu    r1,4(r5)
 389         lwzu    r2,4(r5)
 390         tlbwe   r0,r4,0         /* TLB Word 0 */
 391         tlbwe   r1,r4,1         /* TLB Word 1 */
 392         tlbwe   r2,r4,2         /* TLB Word 2 */
 393         addi    r4,r4,1         /* Next TLB */
 394         bdnz    1b
 395
 396         /*----------------------------------------------------------------*/
 397         /* Continue from 'normal' start */
 398         /*----------------------------------------------------------------*/
 399 2:
 400
 401 #if defined(CONFIG_NAND_SPL)
 402 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 403         /*
 404          * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
 405          */
 406         lis     r2,0x7fff
 407         ori     r2,r2,0xffff
 408         mfdcr   r1,isram0_dpc
 409         and     r1,r1,r2                /* Disable parity check */
 410         mtdcr   isram0_dpc,r1
 411         mfdcr   r1,isram0_pmeg
 412         and     r1,r1,r2                /* Disable pwr mgmt */
 413         mtdcr   isram0_pmeg,r1
 414 #endif
 415 #if defined(CONFIG_440EP)
 416         /*
 417          * On 440EP with no internal SRAM, we setup SDRAM very early
 418          * and copy the NAND_SPL to SDRAM and jump to it
 419          */
 420         /* Clear Dcache to use as RAM */
 421         addis   r3,r0,CFG_INIT_RAM_ADDR@h
 422         ori     r3,r3,CFG_INIT_RAM_ADDR@l
 423         addis   r4,r0,CFG_INIT_RAM_END@h
 424         ori     r4,r4,CFG_INIT_RAM_END@l
 425         rlwinm. r5,r4,0,27,31
 426         rlwinm  r5,r4,27,5,31
 427         beq     ..d_ran3
 428         addi    r5,r5,0x0001
 429 ..d_ran3:
 430         mtctr   r5
 431 ..d_ag3:
 432         dcbz    r0,r3
 433         addi    r3,r3,32
 434         bdnz    ..d_ag3
 435         /*----------------------------------------------------------------*/
 436         /* Setup the stack in internal SRAM */
 437         /*----------------------------------------------------------------*/
 438         lis     r1,CFG_INIT_RAM_ADDR@h
 439         ori     r1,r1,CFG_INIT_SP_OFFSET@l
 440         li      r0,0
 441         stwu    r0,-4(r1)
 442         stwu    r0,-4(r1)               /* Terminate call chain */
 443
 444         stwu    r1,-8(r1)               /* Save back chain and move SP */
 445         lis     r0,RESET_VECTOR@h       /* Address of reset vector */
 446         ori     r0,r0, RESET_VECTOR@l
 447         stwu    r1,-8(r1)               /* Save back chain and move SP */
 448         stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 449         sync
 450         bl      early_sdram_init
 451         sync
 452 #endif /* CONFIG_440EP */
 453
 454         /*
 455          * Copy SPL from cache into internal SRAM
 456          */
 457         li      r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
 458         mtctr   r4
 459         lis     r2,CFG_NAND_BOOT_SPL_SRC@h
 460         ori     r2,r2,CFG_NAND_BOOT_SPL_SRC@l
 461         lis     r3,CFG_NAND_BOOT_SPL_DST@h
 462         ori     r3,r3,CFG_NAND_BOOT_SPL_DST@l
 463 spl_loop:
 464         lwzu    r4,4(r2)
 465         stwu    r4,4(r3)
 466         bdnz    spl_loop
 467
 468         /*
 469          * Jump to code in RAM
 470          */
 471         bl      00f
 472 00:     mflr    r10
 473         lis     r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
 474         ori     r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
 475         sub     r10,r10,r3
 476         addi    r10,r10,28
 477         mtlr    r10
 478         blr
 479
 480 start_ram:
 481         sync
 482         isync
 483 #endif /* CONFIG_NAND_SPL */
 484
 485         bl      3f
 486         b       _start
 487
 488 3:      li      r0,0
 489         mtspr   srr1,r0         /* Keep things disabled for now */
 490         mflr    r1
 491         mtspr   srr0,r1
 492         rfi
 493 #endif /* CONFIG_440 */
 494
 495 /*
 496  * r3 - 1st arg to board_init(): IMMP pointer
 497  * r4 - 2nd arg to board_init(): boot flag
 498  */
 499 #ifndef CONFIG_NAND_SPL
 500         .text
 501         .long   0x27051956              /* U-Boot Magic Number                  */
 502         .globl  version_string
 503 version_string:
 504         .ascii U_BOOT_VERSION
 505         .ascii " (", __DATE__, " - ", __TIME__, ")"
 506         .ascii CONFIG_IDENT_STRING, "\0"
 507
 508         . = EXC_OFF_SYS_RESET
 509         .globl  _start_of_vectors
 510 _start_of_vectors:
 511
 512 /* Critical input. */
 513         CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
 514
 515 #ifdef CONFIG_440
 516 /* Machine check */
 517         MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 518 #else
 519         CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 520 #endif /* CONFIG_440 */
 521
 522 /* Data Storage exception. */
 523         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 524
 525 /* Instruction Storage exception. */
 526         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 527
 528 /* External Interrupt exception. */
 529         STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 530
 531 /* Alignment exception. */
 532         . = 0x600
 533 Alignment:
 534         EXCEPTION_PROLOG(SRR0, SRR1)
 535         mfspr   r4,DAR
 536         stw     r4,_DAR(r21)
 537         mfspr   r5,DSISR
 538         stw     r5,_DSISR(r21)
 539         addi    r3,r1,STACK_FRAME_OVERHEAD
 540         li      r20,MSR_KERNEL
 541         rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
 542         lwz     r6,GOT(transfer_to_handler)
 543         mtlr    r6
 544         blrl
 545 .L_Alignment:
 546         .long   AlignmentException - _start + _START_OFFSET
 547         .long   int_return - _start + _START_OFFSET
 548
 549 /* Program check exception */
 550         . = 0x700
 551 ProgramCheck:
 552         EXCEPTION_PROLOG(SRR0, SRR1)
 553         addi    r3,r1,STACK_FRAME_OVERHEAD
 554         li      r20,MSR_KERNEL
 555         rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
 556         lwz     r6,GOT(transfer_to_handler)
 557         mtlr    r6
 558         blrl
 559 .L_ProgramCheck:
 560         .long   ProgramCheckException - _start + _START_OFFSET
 561         .long   int_return - _start + _START_OFFSET
 562
 563 #ifdef CONFIG_440
 564         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 565         STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
 566         STD_EXCEPTION(0xa00, APU, UnknownException)
 567 #endif
 568         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 569
 570 #ifdef CONFIG_440
 571         STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
 572         STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
 573 #else
 574         STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
 575         STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 576         STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 577 #endif
 578         CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
 579
 580         .globl  _end_of_vectors
 581 _end_of_vectors:
 582         . = _START_OFFSET
 583 #endif
 584         .globl  _start
 585 _start:
 586
 587 /*****************************************************************************/
 588 #if defined(CONFIG_440)
 589
 590         /*----------------------------------------------------------------*/
 591         /* Clear and set up some registers. */
 592         /*----------------------------------------------------------------*/
 593         li      r0,0x0000
 594         lis     r1,0xffff
 595         mtspr   dec,r0                  /* prevent dec exceptions */
 596         mtspr   tbl,r0                  /* prevent fit & wdt exceptions */
 597         mtspr   tbu,r0
 598         mtspr   tsr,r1                  /* clear all timer exception status */
 599         mtspr   tcr,r0                  /* disable all */
 600         mtspr   esr,r0                  /* clear exception syndrome register */
 601         mtxer   r0                      /* clear integer exception register */
 602
 603         /*----------------------------------------------------------------*/
 604         /* Debug setup -- some (not very good) ice's need an event*/
 605         /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
 606         /* value you need in this case 0x8cff 0000 should do the trick */
 607         /*----------------------------------------------------------------*/
 608 #if defined(CFG_INIT_DBCR)
 609         lis     r1,0xffff
 610         ori     r1,r1,0xffff
 611         mtspr   dbsr,r1                 /* Clear all status bits */
 612         lis     r0,CFG_INIT_DBCR@h
 613         ori     r0,r0,CFG_INIT_DBCR@l
 614         mtspr   dbcr0,r0
 615         isync
 616 #endif
 617
 618         /*----------------------------------------------------------------*/
 619         /* Setup the internal SRAM */
 620         /*----------------------------------------------------------------*/
 621         li      r0,0
 622
 623 #ifdef CFG_INIT_RAM_DCACHE
 624         /* Clear Dcache to use as RAM */
 625         addis   r3,r0,CFG_INIT_RAM_ADDR@h
 626         ori     r3,r3,CFG_INIT_RAM_ADDR@l
 627         addis   r4,r0,CFG_INIT_RAM_END@h
 628         ori     r4,r4,CFG_INIT_RAM_END@l
 629         rlwinm. r5,r4,0,27,31
 630         rlwinm  r5,r4,27,5,31
 631         beq     ..d_ran
 632         addi    r5,r5,0x0001
 633 ..d_ran:
 634         mtctr   r5
 635 ..d_ag:
 636         dcbz    r0,r3
 637         addi    r3,r3,32
 638         bdnz    ..d_ag
 639
 640         /*
 641          * Lock the init-ram/stack in d-cache, so that other regions
 642          * may use d-cache as well
 643          * Note, that this current implementation locks exactly 4k
 644          * of d-cache, so please make sure that you don't define a
 645          * bigger init-ram area. Take a look at the lwmon5 440EPx
 646          * implementation as a reference.
 647          */
 648         msync
 649         isync
 650         /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
 651         lis     r1,0x0201
 652         ori     r1,r1,0xf808
 653         mtspr   dvlim,r1
 654         lis     r1,0x0808
 655         ori     r1,r1,0x0808
 656         mtspr   dnv0,r1
 657         mtspr   dnv1,r1
 658         mtspr   dnv2,r1
 659         mtspr   dnv3,r1
 660         mtspr   dtv0,r1
 661         mtspr   dtv1,r1
 662         mtspr   dtv2,r1
 663         mtspr   dtv3,r1
 664         msync
 665         isync
 666 #endif /* CFG_INIT_RAM_DCACHE */
 667
 668         /* 440EP & 440GR are only 440er PPC's without internal SRAM */
 669 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
 670         /* not all PPC's have internal SRAM usable as L2-cache */
 671 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 672         mtdcr   l2_cache_cfg,r0         /* Ensure L2 Cache is off */
 673 #endif
 674
 675         lis     r2,0x7fff
 676         ori     r2,r2,0xffff
 677         mfdcr   r1,isram0_dpc
 678         and     r1,r1,r2                /* Disable parity check */
 679         mtdcr   isram0_dpc,r1
 680         mfdcr   r1,isram0_pmeg
 681         and     r1,r1,r2                /* Disable pwr mgmt */
 682         mtdcr   isram0_pmeg,r1
 683
 684         lis     r1,0x8000               /* BAS = 8000_0000 */
 685 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 686         ori     r1,r1,0x0980            /* first 64k */
 687         mtdcr   isram0_sb0cr,r1
 688         lis     r1,0x8001
 689         ori     r1,r1,0x0980            /* second 64k */
 690         mtdcr   isram0_sb1cr,r1
 691         lis     r1, 0x8002
 692         ori     r1,r1, 0x0980           /* third 64k */
 693         mtdcr   isram0_sb2cr,r1
 694         lis     r1, 0x8003
 695         ori     r1,r1, 0x0980           /* fourth 64k */
 696         mtdcr   isram0_sb3cr,r1
 697 #elif defined(CONFIG_440SPE)
 698         lis     r1,0x0000               /* BAS = 0000_0000 */
 699         ori     r1,r1,0x0984            /* first 64k */
 700         mtdcr   isram0_sb0cr,r1
 701         lis     r1,0x0001
 702         ori     r1,r1,0x0984            /* second 64k */
 703         mtdcr   isram0_sb1cr,r1
 704         lis     r1, 0x0002
 705         ori     r1,r1, 0x0984           /* third 64k */
 706         mtdcr   isram0_sb2cr,r1
 707         lis     r1, 0x0003
 708         ori     r1,r1, 0x0984           /* fourth 64k */
 709         mtdcr   isram0_sb3cr,r1
 710 #elif defined(CONFIG_440GP)
 711         ori     r1,r1,0x0380            /* 8k rw */
 712         mtdcr   isram0_sb0cr,r1
 713         mtdcr   isram0_sb1cr,r0         /* Disable bank 1 */
 714 #endif
 715 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
 716
 717         /*----------------------------------------------------------------*/
 718         /* Setup the stack in internal SRAM */
 719         /*----------------------------------------------------------------*/
 720         lis     r1,CFG_INIT_RAM_ADDR@h
 721         ori     r1,r1,CFG_INIT_SP_OFFSET@l
 722         li      r0,0
 723         stwu    r0,-4(r1)
 724         stwu    r0,-4(r1)               /* Terminate call chain */
 725
 726         stwu    r1,-8(r1)               /* Save back chain and move SP */
 727         lis     r0,RESET_VECTOR@h       /* Address of reset vector */
 728         ori     r0,r0, RESET_VECTOR@l
 729         stwu    r1,-8(r1)               /* Save back chain and move SP */
 730         stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 731
 732 #ifdef CONFIG_NAND_SPL
 733         bl      nand_boot               /* will not return */
 734 #else
 735         GET_GOT
 736
 737         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 738         bl      board_init_f
 739 #endif
 740
 741 #endif /* CONFIG_440 */
 742
 743 /*****************************************************************************/
 744 #ifdef CONFIG_IOP480
 745         /*----------------------------------------------------------------------- */
 746         /* Set up some machine state registers. */
 747         /*----------------------------------------------------------------------- */
 748         addi    r0,r0,0x0000            /* initialize r0 to zero */
 749         mtspr   esr,r0                  /* clear Exception Syndrome Reg */
 750         mttcr   r0                      /* timer control register */
 751         mtexier r0                      /* disable all interrupts */
 752         addis   r4,r0,0xFFFF            /* set r4 to 0xFFFFFFFF (status in the */
 753         ori     r4,r4,0xFFFF            /* dbsr is cleared by setting bits to 1) */
 754         mtdbsr  r4                      /* clear/reset the dbsr */
 755         mtexisr r4                      /* clear all pending interrupts */
 756         addis   r4,r0,0x8000
 757         mtexier r4                      /* enable critical exceptions */
 758         addis   r4,r0,0x0000            /* assume 403GCX - enable core clk */
 759         ori     r4,r4,0x4020            /* dbling (no harm done on GA and GC */
 760         mtiocr  r4                      /* since bit not used) & DRC to latch */
 761                                         /* data bus on rising edge of CAS */
 762         /*----------------------------------------------------------------------- */
 763         /* Clear XER. */
 764         /*----------------------------------------------------------------------- */
 765         mtxer   r0
 766         /*----------------------------------------------------------------------- */
 767         /* Invalidate i-cache and d-cache TAG arrays. */
 768         /*----------------------------------------------------------------------- */
 769         addi    r3,0,1024               /* 1/4 of I-cache size, half of D-cache */
 770         addi    r4,0,1024               /* 1/4 of I-cache */
 771 ..cloop:
 772         iccci   0,r3
 773         iccci   r4,r3
 774         dccci   0,r3
 775         addic.  r3,r3,-16               /* move back one cache line */
 776         bne     ..cloop                 /* loop back to do rest until r3 = 0 */
 777
 778         /* */
 779         /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
 780         /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
 781         /* */
 782
 783         /* first copy IOP480 register base address into r3 */
 784         addis   r3,0,0x5000             /* IOP480 register base address hi */
 785 /*      ori     r3,r3,0x0000            /  IOP480 register base address lo */
 786
 787 #ifdef CONFIG_ADCIOP
 788         /* use r4 as the working variable */
 789         /* turn on CS3 (LOCCTL.7) */
 790         lwz     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 791         andi.   r4,r4,0xff7f            /* make bit 7 = 0 -- CS3 mode */
 792         stw     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 793 #endif
 794
 795 #ifdef CONFIG_DASA_SIM
 796         /* use r4 as the working variable */
 797         /* turn on MA17 (LOCCTL.7) */
 798         lwz     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 799         ori     r4,r4,0x80              /* make bit 7 = 1 -- MA17 mode */
 800         stw     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 801 #endif
 802
 803         /* turn on MA16..13 (LCS0BRD.12 = 0) */
 804         lwz     r4,0x100(r3)            /* LCS0BRD is at offset 0x100 */
 805         andi.   r4,r4,0xefff            /* make bit 12 = 0 */
 806         stw     r4,0x100(r3)            /* LCS0BRD is at offset 0x100 */
 807
 808         /* make sure above stores all comlete before going on */
 809         sync
 810
 811         /* last thing, set local init status done bit (DEVINIT.31) */
 812         lwz     r4,0x80(r3)             /* DEVINIT is at offset 0x80 */
 813         oris    r4,r4,0x8000            /* make bit 31 = 1 */
 814         stw     r4,0x80(r3)             /* DEVINIT is at offset 0x80 */
 815
 816         /* clear all pending interrupts and disable all interrupts */
 817         li      r4,-1                   /* set p1 to 0xffffffff */
 818         stw     r4,0x1b0(r3)            /* clear all pending interrupts */
 819         stw     r4,0x1b8(r3)            /* clear all pending interrupts */
 820         li      r4,0                    /* set r4 to 0 */
 821         stw     r4,0x1b4(r3)            /* disable all interrupts */
 822         stw     r4,0x1bc(r3)            /* disable all interrupts */
 823
 824         /* make sure above stores all comlete before going on */
 825         sync
 826
 827         /*----------------------------------------------------------------------- */
 828         /* Enable two 128MB cachable regions. */
 829         /*----------------------------------------------------------------------- */
 830         addis   r1,r0,0xc000
 831         addi    r1,r1,0x0001
 832         mticcr  r1                      /* instruction cache */
 833
 834         addis   r1,r0,0x0000
 835         addi    r1,r1,0x0000
 836         mtdccr  r1                      /* data cache */
 837
 838         addis   r1,r0,CFG_INIT_RAM_ADDR@h
 839         ori     r1,r1,CFG_INIT_SP_OFFSET          /* set up the stack to SDRAM */
 840         li      r0, 0                   /* Make room for stack frame header and */
 841         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 842         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 843
 844         GET_GOT                 /* initialize GOT access                        */
 845
 846         bl      board_init_f    /* run first part of init code (from Flash)     */
 847
 848 #endif  /* CONFIG_IOP480 */
 849
 850 /*****************************************************************************/
 851 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
 852     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 853     defined(CONFIG_405EX) || defined(CONFIG_405)
 854         /*----------------------------------------------------------------------- */
 855         /* Clear and set up some registers. */
 856         /*----------------------------------------------------------------------- */
 857         addi    r4,r0,0x0000
 858 #if !defined(CONFIG_405EX)
 859         mtspr   sgr,r4
 860 #else
 861         /*
 862          * On 405EX, completely clearing the SGR leads to PPC hangup
 863          * upon PCIe configuration access. The PCIe memory regions
 864          * need to be guarded!
 865          */
 866         lis     r3,0x0000
 867         ori     r3,r3,0x7FFC
 868         mtspr   sgr,r3
 869 #endif
 870         mtspr   dcwr,r4
 871         mtesr   r4                      /* clear Exception Syndrome Reg */
 872         mttcr   r4                      /* clear Timer Control Reg */
 873         mtxer   r4                      /* clear Fixed-Point Exception Reg */
 874         mtevpr  r4                      /* clear Exception Vector Prefix Reg */
 875         addi    r4,r0,(0xFFFF-0x10000)          /* set r4 to 0xFFFFFFFF (status in the */
 876                                         /* dbsr is cleared by setting bits to 1) */
 877         mtdbsr  r4                      /* clear/reset the dbsr */
 878
 879         /*----------------------------------------------------------------------- */
 880         /* Invalidate I and D caches. Enable I cache for defined memory regions */
 881         /* to speed things up. Leave the D cache disabled for now. It will be */
 882         /* enabled/left disabled later based on user selected menu options. */
 883         /* Be aware that the I cache may be disabled later based on the menu */
 884         /* options as well. See miscLib/main.c. */
 885         /*----------------------------------------------------------------------- */
 886         bl      invalidate_icache
 887         bl      invalidate_dcache
 888
 889         /*----------------------------------------------------------------------- */
 890         /* Enable two 128MB cachable regions. */
 891         /*----------------------------------------------------------------------- */
 892         lis     r4,0xc000
 893         ori     r4,r4,0x0001
 894         mticcr  r4                      /* instruction cache */
 895         isync
 896
 897         lis     r4,0x0000
 898         ori     r4,r4,0x0000
 899         mtdccr  r4                      /* data cache */
 900
 901 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX)
 902         /*----------------------------------------------------------------------- */
 903         /* Tune the speed and size for flash CS0  */
 904         /*----------------------------------------------------------------------- */
 905         bl      ext_bus_cntlr_init
 906 #endif
 907 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
 908         /*
 909          * Boards like the Kilauea (405EX) don't have OCM and can't use
 910          * DCache for init-ram. So setup stack here directly after the
 911          * SDRAM is initialized.
 912          */
 913         lis     r1, CFG_INIT_RAM_ADDR@h
 914         ori     r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
 915
 916         li      r0, 0                   /* Make room for stack frame header and */
 917         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 918         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 919         /*
 920          * Set up a dummy frame to store reset vector as return address.
 921          * this causes stack underflow to reset board.
 922          */
 923         stwu    r1, -8(r1)              /* Save back chain and move SP */
 924         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
 925         ori     r0, r0, RESET_VECTOR@l
 926         stwu    r1, -8(r1)              /* Save back chain and move SP */
 927         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
 928 #endif /* !(CFG_INIT_DCACHE_CS  || !CFG_TEM_STACK_OCM) */
 929
 930 #if defined(CONFIG_405EP)
 931         /*----------------------------------------------------------------------- */
 932         /* DMA Status, clear to come up clean */
 933         /*----------------------------------------------------------------------- */
 934         addis   r3,r0, 0xFFFF         /* Clear all existing DMA status */
 935         ori     r3,r3, 0xFFFF
 936         mtdcr   dmasr, r3
 937
 938         bl      ppc405ep_init         /* do ppc405ep specific init */
 939 #endif /* CONFIG_405EP */
 940
 941 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
 942 #if defined(CONFIG_405EZ)
 943         /********************************************************************
 944          * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
 945          *******************************************************************/
 946         /*
 947          * We can map the OCM on the PLB3, so map it at
 948          * CFG_OCM_DATA_ADDR + 0x8000
 949          */
 950         lis     r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
 951         ori     r3,r3,CFG_OCM_DATA_ADDR@l
 952         ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
 953         mtdcr   ocmplb3cr1,r3           /* Set PLB Access */
 954         ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
 955         mtdcr   ocmplb3cr2,r3           /* Set PLB Access */
 956         isync
 957
 958         lis     r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
 959         ori     r3,r3,CFG_OCM_DATA_ADDR@l
 960         ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
 961         mtdcr   ocmdscr1, r3            /* Set Data Side */
 962         mtdcr   ocmiscr1, r3            /* Set Instruction Side */
 963         ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
 964         mtdcr   ocmdscr2, r3            /* Set Data Side */
 965         mtdcr   ocmiscr2, r3            /* Set Instruction Side */
 966         addis   r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
 967         mtdcr   ocmdsisdpc,r3
 968
 969         isync
 970 #else /* CONFIG_405EZ */
 971         /********************************************************************
 972          * Setup OCM - On Chip Memory
 973          *******************************************************************/
 974         /* Setup OCM */
 975         lis     r0, 0x7FFF
 976         ori     r0, r0, 0xFFFF
 977         mfdcr   r3, ocmiscntl           /* get instr-side IRAM config */
 978         mfdcr   r4, ocmdscntl           /* get data-side IRAM config */
 979         and     r3, r3, r0              /* disable data-side IRAM */
 980         and     r4, r4, r0              /* disable data-side IRAM */
 981         mtdcr   ocmiscntl, r3           /* set instr-side IRAM config */
 982         mtdcr   ocmdscntl, r4           /* set data-side IRAM config */
 983         isync
 984
 985         lis     r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
 986         ori     r3,r3,CFG_OCM_DATA_ADDR@l
 987         mtdcr   ocmdsarc, r3
 988         addis   r4, 0, 0xC000           /* OCM data area enabled */
 989         mtdcr   ocmdscntl, r4
 990         isync
 991 #endif /* CONFIG_405EZ */
 992 #endif
 993
 994 #ifdef CONFIG_NAND_SPL
 995         /*
 996          * Copy SPL from cache into internal SRAM
 997          */
 998         li      r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
 999         mtctr   r4
1000         lis     r2,CFG_NAND_BOOT_SPL_SRC@h
1001         ori     r2,r2,CFG_NAND_BOOT_SPL_SRC@l
1002         lis     r3,CFG_NAND_BOOT_SPL_DST@h
1003         ori     r3,r3,CFG_NAND_BOOT_SPL_DST@l
1004 spl_loop:
1005         lwzu    r4,4(r2)
1006         stwu    r4,4(r3)
1007         bdnz    spl_loop
1008
1009         /*
1010          * Jump to code in RAM
1011          */
1012         bl      00f
1013 00:     mflr    r10
1014         lis     r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
1015         ori     r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
1016         sub     r10,r10,r3
1017         addi    r10,r10,28
1018         mtlr    r10
1019         blr
1020
1021 start_ram:
1022         sync
1023         isync
1024 #endif /* CONFIG_NAND_SPL */
1025
1026         /*----------------------------------------------------------------------- */
1027         /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1028         /*----------------------------------------------------------------------- */
1029 #ifdef CFG_INIT_DCACHE_CS
1030         /*----------------------------------------------------------------------- */
1031         /* Memory Bank x (nothingness) initialization 1GB+64MEG */
1032         /* used as temporary stack pointer for stage0  */
1033         /*----------------------------------------------------------------------- */
1034         li      r4,PBxAP
1035         mtdcr   ebccfga,r4
1036         lis     r4,0x0380
1037         ori     r4,r4,0x0480
1038         mtdcr   ebccfgd,r4
1039
1040         addi    r4,0,PBxCR
1041         mtdcr   ebccfga,r4
1042         lis     r4,0x400D
1043         ori     r4,r4,0xa000
1044         mtdcr   ebccfgd,r4
1045
1046         /* turn on data cache for this region */
1047         lis     r4,0x0080
1048         mtdccr  r4
1049
1050         /* set stack pointer and clear stack to known value */
1051
1052         lis     r1,CFG_INIT_RAM_ADDR@h
1053         ori     r1,r1,CFG_INIT_SP_OFFSET@l
1054
1055         li      r4,2048                 /* we store 2048 words to stack */
1056         mtctr   r4
1057
1058         lis     r2,CFG_INIT_RAM_ADDR@h          /* we also clear data area */
1059         ori     r2,r2,CFG_INIT_RAM_END@l        /* so cant copy value from r1 */
1060
1061         lis     r4,0xdead               /* we store 0xdeaddead in the stack */
1062         ori     r4,r4,0xdead
1063
1064 ..stackloop:
1065         stwu    r4,-4(r2)
1066         bdnz    ..stackloop
1067
1068         li      r0, 0                   /* Make room for stack frame header and */
1069         stwu    r0, -4(r1)              /* clear final stack frame so that      */
1070         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
1071         /*
1072          * Set up a dummy frame to store reset vector as return address.
1073          * this causes stack underflow to reset board.
1074          */
1075         stwu    r1, -8(r1)              /* Save back chain and move SP */
1076         addis   r0, 0, RESET_VECTOR@h   /* Address of reset vector */
1077         ori     r0, r0, RESET_VECTOR@l
1078         stwu    r1, -8(r1)              /* Save back chain and move SP */
1079         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1080
1081 #elif defined(CFG_TEMP_STACK_OCM) && \
1082         (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1083         /*
1084          * Stack in OCM.
1085          */
1086
1087         /* Set up Stack at top of OCM */
1088         lis     r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1089         ori     r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1090
1091         /* Set up a zeroized stack frame so that backtrace works right */
1092         li      r0, 0
1093         stwu    r0, -4(r1)
1094         stwu    r0, -4(r1)
1095
1096         /*
1097          * Set up a dummy frame to store reset vector as return address.
1098          * this causes stack underflow to reset board.
1099          */
1100         stwu    r1, -8(r1)              /* Save back chain and move SP */
1101         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
1102         ori     r0, r0, RESET_VECTOR@l
1103         stwu    r1, -8(r1)              /* Save back chain and move SP */
1104         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1105 #endif /* CFG_INIT_DCACHE_CS */
1106
1107         /*----------------------------------------------------------------------- */
1108         /* Initialize SDRAM Controller  */
1109         /*----------------------------------------------------------------------- */
1110         bl      sdram_init
1111
1112 #ifdef CONFIG_NAND_SPL
1113         bl      nand_boot               /* will not return */
1114 #else
1115         GET_GOT                 /* initialize GOT access                        */
1116
1117         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
1118
1119         /* NEVER RETURNS! */
1120         bl      board_init_f    /* run first part of init code (from Flash)     */
1121 #endif /* CONFIG_NAND_SPL */
1122
1123 #endif  /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1124         /*----------------------------------------------------------------------- */
1125
1126
1127 #ifndef CONFIG_NAND_SPL
1128 /*
1129  * This code finishes saving the registers to the exception frame
1130  * and jumps to the appropriate handler for the exception.
1131  * Register r21 is pointer into trap frame, r1 has new stack pointer.
1132  */
1133         .globl  transfer_to_handler
1134 transfer_to_handler:
1135         stw     r22,_NIP(r21)
1136         lis     r22,MSR_POW@h
1137         andc    r23,r23,r22
1138         stw     r23,_MSR(r21)
1139         SAVE_GPR(7, r21)
1140         SAVE_4GPRS(8, r21)
1141         SAVE_8GPRS(12, r21)
1142         SAVE_8GPRS(24, r21)
1143         mflr    r23
1144         andi.   r24,r23,0x3f00          /* get vector offset */
1145         stw     r24,TRAP(r21)
1146         li      r22,0
1147         stw     r22,RESULT(r21)
1148         mtspr   SPRG2,r22               /* r1 is now kernel sp */
1149         lwz     r24,0(r23)              /* virtual address of handler */
1150         lwz     r23,4(r23)              /* where to go when done */
1151         mtspr   SRR0,r24
1152         mtspr   SRR1,r20
1153         mtlr    r23
1154         SYNC
1155         rfi                             /* jump to handler, enable MMU */
1156
1157 int_return:
1158         mfmsr   r28             /* Disable interrupts */
1159         li      r4,0
1160         ori     r4,r4,MSR_EE
1161         andc    r28,r28,r4
1162         SYNC                    /* Some chip revs need this... */
1163         mtmsr   r28
1164         SYNC
1165         lwz     r2,_CTR(r1)
1166         lwz     r0,_LINK(r1)
1167         mtctr   r2
1168         mtlr    r0
1169         lwz     r2,_XER(r1)
1170         lwz     r0,_CCR(r1)
1171         mtspr   XER,r2
1172         mtcrf   0xFF,r0
1173         REST_10GPRS(3, r1)
1174         REST_10GPRS(13, r1)
1175         REST_8GPRS(23, r1)
1176         REST_GPR(31, r1)
1177         lwz     r2,_NIP(r1)     /* Restore environment */
1178         lwz     r0,_MSR(r1)
1179         mtspr   SRR0,r2
1180         mtspr   SRR1,r0
1181         lwz     r0,GPR0(r1)
1182         lwz     r2,GPR2(r1)
1183         lwz     r1,GPR1(r1)
1184         SYNC
1185         rfi
1186
1187 crit_return:
1188         mfmsr   r28             /* Disable interrupts */
1189         li      r4,0
1190         ori     r4,r4,MSR_EE
1191         andc    r28,r28,r4
1192         SYNC                    /* Some chip revs need this... */
1193         mtmsr   r28
1194         SYNC
1195         lwz     r2,_CTR(r1)
1196         lwz     r0,_LINK(r1)
1197         mtctr   r2
1198         mtlr    r0
1199         lwz     r2,_XER(r1)
1200         lwz     r0,_CCR(r1)
1201         mtspr   XER,r2
1202         mtcrf   0xFF,r0
1203         REST_10GPRS(3, r1)
1204         REST_10GPRS(13, r1)
1205         REST_8GPRS(23, r1)
1206         REST_GPR(31, r1)
1207         lwz     r2,_NIP(r1)     /* Restore environment */
1208         lwz     r0,_MSR(r1)
1209         mtspr   csrr0,r2
1210         mtspr   csrr1,r0
1211         lwz     r0,GPR0(r1)
1212         lwz     r2,GPR2(r1)
1213         lwz     r1,GPR1(r1)
1214         SYNC
1215         rfci
1216
1217 #ifdef CONFIG_440
1218 mck_return:
1219         mfmsr   r28             /* Disable interrupts */
1220         li      r4,0
1221         ori     r4,r4,MSR_EE
1222         andc    r28,r28,r4
1223         SYNC                    /* Some chip revs need this... */
1224         mtmsr   r28
1225         SYNC
1226         lwz     r2,_CTR(r1)
1227         lwz     r0,_LINK(r1)
1228         mtctr   r2
1229         mtlr    r0
1230         lwz     r2,_XER(r1)
1231         lwz     r0,_CCR(r1)
1232         mtspr   XER,r2
1233         mtcrf   0xFF,r0
1234         REST_10GPRS(3, r1)
1235         REST_10GPRS(13, r1)
1236         REST_8GPRS(23, r1)
1237         REST_GPR(31, r1)
1238         lwz     r2,_NIP(r1)     /* Restore environment */
1239         lwz     r0,_MSR(r1)
1240         mtspr   mcsrr0,r2
1241         mtspr   mcsrr1,r0
1242         lwz     r0,GPR0(r1)
1243         lwz     r2,GPR2(r1)
1244         lwz     r1,GPR1(r1)
1245         SYNC
1246         rfmci
1247 #endif /* CONFIG_440 */
1248
1249
1250         .globl get_pvr
1251 get_pvr:
1252         mfspr   r3, PVR
1253         blr
1254
1255 /*------------------------------------------------------------------------------- */
1256 /* Function:     out16 */
1257 /* Description:  Output 16 bits */
1258 /*------------------------------------------------------------------------------- */
1259         .globl  out16
1260 out16:
1261         sth     r4,0x0000(r3)
1262         blr
1263
1264 /*------------------------------------------------------------------------------- */
1265 /* Function:     out16r */
1266 /* Description:  Byte reverse and output 16 bits */
1267 /*------------------------------------------------------------------------------- */
1268         .globl  out16r
1269 out16r:
1270         sthbrx  r4,r0,r3
1271         blr
1272
1273 /*------------------------------------------------------------------------------- */
1274 /* Function:     out32r */
1275 /* Description:  Byte reverse and output 32 bits */
1276 /*------------------------------------------------------------------------------- */
1277         .globl  out32r
1278 out32r:
1279         stwbrx  r4,r0,r3
1280         blr
1281
1282 /*------------------------------------------------------------------------------- */
1283 /* Function:     in16 */
1284 /* Description:  Input 16 bits */
1285 /*------------------------------------------------------------------------------- */
1286         .globl  in16
1287 in16:
1288         lhz     r3,0x0000(r3)
1289         blr
1290
1291 /*------------------------------------------------------------------------------- */
1292 /* Function:     in16r */
1293 /* Description:  Input 16 bits and byte reverse */
1294 /*------------------------------------------------------------------------------- */
1295         .globl  in16r
1296 in16r:
1297         lhbrx   r3,r0,r3
1298         blr
1299
1300 /*------------------------------------------------------------------------------- */
1301 /* Function:     in32r */
1302 /* Description:  Input 32 bits and byte reverse */
1303 /*------------------------------------------------------------------------------- */
1304         .globl  in32r
1305 in32r:
1306         lwbrx   r3,r0,r3
1307         blr
1308
1309 /*
1310  * void relocate_code (addr_sp, gd, addr_moni)
1311  *
1312  * This "function" does not return, instead it continues in RAM
1313  * after relocating the monitor code.
1314  *
1315  * r3 = dest
1316  * r4 = src
1317  * r5 = length in bytes
1318  * r6 = cachelinesize
1319  */
1320         .globl  relocate_code
1321 relocate_code:
1322 #ifdef CONFIG_4xx_DCACHE
1323         /*
1324          * We need to flush the Init Data before the dcache will be
1325          * invalidated
1326          */
1327
1328         /* save regs */
1329         mr      r9,r3
1330         mr      r10,r4
1331         mr      r11,r5
1332
1333         mr      r3,r4
1334         addi    r4,r4,0x200     /* should be enough for init data */
1335         bl      flush_dcache_range
1336
1337         /* restore regs */
1338         mr      r3,r9
1339         mr      r4,r10
1340         mr      r5,r11
1341 #endif
1342
1343 #ifdef CFG_INIT_RAM_DCACHE
1344         /*
1345          * Unlock the previously locked d-cache
1346          */
1347         msync
1348         isync
1349         /* set TFLOOR/NFLOOR to 0 again */
1350         lis     r6,0x0001
1351         ori     r6,r6,0xf800
1352         mtspr   dvlim,r6
1353         lis     r6,0x0000
1354         ori     r6,r6,0x0000
1355         mtspr   dnv0,r6
1356         mtspr   dnv1,r6
1357         mtspr   dnv2,r6
1358         mtspr   dnv3,r6
1359         mtspr   dtv0,r6
1360         mtspr   dtv1,r6
1361         mtspr   dtv2,r6
1362         mtspr   dtv3,r6
1363         msync
1364         isync
1365 #endif /* CFG_INIT_RAM_DCACHE */
1366
1367 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1368     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1369     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1370         /*
1371          * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1372          * to speed up the boot process. Now this cache needs to be disabled.
1373          */
1374         iccci   0,0                     /* Invalidate inst cache */
1375         dccci   0,0                     /* Invalidate data cache, now no longer our stack */
1376         sync
1377         isync
1378 #ifdef CFG_TLB_FOR_BOOT_FLASH
1379         addi    r1,r0,CFG_TLB_FOR_BOOT_FLASH    /* Use defined TLB */
1380 #else
1381         addi    r1,r0,0x0000            /* Default TLB entry is #0 */
1382 #endif
1383         tlbre   r0,r1,0x0002            /* Read contents */
1384         ori     r0,r0,0x0c00            /* Or in the inhibit, write through bit */
1385         tlbwe   r0,r1,0x0002            /* Save it out */
1386         sync
1387         isync
1388 #endif
1389         mr      r1,  r3         /* Set new stack pointer                */
1390         mr      r9,  r4         /* Save copy of Init Data pointer       */
1391         mr      r10, r5         /* Save copy of Destination Address     */
1392
1393         mr      r3,  r5                         /* Destination Address  */
1394         lis     r4, CFG_MONITOR_BASE@h          /* Source      Address  */
1395         ori     r4, r4, CFG_MONITOR_BASE@l
1396         lwz     r5, GOT(__init_end)
1397         sub     r5, r5, r4
1398         li      r6, L1_CACHE_BYTES              /* Cache Line Size      */
1399
1400         /*
1401          * Fix GOT pointer:
1402          *
1403          * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1404          *
1405          * Offset:
1406          */
1407         sub     r15, r10, r4
1408
1409         /* First our own GOT */
1410         add     r14, r14, r15
1411         /* the the one used by the C code */
1412         add     r30, r30, r15
1413
1414         /*
1415          * Now relocate code
1416          */
1417
1418         cmplw   cr1,r3,r4
1419         addi    r0,r5,3
1420         srwi.   r0,r0,2
1421         beq     cr1,4f          /* In place copy is not necessary       */
1422         beq     7f              /* Protect against 0 count              */
1423         mtctr   r0
1424         bge     cr1,2f
1425
1426         la      r8,-4(r4)
1427         la      r7,-4(r3)
1428 1:      lwzu    r0,4(r8)
1429         stwu    r0,4(r7)
1430         bdnz    1b
1431         b       4f
1432
1433 2:      slwi    r0,r0,2
1434         add     r8,r4,r0
1435         add     r7,r3,r0
1436 3:      lwzu    r0,-4(r8)
1437         stwu    r0,-4(r7)
1438         bdnz    3b
1439
1440 /*
1441  * Now flush the cache: note that we must start from a cache aligned
1442  * address. Otherwise we might miss one cache line.
1443  */
1444 4:      cmpwi   r6,0
1445         add     r5,r3,r5
1446         beq     7f              /* Always flush prefetch queue in any case */
1447         subi    r0,r6,1
1448         andc    r3,r3,r0
1449         mr      r4,r3
1450 5:      dcbst   0,r4
1451         add     r4,r4,r6
1452         cmplw   r4,r5
1453         blt     5b
1454         sync                    /* Wait for all dcbst to complete on bus */
1455         mr      r4,r3
1456 6:      icbi    0,r4
1457         add     r4,r4,r6
1458         cmplw   r4,r5
1459         blt     6b
1460 7:      sync                    /* Wait for all icbi to complete on bus */
1461         isync
1462
1463 /*
1464  * We are done. Do not return, instead branch to second part of board
1465  * initialization, now running from RAM.
1466  */
1467
1468         addi    r0, r10, in_ram - _start + _START_OFFSET
1469         mtlr    r0
1470         blr                             /* NEVER RETURNS! */
1471
1472 in_ram:
1473
1474         /*
1475          * Relocation Function, r14 point to got2+0x8000
1476          *
1477          * Adjust got2 pointers, no need to check for 0, this code
1478          * already puts a few entries in the table.
1479          */
1480         li      r0,__got2_entries@sectoff@l
1481         la      r3,GOT(_GOT2_TABLE_)
1482         lwz     r11,GOT(_GOT2_TABLE_)
1483         mtctr   r0
1484         sub     r11,r3,r11
1485         addi    r3,r3,-4
1486 1:      lwzu    r0,4(r3)
1487         add     r0,r0,r11
1488         stw     r0,0(r3)
1489         bdnz    1b
1490
1491         /*
1492          * Now adjust the fixups and the pointers to the fixups
1493          * in case we need to move ourselves again.
1494          */
1495 2:      li      r0,__fixup_entries@sectoff@l
1496         lwz     r3,GOT(_FIXUP_TABLE_)
1497         cmpwi   r0,0
1498         mtctr   r0
1499         addi    r3,r3,-4
1500         beq     4f
1501 3:      lwzu    r4,4(r3)
1502         lwzux   r0,r4,r11
1503         add     r0,r0,r11
1504         stw     r10,0(r3)
1505         stw     r0,0(r4)
1506         bdnz    3b
1507 4:
1508 clear_bss:
1509         /*
1510          * Now clear BSS segment
1511          */
1512         lwz     r3,GOT(__bss_start)
1513         lwz     r4,GOT(_end)
1514
1515         cmplw   0, r3, r4
1516         beq     7f
1517
1518         li      r0, 0
1519
1520         andi.   r5, r4, 3
1521         beq     6f
1522         sub     r4, r4, r5
1523         mtctr   r5
1524         mr      r5, r4
1525 5:      stb     r0, 0(r5)
1526         addi    r5, r5, 1
1527         bdnz    5b
1528 6:
1529         stw     r0, 0(r3)
1530         addi    r3, r3, 4
1531         cmplw   0, r3, r4
1532         bne     6b
1533
1534 7:
1535         mr      r3, r9          /* Init Data pointer            */
1536         mr      r4, r10         /* Destination Address          */
1537         bl      board_init_r
1538
1539         /*
1540          * Copy exception vector code to low memory
1541          *
1542          * r3: dest_addr
1543          * r7: source address, r8: end address, r9: target address
1544          */
1545         .globl  trap_init
1546 trap_init:
1547         lwz     r7, GOT(_start_of_vectors)
1548         lwz     r8, GOT(_end_of_vectors)
1549
1550         li      r9, 0x100               /* reset vector always at 0x100 */
1551
1552         cmplw   0, r7, r8
1553         bgelr                           /* return if r7>=r8 - just in case */
1554
1555         mflr    r4                      /* save link register           */
1556 1:
1557         lwz     r0, 0(r7)
1558         stw     r0, 0(r9)
1559         addi    r7, r7, 4
1560         addi    r9, r9, 4
1561         cmplw   0, r7, r8
1562         bne     1b
1563
1564         /*
1565          * relocate `hdlr' and `int_return' entries
1566          */
1567         li      r7, .L_MachineCheck - _start + _START_OFFSET
1568         li      r8, Alignment - _start + _START_OFFSET
1569 2:
1570         bl      trap_reloc
1571         addi    r7, r7, 0x100           /* next exception vector */
1572         cmplw   0, r7, r8
1573         blt     2b
1574
1575         li      r7, .L_Alignment - _start + _START_OFFSET
1576         bl      trap_reloc
1577
1578         li      r7, .L_ProgramCheck - _start + _START_OFFSET
1579         bl      trap_reloc
1580
1581 #ifdef CONFIG_440
1582         li      r7, .L_FPUnavailable - _start + _START_OFFSET
1583         bl      trap_reloc
1584
1585         li      r7, .L_Decrementer - _start + _START_OFFSET
1586         bl      trap_reloc
1587
1588         li      r7, .L_APU - _start + _START_OFFSET
1589         bl      trap_reloc
1590
1591         li      r7, .L_InstructionTLBError - _start + _START_OFFSET
1592         bl      trap_reloc
1593
1594         li      r7, .L_DataTLBError - _start + _START_OFFSET
1595         bl      trap_reloc
1596 #else /* CONFIG_440 */
1597         li      r7, .L_PIT - _start + _START_OFFSET
1598         bl      trap_reloc
1599
1600         li      r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1601         bl      trap_reloc
1602
1603         li      r7, .L_DataTLBMiss - _start + _START_OFFSET
1604         bl      trap_reloc
1605 #endif /* CONFIG_440 */
1606
1607         li      r7, .L_DebugBreakpoint - _start + _START_OFFSET
1608         bl      trap_reloc
1609
1610 #if !defined(CONFIG_440)
1611         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1612         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1613         mtmsr   r7                      /* change MSR */
1614 #else
1615         bl      __440_msr_set
1616         b       __440_msr_continue
1617
1618 __440_msr_set:
1619         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1620         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1621         mtspr   srr1,r7
1622         mflr    r7
1623         mtspr   srr0,r7
1624         rfi
1625 __440_msr_continue:
1626 #endif
1627
1628         mtlr    r4                      /* restore link register        */
1629         blr
1630
1631         /*
1632          * Function: relocate entries for one exception vector
1633          */
1634 trap_reloc:
1635         lwz     r0, 0(r7)               /* hdlr ...                     */
1636         add     r0, r0, r3              /*  ... += dest_addr            */
1637         stw     r0, 0(r7)
1638
1639         lwz     r0, 4(r7)               /* int_return ...               */
1640         add     r0, r0, r3              /*  ... += dest_addr            */
1641         stw     r0, 4(r7)
1642
1643         blr
1644
1645 #if defined(CONFIG_440)
1646 /*----------------------------------------------------------------------------+
1647 | dcbz_area.
1648 +----------------------------------------------------------------------------*/
1649         function_prolog(dcbz_area)
1650         rlwinm. r5,r4,0,27,31
1651         rlwinm  r5,r4,27,5,31
1652         beq     ..d_ra2
1653         addi    r5,r5,0x0001
1654 ..d_ra2:mtctr   r5
1655 ..d_ag2:dcbz    r0,r3
1656         addi    r3,r3,32
1657         bdnz    ..d_ag2
1658         sync
1659         blr
1660         function_epilog(dcbz_area)
1661
1662 /*----------------------------------------------------------------------------+
1663 | dflush.  Assume 32K at vector address is cachable.
1664 +----------------------------------------------------------------------------*/
1665         function_prolog(dflush)
1666         mfmsr   r9
1667         rlwinm  r8,r9,0,15,13
1668         rlwinm  r8,r8,0,17,15
1669         mtmsr   r8
1670         mfspr   r8,dvlim
1671         addi    r3,r0,0x0000
1672         mtspr   dvlim,r3
1673         mfspr   r3,ivpr
1674         addi    r4,r0,1024
1675         mtctr   r4
1676 ..dflush_loop:
1677         lwz     r6,0x0(r3)
1678         addi    r3,r3,32
1679         bdnz    ..dflush_loop
1680         addi    r3,r3,-32
1681         mtctr   r4
1682 ..ag:   dcbf    r0,r3
1683         addi    r3,r3,-32
1684         bdnz    ..ag
1685         mtspr   dvlim,r8
1686         sync
1687         mtmsr   r9
1688         blr
1689         function_epilog(dflush)
1690 #endif /* CONFIG_440 */
1691 #endif /* CONFIG_NAND_SPL */
1692
1693 /*------------------------------------------------------------------------------- */
1694 /* Function:     in8 */
1695 /* Description:  Input 8 bits */
1696 /*------------------------------------------------------------------------------- */
1697         .globl  in8
1698 in8:
1699         lbz     r3,0x0000(r3)
1700         blr
1701
1702 /*------------------------------------------------------------------------------- */
1703 /* Function:     out8 */
1704 /* Description:  Output 8 bits */
1705 /*------------------------------------------------------------------------------- */
1706         .globl  out8
1707 out8:
1708         stb     r4,0x0000(r3)
1709         blr
1710
1711 /*------------------------------------------------------------------------------- */
1712 /* Function:     out32 */
1713 /* Description:  Output 32 bits */
1714 /*------------------------------------------------------------------------------- */
1715         .globl  out32
1716 out32:
1717         stw     r4,0x0000(r3)
1718         blr
1719
1720 /*------------------------------------------------------------------------------- */
1721 /* Function:     in32 */
1722 /* Description:  Input 32 bits */
1723 /*------------------------------------------------------------------------------- */
1724         .globl  in32
1725 in32:
1726         lwz     3,0x0000(3)
1727         blr
1728
1729 /**************************************************************************/
1730 /* PPC405EP specific stuff                                                */
1731 /**************************************************************************/
1732 #ifdef CONFIG_405EP
1733 ppc405ep_init:
1734
1735 #ifdef CONFIG_BUBINGA
1736         /*
1737          * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1738          * function) to support FPGA and NVRAM accesses below.
1739          */
1740
1741         lis     r3,GPIO0_OSRH@h         /* config GPIO output select */
1742         ori     r3,r3,GPIO0_OSRH@l
1743         lis     r4,CFG_GPIO0_OSRH@h
1744         ori     r4,r4,CFG_GPIO0_OSRH@l
1745         stw     r4,0(r3)
1746         lis     r3,GPIO0_OSRL@h
1747         ori     r3,r3,GPIO0_OSRL@l
1748         lis     r4,CFG_GPIO0_OSRL@h
1749         ori     r4,r4,CFG_GPIO0_OSRL@l
1750         stw     r4,0(r3)
1751
1752         lis     r3,GPIO0_ISR1H@h        /* config GPIO input select */
1753         ori     r3,r3,GPIO0_ISR1H@l
1754         lis     r4,CFG_GPIO0_ISR1H@h
1755         ori     r4,r4,CFG_GPIO0_ISR1H@l
1756         stw     r4,0(r3)
1757         lis     r3,GPIO0_ISR1L@h
1758         ori     r3,r3,GPIO0_ISR1L@l
1759         lis     r4,CFG_GPIO0_ISR1L@h
1760         ori     r4,r4,CFG_GPIO0_ISR1L@l
1761         stw     r4,0(r3)
1762
1763         lis     r3,GPIO0_TSRH@h         /* config GPIO three-state select */
1764         ori     r3,r3,GPIO0_TSRH@l
1765         lis     r4,CFG_GPIO0_TSRH@h
1766         ori     r4,r4,CFG_GPIO0_TSRH@l
1767         stw     r4,0(r3)
1768         lis     r3,GPIO0_TSRL@h
1769         ori     r3,r3,GPIO0_TSRL@l
1770         lis     r4,CFG_GPIO0_TSRL@h
1771         ori     r4,r4,CFG_GPIO0_TSRL@l
1772         stw     r4,0(r3)
1773
1774         lis     r3,GPIO0_TCR@h          /* config GPIO driver output enables */
1775         ori     r3,r3,GPIO0_TCR@l
1776         lis     r4,CFG_GPIO0_TCR@h
1777         ori     r4,r4,CFG_GPIO0_TCR@l
1778         stw     r4,0(r3)
1779
1780         li      r3,pb1ap                /* program EBC bank 1 for RTC access */
1781         mtdcr   ebccfga,r3
1782         lis     r3,CFG_EBC_PB1AP@h
1783         ori     r3,r3,CFG_EBC_PB1AP@l
1784         mtdcr   ebccfgd,r3
1785         li      r3,pb1cr
1786         mtdcr   ebccfga,r3
1787         lis     r3,CFG_EBC_PB1CR@h
1788         ori     r3,r3,CFG_EBC_PB1CR@l
1789         mtdcr   ebccfgd,r3
1790
1791         li      r3,pb1ap                /* program EBC bank 1 for RTC access */
1792         mtdcr   ebccfga,r3
1793         lis     r3,CFG_EBC_PB1AP@h
1794         ori     r3,r3,CFG_EBC_PB1AP@l
1795         mtdcr   ebccfgd,r3
1796         li      r3,pb1cr
1797         mtdcr   ebccfga,r3
1798         lis     r3,CFG_EBC_PB1CR@h
1799         ori     r3,r3,CFG_EBC_PB1CR@l
1800         mtdcr   ebccfgd,r3
1801
1802         li      r3,pb4ap                /* program EBC bank 4 for FPGA access */
1803         mtdcr   ebccfga,r3
1804         lis     r3,CFG_EBC_PB4AP@h
1805         ori     r3,r3,CFG_EBC_PB4AP@l
1806         mtdcr   ebccfgd,r3
1807         li      r3,pb4cr
1808         mtdcr   ebccfga,r3
1809         lis     r3,CFG_EBC_PB4CR@h
1810         ori     r3,r3,CFG_EBC_PB4CR@l
1811         mtdcr   ebccfgd,r3
1812 #endif
1813
1814         /*
1815         !-----------------------------------------------------------------------
1816         ! Check to see if chip is in bypass mode.
1817         ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1818         ! CPU reset   Otherwise, skip this step and keep going.
1819         ! Note:  Running BIOS in bypass mode is not supported since PLB speed
1820         !        will not be fast enough for the SDRAM (min 66MHz)
1821         !-----------------------------------------------------------------------
1822         */
1823         mfdcr   r5, CPC0_PLLMR1
1824         rlwinm  r4,r5,1,0x1            /* get system clock source (SSCS) */
1825         cmpi    cr0,0,r4,0x1
1826
1827         beq    pll_done                   /* if SSCS =b'1' then PLL has */
1828                                           /* already been set */
1829                                           /* and CPU has been reset */
1830                                           /* so skip to next section */
1831
1832 #ifdef CONFIG_BUBINGA
1833         /*
1834         !-----------------------------------------------------------------------
1835         ! Read NVRAM to get value to write in PLLMR.
1836         ! If value has not been correctly saved, write default value
1837         ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1838         ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1839         !
1840         ! WARNING:  This code assumes the first three words in the nvram_t
1841         !           structure in openbios.h.  Changing the beginning of
1842         !           the structure will break this code.
1843         !
1844         !-----------------------------------------------------------------------
1845         */
1846         addis   r3,0,NVRAM_BASE@h
1847         addi    r3,r3,NVRAM_BASE@l
1848
1849         lwz     r4, 0(r3)
1850         addis   r5,0,NVRVFY1@h
1851         addi    r5,r5,NVRVFY1@l
1852         cmp     cr0,0,r4,r5            /* Compare 1st NVRAM Magic number*/
1853         bne     ..no_pllset
1854         addi    r3,r3,4
1855         lwz     r4, 0(r3)
1856         addis   r5,0,NVRVFY2@h
1857         addi    r5,r5,NVRVFY2@l
1858         cmp     cr0,0,r4,r5            /* Compare 2 NVRAM Magic number */
1859         bne     ..no_pllset
1860         addi    r3,r3,8                 /* Skip over conf_size */
1861         lwz     r4, 4(r3)               /* Load PLLMR1 value from NVRAM */
1862         lwz     r3, 0(r3)               /* Load PLLMR0 value from NVRAM */
1863         rlwinm  r5,r4,1,0x1             /* get system clock source (SSCS) */
1864         cmpi     cr0,0,r5,1             /* See if PLL is locked */
1865         beq     pll_write
1866 ..no_pllset:
1867 #endif /* CONFIG_BUBINGA */
1868
1869 #ifdef CONFIG_TAIHU
1870         mfdcr   r4, CPC0_BOOT
1871         andi.   r5, r4, CPC0_BOOT_SEP@l
1872         bne     strap_1                 /* serial eeprom present */
1873         addis   r5,0,CPLD_REG0_ADDR@h
1874         ori     r5,r5,CPLD_REG0_ADDR@l
1875         andi.   r5, r5, 0x10
1876         bne     _pci_66mhz
1877 #endif /* CONFIG_TAIHU */
1878
1879 #if defined(CONFIG_ZEUS)
1880         mfdcr   r4, CPC0_BOOT
1881         andi.   r5, r4, CPC0_BOOT_SEP@l
1882         bne     strap_1         /* serial eeprom present */
1883         lis     r3,0x0000
1884         addi    r3,r3,0x3030
1885         lis     r4,0x8042
1886         addi    r4,r4,0x223e
1887         b       1f
1888 strap_1:
1889         mfdcr   r3, CPC0_PLLMR0
1890         mfdcr   r4, CPC0_PLLMR1
1891         b       1f
1892 #endif
1893
1894         addis   r3,0,PLLMR0_DEFAULT@h       /* PLLMR0 default value */
1895         ori     r3,r3,PLLMR0_DEFAULT@l     /* */
1896         addis   r4,0,PLLMR1_DEFAULT@h       /* PLLMR1 default value */
1897         ori     r4,r4,PLLMR1_DEFAULT@l     /* */
1898
1899 #ifdef CONFIG_TAIHU
1900         b       1f
1901 _pci_66mhz:
1902         addis   r3,0,PLLMR0_DEFAULT_PCI66@h
1903         ori     r3,r3,PLLMR0_DEFAULT_PCI66@l
1904         addis   r4,0,PLLMR1_DEFAULT_PCI66@h
1905         ori     r4,r4,PLLMR1_DEFAULT_PCI66@l
1906         b       1f
1907 strap_1:
1908         mfdcr   r3, CPC0_PLLMR0
1909         mfdcr   r4, CPC0_PLLMR1
1910 #endif /* CONFIG_TAIHU */
1911
1912 1:
1913         b       pll_write                 /* Write the CPC0_PLLMR with new value */
1914
1915 pll_done:
1916         /*
1917         !-----------------------------------------------------------------------
1918         ! Clear Soft Reset Register
1919         ! This is needed to enable PCI if not booting from serial EPROM
1920         !-----------------------------------------------------------------------
1921                 */
1922         addi    r3, 0, 0x0
1923         mtdcr   CPC0_SRR, r3
1924
1925         addis    r3,0,0x0010
1926         mtctr   r3
1927 pci_wait:
1928         bdnz    pci_wait
1929
1930         blr                               /* return to main code */
1931
1932 /*
1933 !-----------------------------------------------------------------------------
1934 ! Function:     pll_write
1935 ! Description:  Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1936 !               That is:
1937 !                         1.  Pll is first disabled (de-activated by putting in bypass mode)
1938 !                         2.  PLL is reset
1939 !                         3.  Clock dividers are set while PLL is held in reset and bypassed
1940 !                         4.  PLL Reset is cleared
1941 !                         5.  Wait 100us for PLL to lock
1942 !                         6.  A core reset is performed
1943 ! Input: r3 = Value to write to CPC0_PLLMR0
1944 ! Input: r4 = Value to write to CPC0_PLLMR1
1945 ! Output r3 = none
1946 !-----------------------------------------------------------------------------
1947 */
1948 pll_write:
1949         mfdcr  r5, CPC0_UCR
1950         andis. r5,r5,0xFFFF
1951         ori    r5,r5,0x0101              /* Stop the UART clocks */
1952         mtdcr  CPC0_UCR,r5               /* Before changing PLL */
1953
1954         mfdcr  r5, CPC0_PLLMR1
1955         rlwinm r5,r5,0,0x7FFFFFFF        /* Disable PLL */
1956         mtdcr   CPC0_PLLMR1,r5
1957         oris   r5,r5,0x4000              /* Set PLL Reset */
1958         mtdcr   CPC0_PLLMR1,r5
1959
1960         mtdcr   CPC0_PLLMR0,r3           /* Set clock dividers */
1961         rlwinm r5,r4,0,0x3FFFFFFF        /* Reset & Bypass new PLL dividers */
1962         oris   r5,r5,0x4000              /* Set PLL Reset */
1963         mtdcr   CPC0_PLLMR1,r5           /* Set clock dividers */
1964         rlwinm r5,r5,0,0xBFFFFFFF        /* Clear PLL Reset */
1965         mtdcr   CPC0_PLLMR1,r5
1966
1967                 /*
1968         ! Wait min of 100us for PLL to lock.
1969         ! See CMOS 27E databook for more info.
1970         ! At 200MHz, that means waiting 20,000 instructions
1971                  */
1972         addi    r3,0,20000              /* 2000 = 0x4e20 */
1973         mtctr   r3
1974 pll_wait:
1975         bdnz    pll_wait
1976
1977         oris   r5,r5,0x8000             /* Enable PLL */
1978         mtdcr   CPC0_PLLMR1,r5          /* Engage */
1979
1980         /*
1981          * Reset CPU to guarantee timings are OK
1982          * Not sure if this is needed...
1983          */
1984         addis r3,0,0x1000
1985         mtspr dbcr0,r3               /* This will cause a CPU core reset, and */
1986                                      /* execution will continue from the poweron */
1987                                      /* vector of 0xfffffffc */
1988 #endif /* CONFIG_405EP */
1989
1990 #if defined(CONFIG_440)
1991 /*----------------------------------------------------------------------------+
1992 | mttlb3.
1993 +----------------------------------------------------------------------------*/
1994         function_prolog(mttlb3)
1995         TLBWE(4,3,2)
1996         blr
1997         function_epilog(mttlb3)
1998
1999 /*----------------------------------------------------------------------------+
2000 | mftlb3.
2001 +----------------------------------------------------------------------------*/
2002         function_prolog(mftlb3)
2003         TLBRE(3,3,2)
2004         blr
2005         function_epilog(mftlb3)
2006
2007 /*----------------------------------------------------------------------------+
2008 | mttlb2.
2009 +----------------------------------------------------------------------------*/
2010         function_prolog(mttlb2)
2011         TLBWE(4,3,1)
2012         blr
2013         function_epilog(mttlb2)
2014
2015 /*----------------------------------------------------------------------------+
2016 | mftlb2.
2017 +----------------------------------------------------------------------------*/
2018         function_prolog(mftlb2)
2019         TLBRE(3,3,1)
2020         blr
2021         function_epilog(mftlb2)
2022
2023 /*----------------------------------------------------------------------------+
2024 | mttlb1.
2025 +----------------------------------------------------------------------------*/
2026         function_prolog(mttlb1)
2027         TLBWE(4,3,0)
2028         blr
2029         function_epilog(mttlb1)
2030
2031 /*----------------------------------------------------------------------------+
2032 | mftlb1.
2033 +----------------------------------------------------------------------------*/
2034         function_prolog(mftlb1)
2035         TLBRE(3,3,0)
2036         blr
2037         function_epilog(mftlb1)
2038 #endif /* CONFIG_440 */