]>
git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/pxa/cpu.c
d1551ddc386c7d18b88faa406cae83cbc33a0f8f
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/pxa-regs.h>
40 * setup up stacks if necessary
43 DECLARE_GLOBAL_DATA_PTR
;
45 IRQ_STACK_START
= _armboot_start
- CFG_MALLOC_LEN
- CFG_GBL_DATA_SIZE
- 4;
46 FIQ_STACK_START
= IRQ_STACK_START
- CONFIG_STACKSIZE_IRQ
;
51 int cleanup_before_linux (void)
54 * this function is called just before we call linux
55 * it prepares the processor for linux
57 * just disable everything that can disturb booting linux
62 disable_interrupts ();
64 /* turn off I-cache */
65 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i
));
67 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i
));
70 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i
));
75 int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
77 printf ("resetting ...\n");
79 udelay (50000); /* wait 50 ms */
80 disable_interrupts ();
88 void icache_enable (void)
92 /* read control register */
93 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i
));
98 /* write back to control register */
99 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i
));
102 void icache_disable (void)
106 /* read control register */
107 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i
));
112 /* write back to control register */
113 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i
));
116 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i
));
119 int icache_status (void)
123 /* read control register */
124 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i
));
130 /* we will never enable dcache, because we have to setup MMU first */
131 void dcache_enable (void)
136 void dcache_disable (void)
141 int dcache_status (void)
143 return 0; /* always off */
146 void set_GPIO_mode(int gpio_mode
)
148 int gpio
= gpio_mode
& GPIO_MD_MASK_NR
;
149 int fn
= (gpio_mode
& GPIO_MD_MASK_FN
) >> 8;
152 if (gpio_mode
& GPIO_MD_MASK_DIR
)
154 GPDR(gpio
) |= GPIO_bit(gpio
);
158 GPDR(gpio
) &= ~GPIO_bit(gpio
);
160 gafr
= GAFR(gpio
) & ~(0x3 << (((gpio
) & 0xf)*2));
161 GAFR(gpio
) = gafr
| (fn
<< (((gpio
) & 0xf)*2));