cpu/pxa/cpu.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8  * Alex Zuepke <azu@sysgo.de>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * CPU specific code
  31  */
  32
  33 #include <common.h>
  34 #include <command.h>
  35 #include <asm/arch/pxa-regs.h>
  36
  37 int cpu_init (void)
  38 {
  39         /*
  40          * setup up stacks if necessary
  41          */
  42 #ifdef CONFIG_USE_IRQ
  43         DECLARE_GLOBAL_DATA_PTR;
  44
  45         IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
  46         FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
  47 #endif
  48         return 0;
  49 }
  50
  51 int cleanup_before_linux (void)
  52 {
  53         /*
  54          * this function is called just before we call linux
  55          * it prepares the processor for linux
  56          *
  57          * just disable everything that can disturb booting linux
  58          */
  59
  60         unsigned long i;
  61
  62         disable_interrupts ();
  63
  64         /* turn off I-cache */
  65         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
  66         i &= ~0x1000;
  67         asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
  68
  69         /* flush I-cache */
  70         asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
  71
  72         return (0);
  73 }
  74
  75 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  76 {
  77         printf ("resetting ...\n");
  78
  79         udelay (50000);                         /* wait 50 ms */
  80         disable_interrupts ();
  81         reset_cpu (0);
  82
  83         /*NOTREACHED*/
  84         return (0);
  85 }
  86
  87 /* taken from blob */
  88 void icache_enable (void)
  89 {
  90         register u32 i;
  91
  92         /* read control register */
  93         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
  94
  95         /* set i-cache */
  96         i |= 0x1000;
  97
  98         /* write back to control register */
  99         asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 100 }
 101
 102 void icache_disable (void)
 103 {
 104         register u32 i;
 105
 106         /* read control register */
 107         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 108
 109         /* clear i-cache */
 110         i &= ~0x1000;
 111
 112         /* write back to control register */
 113         asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 114
 115         /* flush i-cache */
 116         asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 117 }
 118
 119 int icache_status (void)
 120 {
 121         register u32 i;
 122
 123         /* read control register */
 124         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 125
 126         /* return bit */
 127         return (i & 0x1000);
 128 }
 129
 130 /* we will never enable dcache, because we have to setup MMU first */
 131 void dcache_enable (void)
 132 {
 133         return;
 134 }
 135
 136 void dcache_disable (void)
 137 {
 138         return;
 139 }
 140
 141 int dcache_status (void)
 142 {
 143         return 0;                                       /* always off */
 144 }
 145
 146 #ifndef CONFIG_CPU_MONAHANS
 147 void set_GPIO_mode(int gpio_mode)
 148 {
 149         int gpio = gpio_mode & GPIO_MD_MASK_NR;
 150         int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
 151         int gafr;
 152
 153         if (gpio_mode & GPIO_MD_MASK_DIR)
 154         {
 155                 GPDR(gpio) |= GPIO_bit(gpio);
 156         }
 157         else
 158         {
 159                 GPDR(gpio) &= ~GPIO_bit(gpio);
 160         }
 161         gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
 162         GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
 163 }
 164 #endif /* CONFIG_CPU_MONAHANS */