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This patch adds little-endian mode support to PPC emulation.
[thirdparty/qemu.git] / cpu-exec.c
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50
51 /* exit the current TB from a signal handler. The host registers are
52 restored in a state compatible with the CPU emulator
53 */
54 void cpu_resume_from_signal(CPUState *env1, void *puc)
55 {
56 #if !defined(CONFIG_SOFTMMU)
57 struct ucontext *uc = puc;
58 #endif
59
60 env = env1;
61
62 /* XXX: restore cpu registers saved in host registers */
63
64 #if !defined(CONFIG_SOFTMMU)
65 if (puc) {
66 /* XXX: use siglongjmp ? */
67 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
68 }
69 #endif
70 longjmp(env->jmp_env, 1);
71 }
72
73 /* main execution loop */
74
75 int cpu_exec(CPUState *env1)
76 {
77 int saved_T0, saved_T1, saved_T2;
78 CPUState *saved_env;
79 #ifdef reg_EAX
80 int saved_EAX;
81 #endif
82 #ifdef reg_ECX
83 int saved_ECX;
84 #endif
85 #ifdef reg_EDX
86 int saved_EDX;
87 #endif
88 #ifdef reg_EBX
89 int saved_EBX;
90 #endif
91 #ifdef reg_ESP
92 int saved_ESP;
93 #endif
94 #ifdef reg_EBP
95 int saved_EBP;
96 #endif
97 #ifdef reg_ESI
98 int saved_ESI;
99 #endif
100 #ifdef reg_EDI
101 int saved_EDI;
102 #endif
103 #ifdef __sparc__
104 int saved_i7, tmp_T0;
105 #endif
106 int code_gen_size, ret, interrupt_request;
107 void (*gen_func)(void);
108 TranslationBlock *tb, **ptb;
109 target_ulong cs_base, pc;
110 uint8_t *tc_ptr;
111 unsigned int flags;
112
113 /* first we save global registers */
114 saved_env = env;
115 env = env1;
116 saved_T0 = T0;
117 saved_T1 = T1;
118 saved_T2 = T2;
119 #ifdef __sparc__
120 /* we also save i7 because longjmp may not restore it */
121 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
122 #endif
123
124 #if defined(TARGET_I386)
125 #ifdef reg_EAX
126 saved_EAX = EAX;
127 #endif
128 #ifdef reg_ECX
129 saved_ECX = ECX;
130 #endif
131 #ifdef reg_EDX
132 saved_EDX = EDX;
133 #endif
134 #ifdef reg_EBX
135 saved_EBX = EBX;
136 #endif
137 #ifdef reg_ESP
138 saved_ESP = ESP;
139 #endif
140 #ifdef reg_EBP
141 saved_EBP = EBP;
142 #endif
143 #ifdef reg_ESI
144 saved_ESI = ESI;
145 #endif
146 #ifdef reg_EDI
147 saved_EDI = EDI;
148 #endif
149
150 env_to_regs();
151 /* put eflags in CPU temporary format */
152 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
153 DF = 1 - (2 * ((env->eflags >> 10) & 1));
154 CC_OP = CC_OP_EFLAGS;
155 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
156 #elif defined(TARGET_ARM)
157 {
158 unsigned int psr;
159 psr = env->cpsr;
160 env->CF = (psr >> 29) & 1;
161 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
162 env->VF = (psr << 3) & 0x80000000;
163 env->QF = (psr >> 27) & 1;
164 env->cpsr = psr & ~CACHED_CPSR_BITS;
165 }
166 #elif defined(TARGET_SPARC)
167 #elif defined(TARGET_PPC)
168 #else
169 #error unsupported target CPU
170 #endif
171 env->exception_index = -1;
172
173 /* prepare setjmp context for exception handling */
174 for(;;) {
175 if (setjmp(env->jmp_env) == 0) {
176 env->current_tb = NULL;
177 /* if an exception is pending, we execute it here */
178 if (env->exception_index >= 0) {
179 if (env->exception_index >= EXCP_INTERRUPT) {
180 /* exit request from the cpu execution loop */
181 ret = env->exception_index;
182 break;
183 } else if (env->user_mode_only) {
184 /* if user mode only, we simulate a fake exception
185 which will be hanlded outside the cpu execution
186 loop */
187 #if defined(TARGET_I386)
188 do_interrupt_user(env->exception_index,
189 env->exception_is_int,
190 env->error_code,
191 env->exception_next_eip);
192 #endif
193 ret = env->exception_index;
194 break;
195 } else {
196 #if defined(TARGET_I386)
197 /* simulate a real cpu exception. On i386, it can
198 trigger new exceptions, but we do not handle
199 double or triple faults yet. */
200 do_interrupt(env->exception_index,
201 env->exception_is_int,
202 env->error_code,
203 env->exception_next_eip, 0);
204 #elif defined(TARGET_PPC)
205 do_interrupt(env);
206 #elif defined(TARGET_SPARC)
207 do_interrupt(env->exception_index);
208 #endif
209 }
210 env->exception_index = -1;
211 }
212 #ifdef USE_KQEMU
213 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
214 int ret;
215 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
216 ret = kqemu_cpu_exec(env);
217 /* put eflags in CPU temporary format */
218 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
219 DF = 1 - (2 * ((env->eflags >> 10) & 1));
220 CC_OP = CC_OP_EFLAGS;
221 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
222 if (ret == 1) {
223 /* exception */
224 longjmp(env->jmp_env, 1);
225 } else if (ret == 2) {
226 /* softmmu execution needed */
227 } else {
228 if (env->interrupt_request != 0) {
229 /* hardware interrupt will be executed just after */
230 } else {
231 /* otherwise, we restart */
232 longjmp(env->jmp_env, 1);
233 }
234 }
235 }
236 #endif
237
238 T0 = 0; /* force lookup of first TB */
239 for(;;) {
240 #ifdef __sparc__
241 /* g1 can be modified by some libc? functions */
242 tmp_T0 = T0;
243 #endif
244 interrupt_request = env->interrupt_request;
245 if (__builtin_expect(interrupt_request, 0)) {
246 #if defined(TARGET_I386)
247 /* if hardware interrupt pending, we execute it */
248 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
249 (env->eflags & IF_MASK) &&
250 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
251 int intno;
252 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
253 intno = cpu_get_pic_interrupt(env);
254 if (loglevel & CPU_LOG_TB_IN_ASM) {
255 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
256 }
257 do_interrupt(intno, 0, 0, 0, 1);
258 /* ensure that no TB jump will be modified as
259 the program flow was changed */
260 #ifdef __sparc__
261 tmp_T0 = 0;
262 #else
263 T0 = 0;
264 #endif
265 }
266 #elif defined(TARGET_PPC)
267 #if 0
268 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
269 cpu_ppc_reset(env);
270 }
271 #endif
272 if (msr_ee != 0) {
273 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
274 /* Raise it */
275 env->exception_index = EXCP_EXTERNAL;
276 env->error_code = 0;
277 do_interrupt(env);
278 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
279 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
280 /* Raise it */
281 env->exception_index = EXCP_DECR;
282 env->error_code = 0;
283 do_interrupt(env);
284 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
285 }
286 }
287 #elif defined(TARGET_SPARC)
288 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
289 (env->psret != 0)) {
290 int pil = env->interrupt_index & 15;
291 int type = env->interrupt_index & 0xf0;
292
293 if (((type == TT_EXTINT) &&
294 (pil == 15 || pil > env->psrpil)) ||
295 type != TT_EXTINT) {
296 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
297 do_interrupt(env->interrupt_index);
298 env->interrupt_index = 0;
299 }
300 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
301 //do_interrupt(0, 0, 0, 0, 0);
302 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
303 }
304 #endif
305 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
306 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
307 /* ensure that no TB jump will be modified as
308 the program flow was changed */
309 #ifdef __sparc__
310 tmp_T0 = 0;
311 #else
312 T0 = 0;
313 #endif
314 }
315 if (interrupt_request & CPU_INTERRUPT_EXIT) {
316 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
317 env->exception_index = EXCP_INTERRUPT;
318 cpu_loop_exit();
319 }
320 }
321 #ifdef DEBUG_EXEC
322 if ((loglevel & CPU_LOG_EXEC)) {
323 #if defined(TARGET_I386)
324 /* restore flags in standard format */
325 env->regs[R_EAX] = EAX;
326 env->regs[R_EBX] = EBX;
327 env->regs[R_ECX] = ECX;
328 env->regs[R_EDX] = EDX;
329 env->regs[R_ESI] = ESI;
330 env->regs[R_EDI] = EDI;
331 env->regs[R_EBP] = EBP;
332 env->regs[R_ESP] = ESP;
333 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
334 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
335 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
336 #elif defined(TARGET_ARM)
337 env->cpsr = compute_cpsr();
338 cpu_dump_state(env, logfile, fprintf, 0);
339 env->cpsr &= ~CACHED_CPSR_BITS;
340 #elif defined(TARGET_SPARC)
341 cpu_dump_state (env, logfile, fprintf, 0);
342 #elif defined(TARGET_PPC)
343 cpu_dump_state(env, logfile, fprintf, 0);
344 #else
345 #error unsupported target CPU
346 #endif
347 }
348 #endif
349 /* we record a subset of the CPU state. It will
350 always be the same before a given translated block
351 is executed. */
352 #if defined(TARGET_I386)
353 flags = env->hflags;
354 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
355 cs_base = env->segs[R_CS].base;
356 pc = cs_base + env->eip;
357 #elif defined(TARGET_ARM)
358 flags = env->thumb | (env->vfp.vec_len << 1)
359 | (env->vfp.vec_stride << 4);
360 cs_base = 0;
361 pc = env->regs[15];
362 #elif defined(TARGET_SPARC)
363 flags = 0;
364 cs_base = env->npc;
365 pc = env->pc;
366 #elif defined(TARGET_PPC)
367 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
368 (msr_se << MSR_SE) | (msr_le << MSR_LE);
369 cs_base = 0;
370 pc = env->nip;
371 #else
372 #error unsupported CPU
373 #endif
374 tb = tb_find(&ptb, pc, cs_base,
375 flags);
376 if (!tb) {
377 TranslationBlock **ptb1;
378 unsigned int h;
379 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
380
381
382 spin_lock(&tb_lock);
383
384 tb_invalidated_flag = 0;
385
386 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
387
388 /* find translated block using physical mappings */
389 phys_pc = get_phys_addr_code(env, pc);
390 phys_page1 = phys_pc & TARGET_PAGE_MASK;
391 phys_page2 = -1;
392 h = tb_phys_hash_func(phys_pc);
393 ptb1 = &tb_phys_hash[h];
394 for(;;) {
395 tb = *ptb1;
396 if (!tb)
397 goto not_found;
398 if (tb->pc == pc &&
399 tb->page_addr[0] == phys_page1 &&
400 tb->cs_base == cs_base &&
401 tb->flags == flags) {
402 /* check next page if needed */
403 if (tb->page_addr[1] != -1) {
404 virt_page2 = (pc & TARGET_PAGE_MASK) +
405 TARGET_PAGE_SIZE;
406 phys_page2 = get_phys_addr_code(env, virt_page2);
407 if (tb->page_addr[1] == phys_page2)
408 goto found;
409 } else {
410 goto found;
411 }
412 }
413 ptb1 = &tb->phys_hash_next;
414 }
415 not_found:
416 /* if no translated code available, then translate it now */
417 tb = tb_alloc(pc);
418 if (!tb) {
419 /* flush must be done */
420 tb_flush(env);
421 /* cannot fail at this point */
422 tb = tb_alloc(pc);
423 /* don't forget to invalidate previous TB info */
424 ptb = &tb_hash[tb_hash_func(pc)];
425 T0 = 0;
426 }
427 tc_ptr = code_gen_ptr;
428 tb->tc_ptr = tc_ptr;
429 tb->cs_base = cs_base;
430 tb->flags = flags;
431 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
432 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
433
434 /* check next page if needed */
435 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
436 phys_page2 = -1;
437 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
438 phys_page2 = get_phys_addr_code(env, virt_page2);
439 }
440 tb_link_phys(tb, phys_pc, phys_page2);
441
442 found:
443 if (tb_invalidated_flag) {
444 /* as some TB could have been invalidated because
445 of memory exceptions while generating the code, we
446 must recompute the hash index here */
447 ptb = &tb_hash[tb_hash_func(pc)];
448 while (*ptb != NULL)
449 ptb = &(*ptb)->hash_next;
450 T0 = 0;
451 }
452 /* we add the TB in the virtual pc hash table */
453 *ptb = tb;
454 tb->hash_next = NULL;
455 tb_link(tb);
456 spin_unlock(&tb_lock);
457 }
458 #ifdef DEBUG_EXEC
459 if ((loglevel & CPU_LOG_EXEC)) {
460 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
461 (long)tb->tc_ptr, tb->pc,
462 lookup_symbol(tb->pc));
463 }
464 #endif
465 #ifdef __sparc__
466 T0 = tmp_T0;
467 #endif
468 /* see if we can patch the calling TB. */
469 {
470 if (T0 != 0
471 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
472 && (tb->cflags & CF_CODE_COPY) ==
473 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
474 #endif
475 ) {
476 spin_lock(&tb_lock);
477 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
478 #if defined(USE_CODE_COPY)
479 /* propagates the FP use info */
480 ((TranslationBlock *)(T0 & ~3))->cflags |=
481 (tb->cflags & CF_FP_USED);
482 #endif
483 spin_unlock(&tb_lock);
484 }
485 }
486 tc_ptr = tb->tc_ptr;
487 env->current_tb = tb;
488 /* execute the generated code */
489 gen_func = (void *)tc_ptr;
490 #if defined(__sparc__)
491 __asm__ __volatile__("call %0\n\t"
492 "mov %%o7,%%i0"
493 : /* no outputs */
494 : "r" (gen_func)
495 : "i0", "i1", "i2", "i3", "i4", "i5");
496 #elif defined(__arm__)
497 asm volatile ("mov pc, %0\n\t"
498 ".global exec_loop\n\t"
499 "exec_loop:\n\t"
500 : /* no outputs */
501 : "r" (gen_func)
502 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
503 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
504 {
505 if (!(tb->cflags & CF_CODE_COPY)) {
506 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
507 save_native_fp_state(env);
508 }
509 gen_func();
510 } else {
511 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
512 restore_native_fp_state(env);
513 }
514 /* we work with native eflags */
515 CC_SRC = cc_table[CC_OP].compute_all();
516 CC_OP = CC_OP_EFLAGS;
517 asm(".globl exec_loop\n"
518 "\n"
519 "debug1:\n"
520 " pushl %%ebp\n"
521 " fs movl %10, %9\n"
522 " fs movl %11, %%eax\n"
523 " andl $0x400, %%eax\n"
524 " fs orl %8, %%eax\n"
525 " pushl %%eax\n"
526 " popf\n"
527 " fs movl %%esp, %12\n"
528 " fs movl %0, %%eax\n"
529 " fs movl %1, %%ecx\n"
530 " fs movl %2, %%edx\n"
531 " fs movl %3, %%ebx\n"
532 " fs movl %4, %%esp\n"
533 " fs movl %5, %%ebp\n"
534 " fs movl %6, %%esi\n"
535 " fs movl %7, %%edi\n"
536 " fs jmp *%9\n"
537 "exec_loop:\n"
538 " fs movl %%esp, %4\n"
539 " fs movl %12, %%esp\n"
540 " fs movl %%eax, %0\n"
541 " fs movl %%ecx, %1\n"
542 " fs movl %%edx, %2\n"
543 " fs movl %%ebx, %3\n"
544 " fs movl %%ebp, %5\n"
545 " fs movl %%esi, %6\n"
546 " fs movl %%edi, %7\n"
547 " pushf\n"
548 " popl %%eax\n"
549 " movl %%eax, %%ecx\n"
550 " andl $0x400, %%ecx\n"
551 " shrl $9, %%ecx\n"
552 " andl $0x8d5, %%eax\n"
553 " fs movl %%eax, %8\n"
554 " movl $1, %%eax\n"
555 " subl %%ecx, %%eax\n"
556 " fs movl %%eax, %11\n"
557 " fs movl %9, %%ebx\n" /* get T0 value */
558 " popl %%ebp\n"
559 :
560 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
561 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
562 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
563 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
564 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
565 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
566 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
567 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
568 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
569 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
570 "a" (gen_func),
571 "m" (*(uint8_t *)offsetof(CPUState, df)),
572 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
573 : "%ecx", "%edx"
574 );
575 }
576 }
577 #elif defined(__ia64)
578 struct fptr {
579 void *ip;
580 void *gp;
581 } fp;
582
583 fp.ip = tc_ptr;
584 fp.gp = code_gen_buffer + 2 * (1 << 20);
585 (*(void (*)(void)) &fp)();
586 #else
587 gen_func();
588 #endif
589 env->current_tb = NULL;
590 /* reset soft MMU for next block (it can currently
591 only be set by a memory fault) */
592 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
593 if (env->hflags & HF_SOFTMMU_MASK) {
594 env->hflags &= ~HF_SOFTMMU_MASK;
595 /* do not allow linking to another block */
596 T0 = 0;
597 }
598 #endif
599 }
600 } else {
601 env_to_regs();
602 }
603 } /* for(;;) */
604
605
606 #if defined(TARGET_I386)
607 #if defined(USE_CODE_COPY)
608 if (env->native_fp_regs) {
609 save_native_fp_state(env);
610 }
611 #endif
612 /* restore flags in standard format */
613 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
614
615 /* restore global registers */
616 #ifdef reg_EAX
617 EAX = saved_EAX;
618 #endif
619 #ifdef reg_ECX
620 ECX = saved_ECX;
621 #endif
622 #ifdef reg_EDX
623 EDX = saved_EDX;
624 #endif
625 #ifdef reg_EBX
626 EBX = saved_EBX;
627 #endif
628 #ifdef reg_ESP
629 ESP = saved_ESP;
630 #endif
631 #ifdef reg_EBP
632 EBP = saved_EBP;
633 #endif
634 #ifdef reg_ESI
635 ESI = saved_ESI;
636 #endif
637 #ifdef reg_EDI
638 EDI = saved_EDI;
639 #endif
640 #elif defined(TARGET_ARM)
641 env->cpsr = compute_cpsr();
642 /* XXX: Save/restore host fpu exception state?. */
643 #elif defined(TARGET_SPARC)
644 #elif defined(TARGET_PPC)
645 #else
646 #error unsupported target CPU
647 #endif
648 #ifdef __sparc__
649 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
650 #endif
651 T0 = saved_T0;
652 T1 = saved_T1;
653 T2 = saved_T2;
654 env = saved_env;
655 return ret;
656 }
657
658 /* must only be called from the generated code as an exception can be
659 generated */
660 void tb_invalidate_page_range(target_ulong start, target_ulong end)
661 {
662 /* XXX: cannot enable it yet because it yields to MMU exception
663 where NIP != read address on PowerPC */
664 #if 0
665 target_ulong phys_addr;
666 phys_addr = get_phys_addr_code(env, start);
667 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
668 #endif
669 }
670
671 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
672
673 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
674 {
675 CPUX86State *saved_env;
676
677 saved_env = env;
678 env = s;
679 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
680 selector &= 0xffff;
681 cpu_x86_load_seg_cache(env, seg_reg, selector,
682 (selector << 4), 0xffff, 0);
683 } else {
684 load_seg(seg_reg, selector);
685 }
686 env = saved_env;
687 }
688
689 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
690 {
691 CPUX86State *saved_env;
692
693 saved_env = env;
694 env = s;
695
696 helper_fsave((target_ulong)ptr, data32);
697
698 env = saved_env;
699 }
700
701 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
702 {
703 CPUX86State *saved_env;
704
705 saved_env = env;
706 env = s;
707
708 helper_frstor((target_ulong)ptr, data32);
709
710 env = saved_env;
711 }
712
713 #endif /* TARGET_I386 */
714
715 #if !defined(CONFIG_SOFTMMU)
716
717 #if defined(TARGET_I386)
718
719 /* 'pc' is the host PC at which the exception was raised. 'address' is
720 the effective address of the memory exception. 'is_write' is 1 if a
721 write caused the exception and otherwise 0'. 'old_set' is the
722 signal set which should be restored */
723 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
724 int is_write, sigset_t *old_set,
725 void *puc)
726 {
727 TranslationBlock *tb;
728 int ret;
729
730 if (cpu_single_env)
731 env = cpu_single_env; /* XXX: find a correct solution for multithread */
732 #if defined(DEBUG_SIGNAL)
733 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
734 pc, address, is_write, *(unsigned long *)old_set);
735 #endif
736 /* XXX: locking issue */
737 if (is_write && page_unprotect(address, pc, puc)) {
738 return 1;
739 }
740
741 /* see if it is an MMU fault */
742 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
743 ((env->hflags & HF_CPL_MASK) == 3), 0);
744 if (ret < 0)
745 return 0; /* not an MMU fault */
746 if (ret == 0)
747 return 1; /* the MMU fault was handled without causing real CPU fault */
748 /* now we have a real cpu fault */
749 tb = tb_find_pc(pc);
750 if (tb) {
751 /* the PC is inside the translated code. It means that we have
752 a virtual CPU fault */
753 cpu_restore_state(tb, env, pc, puc);
754 }
755 if (ret == 1) {
756 #if 0
757 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
758 env->eip, env->cr[2], env->error_code);
759 #endif
760 /* we restore the process signal mask as the sigreturn should
761 do it (XXX: use sigsetjmp) */
762 sigprocmask(SIG_SETMASK, old_set, NULL);
763 raise_exception_err(EXCP0E_PAGE, env->error_code);
764 } else {
765 /* activate soft MMU for this block */
766 env->hflags |= HF_SOFTMMU_MASK;
767 cpu_resume_from_signal(env, puc);
768 }
769 /* never comes here */
770 return 1;
771 }
772
773 #elif defined(TARGET_ARM)
774 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
775 int is_write, sigset_t *old_set,
776 void *puc)
777 {
778 TranslationBlock *tb;
779 int ret;
780
781 if (cpu_single_env)
782 env = cpu_single_env; /* XXX: find a correct solution for multithread */
783 #if defined(DEBUG_SIGNAL)
784 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
785 pc, address, is_write, *(unsigned long *)old_set);
786 #endif
787 /* XXX: locking issue */
788 if (is_write && page_unprotect(address, pc, puc)) {
789 return 1;
790 }
791 /* see if it is an MMU fault */
792 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
793 if (ret < 0)
794 return 0; /* not an MMU fault */
795 if (ret == 0)
796 return 1; /* the MMU fault was handled without causing real CPU fault */
797 /* now we have a real cpu fault */
798 tb = tb_find_pc(pc);
799 if (tb) {
800 /* the PC is inside the translated code. It means that we have
801 a virtual CPU fault */
802 cpu_restore_state(tb, env, pc, puc);
803 }
804 /* we restore the process signal mask as the sigreturn should
805 do it (XXX: use sigsetjmp) */
806 sigprocmask(SIG_SETMASK, old_set, NULL);
807 cpu_loop_exit();
808 }
809 #elif defined(TARGET_SPARC)
810 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
811 int is_write, sigset_t *old_set,
812 void *puc)
813 {
814 TranslationBlock *tb;
815 int ret;
816
817 if (cpu_single_env)
818 env = cpu_single_env; /* XXX: find a correct solution for multithread */
819 #if defined(DEBUG_SIGNAL)
820 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
821 pc, address, is_write, *(unsigned long *)old_set);
822 #endif
823 /* XXX: locking issue */
824 if (is_write && page_unprotect(address, pc, puc)) {
825 return 1;
826 }
827 /* see if it is an MMU fault */
828 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
829 if (ret < 0)
830 return 0; /* not an MMU fault */
831 if (ret == 0)
832 return 1; /* the MMU fault was handled without causing real CPU fault */
833 /* now we have a real cpu fault */
834 tb = tb_find_pc(pc);
835 if (tb) {
836 /* the PC is inside the translated code. It means that we have
837 a virtual CPU fault */
838 cpu_restore_state(tb, env, pc, puc);
839 }
840 /* we restore the process signal mask as the sigreturn should
841 do it (XXX: use sigsetjmp) */
842 sigprocmask(SIG_SETMASK, old_set, NULL);
843 cpu_loop_exit();
844 }
845 #elif defined (TARGET_PPC)
846 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
847 int is_write, sigset_t *old_set,
848 void *puc)
849 {
850 TranslationBlock *tb;
851 int ret;
852
853 if (cpu_single_env)
854 env = cpu_single_env; /* XXX: find a correct solution for multithread */
855 #if defined(DEBUG_SIGNAL)
856 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
857 pc, address, is_write, *(unsigned long *)old_set);
858 #endif
859 /* XXX: locking issue */
860 if (is_write && page_unprotect(address, pc, puc)) {
861 return 1;
862 }
863
864 /* see if it is an MMU fault */
865 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
866 if (ret < 0)
867 return 0; /* not an MMU fault */
868 if (ret == 0)
869 return 1; /* the MMU fault was handled without causing real CPU fault */
870
871 /* now we have a real cpu fault */
872 tb = tb_find_pc(pc);
873 if (tb) {
874 /* the PC is inside the translated code. It means that we have
875 a virtual CPU fault */
876 cpu_restore_state(tb, env, pc, puc);
877 }
878 if (ret == 1) {
879 #if 0
880 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
881 env->nip, env->error_code, tb);
882 #endif
883 /* we restore the process signal mask as the sigreturn should
884 do it (XXX: use sigsetjmp) */
885 sigprocmask(SIG_SETMASK, old_set, NULL);
886 do_raise_exception_err(env->exception_index, env->error_code);
887 } else {
888 /* activate soft MMU for this block */
889 cpu_resume_from_signal(env, puc);
890 }
891 /* never comes here */
892 return 1;
893 }
894 #else
895 #error unsupported target CPU
896 #endif
897
898 #if defined(__i386__)
899
900 #if defined(USE_CODE_COPY)
901 static void cpu_send_trap(unsigned long pc, int trap,
902 struct ucontext *uc)
903 {
904 TranslationBlock *tb;
905
906 if (cpu_single_env)
907 env = cpu_single_env; /* XXX: find a correct solution for multithread */
908 /* now we have a real cpu fault */
909 tb = tb_find_pc(pc);
910 if (tb) {
911 /* the PC is inside the translated code. It means that we have
912 a virtual CPU fault */
913 cpu_restore_state(tb, env, pc, uc);
914 }
915 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
916 raise_exception_err(trap, env->error_code);
917 }
918 #endif
919
920 int cpu_signal_handler(int host_signum, struct siginfo *info,
921 void *puc)
922 {
923 struct ucontext *uc = puc;
924 unsigned long pc;
925 int trapno;
926
927 #ifndef REG_EIP
928 /* for glibc 2.1 */
929 #define REG_EIP EIP
930 #define REG_ERR ERR
931 #define REG_TRAPNO TRAPNO
932 #endif
933 pc = uc->uc_mcontext.gregs[REG_EIP];
934 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
935 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
936 if (trapno == 0x00 || trapno == 0x05) {
937 /* send division by zero or bound exception */
938 cpu_send_trap(pc, trapno, uc);
939 return 1;
940 } else
941 #endif
942 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
943 trapno == 0xe ?
944 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
945 &uc->uc_sigmask, puc);
946 }
947
948 #elif defined(__x86_64__)
949
950 int cpu_signal_handler(int host_signum, struct siginfo *info,
951 void *puc)
952 {
953 struct ucontext *uc = puc;
954 unsigned long pc;
955
956 pc = uc->uc_mcontext.gregs[REG_RIP];
957 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
958 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
959 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
960 &uc->uc_sigmask, puc);
961 }
962
963 #elif defined(__powerpc__)
964
965 /***********************************************************************
966 * signal context platform-specific definitions
967 * From Wine
968 */
969 #ifdef linux
970 /* All Registers access - only for local access */
971 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
972 /* Gpr Registers access */
973 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
974 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
975 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
976 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
977 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
978 # define LR_sig(context) REG_sig(link, context) /* Link register */
979 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
980 /* Float Registers access */
981 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
982 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
983 /* Exception Registers access */
984 # define DAR_sig(context) REG_sig(dar, context)
985 # define DSISR_sig(context) REG_sig(dsisr, context)
986 # define TRAP_sig(context) REG_sig(trap, context)
987 #endif /* linux */
988
989 #ifdef __APPLE__
990 # include <sys/ucontext.h>
991 typedef struct ucontext SIGCONTEXT;
992 /* All Registers access - only for local access */
993 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
994 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
995 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
996 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
997 /* Gpr Registers access */
998 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
999 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1000 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1001 # define CTR_sig(context) REG_sig(ctr, context)
1002 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1003 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1004 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1005 /* Float Registers access */
1006 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1007 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1008 /* Exception Registers access */
1009 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1010 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1011 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1012 #endif /* __APPLE__ */
1013
1014 int cpu_signal_handler(int host_signum, struct siginfo *info,
1015 void *puc)
1016 {
1017 struct ucontext *uc = puc;
1018 unsigned long pc;
1019 int is_write;
1020
1021 pc = IAR_sig(uc);
1022 is_write = 0;
1023 #if 0
1024 /* ppc 4xx case */
1025 if (DSISR_sig(uc) & 0x00800000)
1026 is_write = 1;
1027 #else
1028 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1029 is_write = 1;
1030 #endif
1031 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1032 is_write, &uc->uc_sigmask, puc);
1033 }
1034
1035 #elif defined(__alpha__)
1036
1037 int cpu_signal_handler(int host_signum, struct siginfo *info,
1038 void *puc)
1039 {
1040 struct ucontext *uc = puc;
1041 uint32_t *pc = uc->uc_mcontext.sc_pc;
1042 uint32_t insn = *pc;
1043 int is_write = 0;
1044
1045 /* XXX: need kernel patch to get write flag faster */
1046 switch (insn >> 26) {
1047 case 0x0d: // stw
1048 case 0x0e: // stb
1049 case 0x0f: // stq_u
1050 case 0x24: // stf
1051 case 0x25: // stg
1052 case 0x26: // sts
1053 case 0x27: // stt
1054 case 0x2c: // stl
1055 case 0x2d: // stq
1056 case 0x2e: // stl_c
1057 case 0x2f: // stq_c
1058 is_write = 1;
1059 }
1060
1061 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1062 is_write, &uc->uc_sigmask, puc);
1063 }
1064 #elif defined(__sparc__)
1065
1066 int cpu_signal_handler(int host_signum, struct siginfo *info,
1067 void *puc)
1068 {
1069 uint32_t *regs = (uint32_t *)(info + 1);
1070 void *sigmask = (regs + 20);
1071 unsigned long pc;
1072 int is_write;
1073 uint32_t insn;
1074
1075 /* XXX: is there a standard glibc define ? */
1076 pc = regs[1];
1077 /* XXX: need kernel patch to get write flag faster */
1078 is_write = 0;
1079 insn = *(uint32_t *)pc;
1080 if ((insn >> 30) == 3) {
1081 switch((insn >> 19) & 0x3f) {
1082 case 0x05: // stb
1083 case 0x06: // sth
1084 case 0x04: // st
1085 case 0x07: // std
1086 case 0x24: // stf
1087 case 0x27: // stdf
1088 case 0x25: // stfsr
1089 is_write = 1;
1090 break;
1091 }
1092 }
1093 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1094 is_write, sigmask, NULL);
1095 }
1096
1097 #elif defined(__arm__)
1098
1099 int cpu_signal_handler(int host_signum, struct siginfo *info,
1100 void *puc)
1101 {
1102 struct ucontext *uc = puc;
1103 unsigned long pc;
1104 int is_write;
1105
1106 pc = uc->uc_mcontext.gregs[R15];
1107 /* XXX: compute is_write */
1108 is_write = 0;
1109 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1110 is_write,
1111 &uc->uc_sigmask);
1112 }
1113
1114 #elif defined(__mc68000)
1115
1116 int cpu_signal_handler(int host_signum, struct siginfo *info,
1117 void *puc)
1118 {
1119 struct ucontext *uc = puc;
1120 unsigned long pc;
1121 int is_write;
1122
1123 pc = uc->uc_mcontext.gregs[16];
1124 /* XXX: compute is_write */
1125 is_write = 0;
1126 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1127 is_write,
1128 &uc->uc_sigmask, puc);
1129 }
1130
1131 #elif defined(__ia64)
1132
1133 #ifndef __ISR_VALID
1134 /* This ought to be in <bits/siginfo.h>... */
1135 # define __ISR_VALID 1
1136 # define si_flags _sifields._sigfault._si_pad0
1137 #endif
1138
1139 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1140 {
1141 struct ucontext *uc = puc;
1142 unsigned long ip;
1143 int is_write = 0;
1144
1145 ip = uc->uc_mcontext.sc_ip;
1146 switch (host_signum) {
1147 case SIGILL:
1148 case SIGFPE:
1149 case SIGSEGV:
1150 case SIGBUS:
1151 case SIGTRAP:
1152 if (info->si_code && (info->si_flags & __ISR_VALID))
1153 /* ISR.W (write-access) is bit 33: */
1154 is_write = (info->si_isr >> 33) & 1;
1155 break;
1156
1157 default:
1158 break;
1159 }
1160 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1161 is_write,
1162 &uc->uc_sigmask, puc);
1163 }
1164
1165 #else
1166
1167 #error host CPU specific signal handler needed
1168
1169 #endif
1170
1171 #endif /* !defined(CONFIG_SOFTMMU) */
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