doc/README.mpc8360emds

   1 Freescale MPC8360EMDS Board
   2 -----------------------------------------
   3 1.      Board Switches and Jumpers
   4 1.0     There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
   5         For some reason, the HW designers describe the switch settings
   6         in terms of 0 and 1, and then map that to physical switches where
   7         the label "On" refers to logic 0 and "Off" is logic 1.
   8
   9         Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
  10         bits may contribute to signals that are numbered based at 0,
  11         and some of those signals may be high-bit-number-0 too.  Heed
  12         well the names and labels and do not get confused.
  13
  14                 "Off" == 1
  15                 "On"  == 0
  16
  17         SW18 is switch 18 as silk-screened onto the board.
  18         SW4[8] is the bit labled 8 on Switch 4.
  19         SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
  20         SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
  21         SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
  22                 and bits labeled 8 is set as "Off".
  23
  24 1.1     For the MPC8360E PB PROTO Board
  25
  26         First, make sure the board default setting is consistent with the
  27         document shipped with your board. Then apply the following setting:
  28         SW3[1-8]= 0000_0100  (HRCW setting value is performed on local bus)
  29         SW4[1-8]= 0011_0000  (Flash boot on local bus)
  30         SW9[1-8]= 0110_0110  (PCI Mode enabled. HRCW is read from FLASH)
  31         SW10[1-8]= 0000_1000  (core PLL setting)
  32         SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
  33         JP6 1-2
  34         on board Oscillator: 66M
  35
  36
  37 2.      Memory Map
  38
  39 2.1.    The memory map should look pretty much like this:
  40
  41         0x0000_0000     0x7fff_ffff     DDR                     2G
  42         0x8000_0000     0x8fff_ffff     PCI MEM prefetch        256M
  43         0x9000_0000     0x9fff_ffff     PCI MEM non-prefetch    256M
  44         0xc000_0000     0xdfff_ffff     Empty                   512M
  45         0xe000_0000     0xe01f_ffff     Int Mem Reg Space       2M
  46         0xe020_0000     0xe02f_ffff     Empty                   1M
  47         0xe030_0000     0xe03f_ffff     PCI IO                  1M
  48         0xe040_0000     0xefff_ffff     Empty                   252M
  49         0xf000_0000     0xf3ff_ffff     Local Bus SDRAM         64M
  50         0xf400_0000     0xf7ff_ffff     Empty                   64M
  51         0xf800_0000     0xf800_7fff     BCSR on CS1             32K
  52         0xf800_8000     0xf800_ffff     PIB CS4                 32K
  53         0xf801_0000     0xf801_7fff     PIB CS5                 32K
  54         0xfe00_0000     0xfeff_ffff     FLASH on CS0            16M
  55
  56
  57 3. Definitions
  58
  59 3.1 Explanation of NEW definitions in:
  60
  61         include/configs/MPC8360EMDS.h
  62
  63     CONFIG_MPC83XX          MPC83xx family for both MPC8349 and MPC8360
  64     CONFIG_MPC8360          MPC8360 specific
  65     CONFIG_MPC8360EMDS      MPC8360EMDS board specific
  66
  67 4. Compilation
  68
  69         Assuming you're using BASH shell:
  70
  71                 export CROSS_COMPILE=your-cross-compile-prefix
  72                 cd u-boot
  73                 make distclean
  74                 make MPC8360EMDS_config
  75                 make
  76
  77         MPC8360 support PCI in host and slave mode.
  78
  79         To make u-boot support PCI host 66M :
  80         1) DIP SW support PCI mode as described in Section 1.1.
  81         2) Make MPC8360EMDS_HOST_66_config
  82
  83         To make u-boot support PCI host 33M :
  84         1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
  85         2) Make MPC8360EMDS_HOST_33_config
  86
  87         To make u-boot support PCI slave 66M :
  88         1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
  89         2) Make MPC8360EMDS_SLAVE_config
  90
  91
  92 5. Downloading and Flashing Images
  93
  94 5.0 Download over serial line using Kermit:
  95
  96         loadb
  97         [Drop to kermit:
  98             ^\c
  99             send <u-boot-bin-image>
 100             c
 101         ]
 102
 103
 104     Or via tftp:
 105
 106         tftp 10000 u-boot.bin
 107
 108 5.1 Reflash U-boot Image using U-boot
 109
 110         tftp 20000 u-boot.bin
 111         protect off fef00000 fef3ffff
 112         erase fef00000 fef3ffff
 113
 114         cp.b 20000 fef00000 xxxx
 115
 116         or
 117
 118         cp.b 20000 fef00000 3ffff
 119
 120
 121 You have to supply the correct byte count with 'xxxx' from the TFTP result log.
 122 Maybe 3ffff will work too, that corresponds to the erased sectors.
 123
 124
 125 6. Notes
 126         1) The console baudrate for MPC8360EMDS is 115200bps.