doc/README.mpc85xxads

   1 Motorola MPC8540ADS and MPC8560ADS board
   2
   3 Created 10/15/03 Xianghua Xiao
   4 Updated 13-July-2004 Jon Loeliger
   5 -----------------------------------------
   6
   7 0. Toolchain
   8
   9     The Binutils in current ELDK toolchain will not support MPC85xx
  10     chip.  You need to use binutils-2.14.tar.bz2 (or newer) from
  11     http://ftp.gnu.org/gnu/binutils.
  12
  13     The 8540/8560 ADS code base is known to compile using:
  14         gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
  15
  16
  17 1. SWITCH SETTINGS & JUMPERS
  18
  19 1.0 Nomenclature
  20
  21     For some reason, the HW designers describe the switch settings
  22     in terms of 0 and 1, and then map that to physical switches where
  23     the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1.
  24     Luckily, we're SW types and virtual settings are handled daily.
  25
  26     The switches for the Rev A board are numbered differently than
  27     for the Pilot board.  Oh yeah.
  28
  29     Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
  30     bits may contribute to signals that are numbered based at 0,
  31     and some of those signals may be high-bit-number-0 too.  Heed
  32     well the names and labels and do not get confused.
  33
  34     "Off" == 1
  35     "On"  == 0
  36
  37     SW18 is switch 18 as silk-screened onto the board.
  38     SW4[8] is the bit labled 8 on Switch 4.
  39     SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2
  40     SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3
  41
  42 1.1 For the MPC85xxADS Pilot Board
  43
  44     First, make sure the board default setting is consistent with the document
  45     shipped with your board. Then apply the following changes:
  46     SW3[1-6]="all OFF"  (boot from 32bit flash, no boot sequence is used)
  47     SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
  48     SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode)
  49     SW11[7]='ON' (rev2), 'OFF' (rev1)
  50     SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector)
  51     SW22[1-4]="OFF OFF ON OFF"
  52     SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF"
  53     J1 = "Enable Prog" (Make sure your flash is programmable for development)
  54
  55     If you want to test PCI functionality with a 33Mhz PCI card, you will
  56     have to change the system clock from the default 66Mhz to 33Mhz by
  57     setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need
  58     double your platform clock(SW6) because the system clock is now only
  59     half of its original value. For example, if at 66MHz your system
  60     clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10.
  61
  62         SW17[8] ------+    SW6
  63         SW15[1] ----+ |   [0:1]
  64                     V V    V V
  65         33MHz       1 1    1 0
  66         66MHz       0 0    0 1
  67
  68     Hmmm... That SW6 setting description is incomplete but it works.
  69
  70
  71 1.3 For the MPC85xxADS Rev A Board
  72
  73     As shipped, the board should be a 33MHz PCI bus with a CPU Clock
  74     rate of 825 +/- fuzz:
  75
  76         Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC:  82 MHz
  77
  78     For 33MHz PCI, the switch settings should be like this:
  79
  80         SW18[7:1] = 0100001 = M==33 =>    33MHz
  81         SW18[8]   =       1         => PWD Divider == 16
  82         SW16[1:2] =      11         => N == 16 as PWD==1
  83
  84     Use the magical formula:
  85         Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz
  86
  87         SW7[1:4]  =    1010 = 10    => 10 x 33   = 330  CCB Sysclk
  88         SW7[5:6]  =      01         => 5:2 x 330 = 825  Core clock
  89
  90
  91     For 66MHz PCI, the switch settings should be like this:
  92
  93         SW18[7:1] = 0100001 = M==33 =>    33MHz
  94         SW18[8]   =       0         => PWD Divider == 1
  95         SW16[1:2] =      01         => N == 8 as PWD == 0
  96
  97     Use the magical formula:
  98         Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz
  99
 100         SW7[1:4]  =    0101 =  5    => 5 x 66    = 330  CCB Sysclk
 101         SW7[5:6]  =      01         => 5:2 x 330 = 825  Core clock
 102
 103
 104 2. MEMORY MAP TO WORK WITH LINUX KERNEL
 105
 106 2.1. For the initial bringup, we adopted a consistent memory scheme
 107      between u-boot and linux kernel, you can customize it based on your
 108      system requirements:
 109
 110      0x0000_0000     0x7fff_ffff     DDR                     2G
 111      0x8000_0000     0x9fff_ffff     PCI MEM                 512M
 112      0xc000_0000     0xdfff_ffff     Rapid IO                512M
 113      0xe000_0000     0xe00f_ffff     CCSR                    1M
 114      0xe200_0000     0xe2ff_ffff     PCI IO                  16M
 115      0xf000_0000     0xf7ff_ffff     SDRAM                   128M
 116      0xf800_0000     0xf80f_ffff     BCSR                    1M
 117      0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
 118
 119 2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. You
 120     can download them from linuxppc-2.4 public source. Please make sure the
 121     kernel's ppcboot.h is consistent with U-Boot's u-boot.h. You can use two
 122     default configuration files as your starting points to configure the
 123     kernel:
 124         arch/ppc/configs/mpc8540_ads_defconfig
 125         arch/ppc/configs/mpc8560_ads_defconfig
 126
 127 3. DEFINITIONS AND COMPILATION
 128
 129 3.1 Explanation on NEW definitions in:
 130         include/configs/MPC8540ADS.h
 131         include/configs/MPC8560ADS.h
 132
 133     CONFIG_BOOKE            BOOKE(e.g. Motorola MPC85xx, IBM 440, etc)
 134     CONFIG_E500             BOOKE e500 family(Motorola)
 135     CONFIG_MPC85xx          MPC8540,MPC8560 and their derivatives
 136     CONFIG_MPC8540          MPC8540 specific
 137     CONFIG_MPC8540ADS       MPC8540ADS board specific
 138     CONFIG_MPC8560ADS       MPC8560ADS board specific
 139     CONFIG_TSEC_ENET        Use on-chip 10/100/1000 ethernet for networking
 140     CONFIG_SPD_EEPROM       Use SPD EEPROM for DDR auto configuration, you can
 141                             also manual config the DDR after undef this
 142                             definition.
 143     CONFIG_DDR_ECC          only for ECC DDR module
 144     CONFIG_DDR_DLL          DLL fix on some ADS boards needed for more
 145                             stability.
 146     CONFIG_HAS_FEC          If an FEC is on chip, set to 1, else 0.
 147
 148 Other than the above definitions, the rest in the config files are
 149 straightforward.
 150
 151
 152 3.2 Compilation
 153
 154     Assuming you're using BASH shell:
 155
 156         export CROSS_COMPILE=your-cross-compile-prefix
 157         cd u-boot
 158         make distclean
 159         make MPC8560ADS_config (or make MPC8540ADS_config)
 160         make
 161
 162 4.  Notes:
 163
 164 4.1 When connecting with kermit, the following commands must be present.in
 165     your .kermrc file. These are especially important when booting as
 166     MPC8560, as the serial console will not work without them:
 167
 168         set speed 115200
 169         set carrier-watch off
 170         set handshake none
 171         set flow-control none
 172         robust
 173
 174
 175 4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC
 176     ethernet. If that happens, you can try the following steps to make
 177     network work:
 178
 179         MPC8560ADS>tftp 1000000 pImage
 180         (if it hangs, use Ctrl-C to quit)
 181         MPC8560ADS>nm fdf24524
 182         >0
 183         >1
 184         >. (to quit this memory operation)
 185         MPC8560ADS>tftp 1000000 pImage
 186
 187 4.3 If you're one of the early developers using the Rev1 8540/8560 chips,
 188     please use U-Boot 1.0.0, as the newer silicon will only support Rev2
 189     and future revisions of 8540/8560.
 190
 191
 192 4.4 Reflash U-boot Image using U-boot
 193
 194     tftp 10000 u-boot.bin
 195     protect off fff80000 ffffffff
 196     erase fff80000 ffffffff
 197     cp.b 10000 fff80000 80000
 198
 199
 200 4.5 Reflash U-Boot with a BDI-2000
 201
 202     BDI> erase 0xFFF80000 0x4000 0x20
 203     BDI> prog 0xfff80000 u-boot.bin.8560ads
 204     BDI> verify
 205
 206
 207 5. Screen dump MPC8540ADS board
 208
 209 U-Boot 1.1.2(pq3-20040707-0) (Jul  6 2004 - 17:34:25)
 210
 211 Freescale PowerPC
 212     Core: E500, Version: 2.0, (0x80200020)
 213     System: 8540, Version: 2.0, (0x80300020)
 214     Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC:  82 MHz
 215     L1 D-cache 32KB, L1 I-cache 32KB enabled.
 216 Board: ADS
 217     PCI1: 32 bit, 66 MHz (compiled)
 218 I2C:   ready
 219 DRAM:  Initializing
 220     SDRAM: 64 MB
 221     DDR: 256 MB
 222 FLASH: 16 MB
 223 L2 cache enabled: 256KB
 224 *** Warning - bad CRC, using default environment
 225
 226 In:    serial
 227 Out:   serial
 228 Err:   serial
 229 Net:   MOTO ENET0: PHY is Marvell 88E1011S (1410c62)
 230 MOTO ENET1: PHY is Marvell 88E1011S (1410c62)
 231 MOTO ENET2: PHY is Davicom DM9161E (181b881)
 232 MOTO ENET0, MOTO ENET1, MOTO ENET2
 233 Hit any key to stop autoboot:  0
 234 =>
 235 => fli
 236
 237 Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
 238   Size: 16 MB in 64 Sectors
 239   Sector Start Addresses:
 240     FF000000      FF040000      FF080000      FF0C0000      FF100000
 241     FF140000      FF180000      FF1C0000      FF200000      FF240000
 242     FF280000      FF2C0000      FF300000      FF340000      FF380000
 243     FF3C0000      FF400000      FF440000      FF480000      FF4C0000
 244     FF500000      FF540000      FF580000      FF5C0000      FF600000
 245     FF640000      FF680000      FF6C0000      FF700000      FF740000
 246     FF780000      FF7C0000      FF800000      FF840000      FF880000
 247     FF8C0000      FF900000      FF940000      FF980000      FF9C0000
 248     FFA00000      FFA40000      FFA80000      FFAC0000      FFB00000
 249     FFB40000      FFB80000      FFBC0000      FFC00000      FFC40000
 250     FFC80000      FFCC0000      FFD00000      FFD40000      FFD80000
 251     FFDC0000      FFE00000      FFE40000      FFE80000      FFEC0000
 252     FFF00000      FFF40000      FFF80000 (RO) FFFC0000 (RO)
 253
 254 => bdinfo
 255 memstart    = 0x00000000
 256 memsize     = 0x10000000
 257 flashstart  = 0xFF000000
 258 flashsize   = 0x01000000
 259 flashoffset = 0x00000000
 260 sramstart   = 0x00000000
 261 sramsize    = 0x00000000
 262 immr_base   = 0xE0000000
 263 bootflags   = 0xE4013F80
 264 intfreq     =    825 MHz
 265 busfreq     =    330 MHz
 266 ethaddr     = 00:E0:0C:00:00:FD
 267 eth1addr    = 00:E0:0C:00:01:FD
 268 eth2addr    = 00:E0:0C:00:02:FD
 269 IP addr     = 192.168.1.253
 270 baudrate    = 115200 bps
 271
 272
 273 => printenv
 274 bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
 275 ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr
 276 nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
 277 bootdelay=10
 278 baudrate=115200
 279 loads_echo=1
 280 ethaddr=00:E0:0C:00:00:FD
 281 eth1addr=00:E0:0C:00:01:FD
 282 eth2addr=00:E0:0C:00:02:FD
 283 ipaddr=192.168.1.253
 284 serverip=192.168.1.1
 285 rootpath=/nfsroot
 286 gatewayip=192.168.1.1
 287 netmask=255.255.255.0
 288 hostname=unknown
 289 bootfile=your.uImage
 290 loadaddr=200000
 291 netdev=eth0
 292 consoledev=ttyS0
 293 ramdiskaddr=400000
 294 ramdiskfile=your.ramdisk.u-boot
 295 stdin=serial
 296 stdout=serial
 297 stderr=serial
 298 ethact=MOTO ENET0
 299
 300 Environment size: 1020/8188 bytes