doc/README.sbc8548

   1 Intro:
   2 ======
   3
   4 The SBC8548 is a stand alone single board computer with a 1GHz
   5 MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
   6 memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
   7 and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
   8 ethernet connections.
   9
  10 U-boot Configuration:
  11 =====================
  12
  13 The following possible u-boot configuration targets are available:
  14
  15         1) sbc8548_config
  16         2) sbc8548_PCI_33_config
  17         3) sbc8548_PCI_66_config
  18         4) sbc8548_PCI_33_PCIE_config
  19         5) sbc8548_PCI_66_PCIE_config
  20
  21 Generally speaking, most people should choose to use #5.  Details
  22 of each choice are listed below.
  23
  24 Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
  25 will be left empty (M66EN high), and so the board will operate with
  26 a base clock of 66MHz.  Note that you need both PCI enabled in u-boot
  27 and linux in order to have functional PCI under linux.
  28
  29 The second enables PCI support and builds for a 33MHz clock rate.  Note
  30 that if a 33MHz 32bit card is inserted in the slot, then the whole board
  31 will clock down to a 33MHz base clock instead of the default 66MHz.  This
  32 will change the baud clocks and mess up your serial console output if you
  33 were previously running at 66MHz.  If you want to use a 33MHz PCI card,
  34 then you should build a U-Boot with a _PCI_33_ config and store this
  35 to flash prior to powering down the board and inserting the 33MHz PCI
  36 card. [The above discussion assumes that the SW2[1-4] has not been changed
  37 to reflect a different CCB:SYSCLK ratio]
  38
  39 The third option builds PCI support in, and leaves the clocking at the
  40 default 66MHz.  Options four and five are just repeats of option two
  41 and three, but with PCI-e support enabled as well.
  42
  43 PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
  44 is shown below for sbc8548_PCI_66_PCIE_config.  (Note that PCI-e with
  45 a 33MHz PCI configuration is currently untested.)
  46
  47     => pci 0
  48     Scanning PCI devices on bus 0
  49     BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
  50     _____________________________________________________________
  51     00.00.00   0x1057     0x0012     Processor               0x20
  52     00.01.00   0x8086     0x1026     Network controller      0x00
  53     => pci 1
  54     Scanning PCI devices on bus 1
  55     BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
  56     _____________________________________________________________
  57     01.00.00   0x1957     0x0012     Processor               0x20
  58     => pci 2
  59     Scanning PCI devices on bus 2
  60     BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
  61     _____________________________________________________________
  62     02.00.00   0x1148     0x9e00     Network controller      0x00
  63     =>
  64
  65
  66 Updating U-boot with U-boot:
  67 ============================
  68
  69 Note that versions of u-boot up to and including 2009.08 had u-boot stored
  70 at 0xfff8_0000 -> 0xffff_ffff (512k).  Currently it is being stored from
  71 0xfffa_0000 -> 0xffff_ffff (384k).  If you use an old macro/script to
  72 update u-boot with u-boot and it uses the old address, you will render
  73 your board inoperable, and you will require JTAG recovery.
  74
  75 The following steps list how to update with the current address:
  76
  77         tftp u-boot.bin
  78         md 200000 10
  79         protect off all
  80         erase fffa0000 ffffffff
  81         cp.b 200000 fffa0000 60000
  82         md fffa0000 10
  83         protect on all
  84
  85 The "md" steps in the above are just a precautionary step that allow
  86 you to confirm the u-boot version that was downloaded, and then confirm
  87 that it was copied to flash.
  88
  89 The above assumes that you are using the default board settings which
  90 have u-boot in the 8MB flash, tied to /CS0.
  91
  92 If you are running the default 8MB /CS0 settings but want to store an
  93 image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
  94 (as a backup, etc) then the steps will become:
  95
  96         tftp u-boot.bin
  97         md 200000 10
  98         protect off all
  99         era eff00000 efffffff
 100         cp.b 200000 eff00000 100000
 101         md eff00000 10
 102         protect on all
 103
 104 Finally, if you are running the alternate 64MB /CS0 settings and want
 105 to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT
 106 enabled) the steps will become:
 107
 108         tftp u-boot.bin
 109         md 200000 10
 110         protect off all
 111         era fff00000 ffffffff
 112         cp.b 200000 fff00000 100000
 113         md fff00000 10
 114         protect on all
 115
 116
 117 Hardware Reference:
 118 ===================
 119
 120 The following contains some summary information on hardware settings
 121 that are relevant to u-boot, based on the board manual.  For the
 122 most up to date and complete details of the board, please request the
 123 reference manual ERG-00327-001.pdf from www.windriver.com
 124
 125 Boot flash:
 126         intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
 127
 128 Sodimm flash:
 129         intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
 130         Note that this address reflects the default setting for
 131         the JTAG debugging tools, but since the alignment is
 132         rather inconvenient, u-boot puts it at 0xec00_0000.
 133
 134
 135         Jumpers:
 136
 137 Jumper          Name            ON              OFF
 138 ----------------------------------------------------------------
 139 JP12            CS0/CS6 swap    see note[*]     see note[*]
 140
 141 JP13            SODIMM flash    write OK        writes disabled
 142                 write prot.
 143
 144 JP14            HRESET/TRST     joined          isolated
 145
 146 JP15            PWR ON          when AC pwr     use S1 for on/off
 147
 148 JP16            Demo LEDs       lit             not lit
 149
 150 JP19            PCI mode        PCI             PCI-X
 151
 152
 153 [*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
 154 onto /CS0 and the SODIMM flash on /CS6 (default).  When JP12
 155 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
 156 SODIMM flash and /CS6 is for the boot flash.  Note that in this
 157 alternate setting, you also need to switch SW2.8 to ON.
 158 See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
 159 and boot u-boot from the 64MB SODIMM
 160
 161
 162         Switches:
 163
 164 The defaults are marked with a *
 165
 166 Name            Desc.                   ON              OFF
 167 ------------------------------------------------------------------
 168 S1              Pwr toggle              n/a             n/a
 169
 170 SW2.1           CFG_SYS_PLL0            1               0*
 171 SW2.2           CFG_SYS_PLL1            1*              0
 172 SW2.3           CFG_SYS_PLL2            1*              0
 173 SW2.4           CFG_SYS_PLL3            1               0*
 174 SW2.5           CFG_CORE_PLL0           1*              0
 175 SW2.6           CFG_CORE_PLL1           1               0*
 176 SW2.7           CFG_CORE_PLL2           1*              0
 177 SW2.8           CFG_ROM_LOC1            1               0*
 178
 179 SW3.1           CFG_HOST_AGT0           1*              0
 180 SW3.2           CFG_HOST_AGT1           1*              0
 181 SW3.3           CFG_HOST_AGT2           1*              0
 182 SW3.4           CFG_IO_PORTS0           1*              0
 183 SW3.5           CFG_IO_PORTS0           1               0*
 184 SW3.6           CFG_IO_PORTS0           1               0*
 185
 186 SerDes CLK(MHz)         SW5.1           SW5.2
 187 ----------------------------------------------
 188 25                      0               0
 189 100*                    1               0
 190 125                     0               1
 191 200                     1               1
 192
 193 SerDes CLK spread       SW5.3           SW5.4
 194 ----------------------------------------------
 195 +/- 0.25%               0               0
 196 -0.50%                  1               0
 197 -0.75%                  0               1
 198 No Spread*              1               1
 199
 200 SW4 settings are readable from the EPLD and are currently not used for
 201 any hardware settings (i.e. user configuration switches).
 202
 203         LEDs:
 204
 205 Name            Desc.                   ON              OFF
 206 ------------------------------------------------------------------
 207 D13             PCI/PCI-X               PCI-X           PCI
 208 D14             3.3V PWR                3.3V            no power
 209 D15             SYSCLK                  66MHz           33MHz
 210
 211
 212         Default Memory Map:
 213
 214 start           end             CS<n>   width   Desc.
 215 ----------------------------------------------------------------------
 216 0000_0000       0fff_ffff       MCS0,1  64      DDR2 (256MB)
 217 f000_0000       f7ff_ffff       CS3,4   32      LB SDRAM (128MB)
 218 f800_0000       f8b0_1fff       CS5     -       EPLD
 219 fb80_0000       ff7f_ffff       CS6     32      SODIMM flash (64MB) [*]
 220 ff80_0000       ffff_ffff       CS0     8       Boot flash (8MB)
 221
 222 [*] fb80 represents the default programmed by WR JTAG register files,
 223     but u-boot places the flash at either ec00 or fc00 based on JP12.
 224
 225 The EPLD on CS5 demuxes the following devices at the following offsets:
 226
 227 offset          size    width   device
 228 --------------------------------------------------------
 229 0               1fff    8       7 segment display LED
 230 10_0000         1fff    4       user switches
 231 30_0000         1fff    4       HW Rev. register
 232 b0_0000         1fff    8       8kB EEPROM