docs/specs/pci-testdev.txt

   1 pci-test is a device used for testing low level IO
   2
   3 device implements up to three BARs: BAR0, BAR1 and BAR2.
   4 Each of BAR 0+1 can be memory or IO. Guests must detect
   5 BAR types and act accordingly.
   6
   7 BAR 0+1 size is up to 4K bytes each.
   8 BAR 0+1 starts with the following header:
   9
  10 typedef struct PCITestDevHdr {
  11     uint8_t test;  <- write-only, starts a given test number
  12     uint8_t width_type; <- read-only, type and width of access for a given test.
  13                            1,2,4 for byte,word or long write.
  14                            any other value if test not supported on this BAR
  15     uint8_t pad0[2];
  16     uint32_t offset; <- read-only, offset in this BAR for a given test
  17     uint32_t data;    <- read-only, data to use for a given test
  18     uint32_t count;  <- for debugging. number of writes detected.
  19     uint8_t name[]; <- for debugging. 0-terminated ASCII string.
  20 } PCITestDevHdr;
  21
  22 All registers are little endian.
  23
  24 device is expected to always implement tests 0 to N on each BAR, and to add new
  25 tests with higher numbers.  In this way a guest can scan test numbers until it
  26 detects an access type that it does not support on this BAR, then stop.
  27
  28 BAR2 is a 64bit memory bar, without backing storage.  It is disabled
  29 by default and can be enabled using the membar=<size> property.  This
  30 can be used to test whether guests handle pci bars of a specific
  31 (possibly quite large) size correctly.