drivers/at91rm9200_ether.c

   1
   2 #include <common.h>
   3 #include <command.h>
   4 #include <asm/io.h>
   5 #include <net.h>
   6
   7 /* ----- Ethernet Buffer definitions ----- */
   8
   9 typedef struct {
  10   unsigned long addr,size;
  11 } rbf_t;
  12
  13 #define RBF_ADDR      0xfffffffc
  14 #define RBF_OWNER     (1<<0)
  15 #define RBF_WRAP      (1<<1)
  16 #define RBF_BROADCAST (1<<31)
  17 #define RBF_MULTICAST (1<<30)
  18 #define RBF_UNICAST   (1<<29)
  19 #define RBF_EXTERNAL  (1<<28)
  20 #define RBF_UNKOWN    (1<<27)
  21 #define RBF_SIZE      0x07ff
  22 #define RBF_LOCAL4    (1<<26)
  23 #define RBF_LOCAL3    (1<<25)
  24 #define RBF_LOCAL2    (1<<24)
  25 #define RBF_LOCAL1    (1<<23)
  26
  27 #define RBF_FRAMEMAX 10
  28 #define RBF_FRAMEMEM 0x200000
  29 #define RBF_FRAMELEN 0x600
  30
  31 #define RBF_FRAMEBTD RBF_FRAMEMEM
  32 #define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t))
  33
  34 /* stolen from mii.h */
  35 /* Generic MII registers. */
  36
  37 #define MII_BMCR            0x00        /* Basic mode control register */
  38 #define MII_BMSR            0x01        /* Basic mode status register  */
  39 #define BMSR_JCD                0x0002  /* Jabber detected             */
  40 #define BMSR_LSTATUS            0x0004  /* Link status                 */
  41 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
  42 #define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
  43 #define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
  44 #define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
  45
  46 #define MII_STS2_REG    17  /* Davicom specific */
  47 #define MII_MDINTR_REG  21  /* Davicom specific */
  48
  49 #ifdef CONFIG_DRIVER_ETHER
  50
  51 #if (CONFIG_COMMANDS & CFG_CMD_NET)
  52
  53 AT91PS_EMAC p_mac;
  54
  55 int MII_ReadPhy(unsigned char addr, unsigned short *ret)
  56   {
  57
  58   p_mac->EMAC_MAN = 0x60020000 | (addr << 18);
  59   udelay(10000);
  60   *ret = (unsigned short)p_mac->EMAC_MAN;
  61   return 1;
  62   }
  63
  64
  65 int MII_GetLinkSpeed(void)
  66   {
  67   unsigned short stat1, stat2;
  68   int ret;
  69
  70   if (!(ret = MII_ReadPhy(MII_BMSR, &stat1)))
  71     return 0;
  72
  73   if (stat1 & BMSR_JCD)
  74     {
  75 #ifdef DEBUG
  76     printf("MII: jabber condition detected\n");
  77 #endif      /*jabber detected re-read the register*/
  78     }
  79   if (!(ret = MII_ReadPhy(MII_BMSR, &stat1)))
  80     return 0;
  81   if (!(stat1 & BMSR_LSTATUS))  /* link status up? */
  82     {
  83     printf("MII: no Link\n");
  84     return 0;
  85     }
  86
  87   if (!(ret = MII_ReadPhy(MII_STS2_REG, &stat2)))
  88     return 0;
  89
  90   if ((stat1 & BMSR_100FULL) && (stat2 & 0x8000) )
  91     {
  92     /* set MII for 100BaseTX and Full Duplex */
  93     p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
  94 #ifdef DEBUG
  95     printf("MII: 100BaseTX and Full Duplex detected\n");
  96 #endif
  97     return 1;
  98     }
  99
 100   else
 101     if ((stat1 & BMSR_10FULL) && (stat2 & 0x2000))
 102       {
 103       /* set MII for 10BaseT and Full Duplex */
 104       p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD));
 105 #ifdef DEBUG
 106         printf("MII: 10BaseT and Full Duplex detected\n");
 107 #endif
 108       return 1;
 109       }
 110     else
 111       if ((stat1 & BMSR_100HALF) && (stat2 & 0x4000))
 112         {
 113         /* set MII for 100BaseTX and Half Duplex */
 114         p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD));
 115 #ifdef DEBUG
 116           printf("MII: 100BaseTX and Hall Duplex detected\n");
 117 #endif
 118         return 1;
 119         }
 120       else
 121         if ((stat1 & BMSR_10HALF) && (stat2 & 0x1000))
 122           {
 123           /*set MII for 10BaseT and Half Duplex */
 124           p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
 125 #ifdef DEBUG
 126           printf("MII: 10BaseT and Hall Duplex detected\n");
 127 #endif
 128           return 1;
 129           }
 130
 131   return 0;
 132   }
 133
 134
 135 int MDIO_StartupPhy(void)
 136   {
 137   int ret;
 138
 139   if(p_mac->EMAC_SR & AT91C_EMAC_LINK)
 140     {
 141     printf("MDIO_StartupPhy: no link\n");
 142     return 0;
 143     };
 144
 145   p_mac->EMAC_CTL |= AT91C_EMAC_MPE;
 146
 147   ret = MII_GetLinkSpeed();
 148   if (ret == 0)
 149     {
 150     printf("MDIO_StartupPhy: MII_GetLinkSpeed failed\n");
 151     ret = 0;
 152     }
 153   else
 154     {
 155     ret = 1;
 156     }
 157
 158   p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE;
 159   return ret;
 160
 161   }
 162
 163
 164 rbf_t* rbfdt;
 165 rbf_t* rbfp;
 166
 167 int eth_init( bd_t *bd )
 168   {
 169   int ret;
 170   int i;
 171   p_mac = AT91C_BASE_EMAC;
 172
 173   *AT91C_PIOA_PDR = AT91C_PA16_EMDIO |
 174     AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1 | AT91C_PA12_ERX0 |
 175     AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
 176     AT91C_PA7_ETXCK_EREFCK;     /* PIO Disable Register */
 177
 178   *AT91C_PIOB_PDR = AT91C_PB25_EF100 |
 179     AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 |
 180     AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
 181
 182   *AT91C_PIOB_BSR = AT91C_PB25_EF100 |
 183     AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 |
 184     AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;  /* Select B Register */
 185   *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC;  /* Peripheral Clock Enable Register */
 186   p_mac->EMAC_CFG |= AT91C_EMAC_CSR;  /* Clear statistics */
 187
 188   rbfdt=(rbf_t *)RBF_FRAMEBTD;
 189   for(i = 0; i < RBF_FRAMEMAX; i++)
 190     {
 191     rbfdt[i].addr=RBF_FRAMEBUF+RBF_FRAMELEN*i;
 192     rbfdt[i].size=0;
 193     }
 194   rbfdt[RBF_FRAMEMAX-1].addr|=RBF_WRAP;
 195   rbfp=&rbfdt[0];
 196
 197   if (!(ret = MDIO_StartupPhy()))
 198     {
 199     printf("MAC: error during MII initialization\n");
 200     return 0;
 201     }
 202
 203   p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
 204     | (bd->bi_enetaddr[1] <<  8) | (bd->bi_enetaddr[0]);
 205   p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] <<  8) | (bd->bi_enetaddr[4]);
 206
 207   p_mac->EMAC_RBQP = (long)(&rbfdt[0]);
 208   p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
 209   p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_RMII) & ~AT91C_EMAC_CLK;
 210   p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE ;
 211
 212   return 0;
 213   }
 214
 215 int eth_send(volatile void *packet, int length)
 216   {
 217   while(!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ))
 218     ;
 219   p_mac->EMAC_TAR = (long)packet;
 220   p_mac->EMAC_TCR = length;
 221   while(p_mac->EMAC_TCR & 0x7ff)
 222     ;
 223   p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
 224   return 0;
 225   }
 226
 227 int eth_rx(void)
 228   {
 229   int size;
 230
 231   if(!(rbfp->addr & RBF_OWNER))
 232     return 0;
 233
 234   size=rbfp->size & RBF_SIZE;
 235   NetReceive((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
 236
 237   rbfp->addr &= ~RBF_OWNER;
 238   if(rbfp->addr & RBF_WRAP)
 239     rbfp = &rbfdt[0];
 240   else
 241     rbfp++;
 242
 243   p_mac->EMAC_RSR |= AT91C_EMAC_REC;
 244
 245   return size;
 246   }
 247
 248 void eth_halt( void )
 249  {};
 250 #endif
 251 #endif