2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference on libata and ahci drvier in kernel
15 #include <asm/processor.h>
16 #include <linux/errno.h>
22 #include <linux/ctype.h>
25 static int ata_io_flush(struct ahci_uc_priv
*uc_priv
, u8 port
);
27 struct ahci_uc_priv
*probe_ent
= NULL
;
29 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
32 * Some controllers limit number of blocks they can read/write at once.
33 * Contemporary SSD devices work much faster if the read/write size is aligned
34 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
37 #ifndef MAX_SATA_BLOCKS_READ_WRITE
38 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
41 /* Maximum timeouts for each event */
42 #define WAIT_MS_SPINUP 20000
43 #define WAIT_MS_DATAIO 10000
44 #define WAIT_MS_FLUSH 5000
45 #define WAIT_MS_LINKUP 200
47 __weak
void __iomem
*ahci_port_base(void __iomem
*base
, u32 port
)
49 return base
+ 0x100 + (port
* 0x80);
53 static void ahci_setup_port(struct ahci_ioports
*port
, void __iomem
*base
,
54 unsigned int port_idx
)
56 base
= ahci_port_base(base
, port_idx
);
58 port
->cmd_addr
= base
;
59 port
->scr_addr
= base
+ PORT_SCR
;
63 #define msleep(a) udelay(a * 1000)
65 static void ahci_dcache_flush_range(unsigned long begin
, unsigned long len
)
67 const unsigned long start
= begin
;
68 const unsigned long end
= start
+ len
;
70 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
71 flush_dcache_range(start
, end
);
75 * SATA controller DMAs to physical RAM. Ensure data from the
76 * controller is invalidated from dcache; next access comes from
79 static void ahci_dcache_invalidate_range(unsigned long begin
, unsigned long len
)
81 const unsigned long start
= begin
;
82 const unsigned long end
= start
+ len
;
84 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
85 invalidate_dcache_range(start
, end
);
89 * Ensure data for SATA controller is flushed out of dcache and
90 * written to physical memory.
92 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports
*pp
)
94 ahci_dcache_flush_range((unsigned long)pp
->cmd_slot
,
95 AHCI_PORT_PRIV_DMA_SZ
);
98 static int waiting_for_cmd_completed(void __iomem
*offset
,
105 for (i
= 0; ((status
= readl(offset
)) & sign
) && i
< timeout_msec
; i
++)
108 return (i
< timeout_msec
) ? 0 : -1;
111 int __weak
ahci_link_up(struct ahci_uc_priv
*uc_priv
, u8 port
)
115 void __iomem
*port_mmio
= uc_priv
->port
[port
].port_mmio
;
118 * Bring up SATA link.
119 * SATA link bringup time is usually less than 1 ms; only very
120 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
122 while (j
< WAIT_MS_LINKUP
) {
123 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
124 tmp
&= PORT_SCR_STAT_DET_MASK
;
125 if (tmp
== PORT_SCR_STAT_DET_PHYRDY
)
133 #ifdef CONFIG_SUNXI_AHCI
134 /* The sunxi AHCI controller requires this undocumented setup */
135 static void sunxi_dma_init(void __iomem
*port_mmio
)
137 clrsetbits_le32(port_mmio
+ PORT_P0DMACR
, 0x0000ff00, 0x00004400);
141 int ahci_reset(void __iomem
*base
)
144 u32 __iomem
*host_ctl_reg
= base
+ HOST_CTL
;
145 u32 tmp
= readl(host_ctl_reg
); /* global controller reset */
147 if ((tmp
& HOST_RESET
) == 0)
148 writel_with_flush(tmp
| HOST_RESET
, host_ctl_reg
);
151 * reset must complete within 1 second, or
152 * the hardware should be considered fried.
156 tmp
= readl(host_ctl_reg
);
158 } while ((i
> 0) && (tmp
& HOST_RESET
));
161 printf("controller reset failed (0x%x)\n", tmp
);
168 static int ahci_host_init(struct ahci_uc_priv
*uc_priv
)
170 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
171 # ifdef CONFIG_DM_PCI
172 struct udevice
*dev
= uc_priv
->dev
;
173 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
175 pci_dev_t pdev
= uc_priv
->dev
;
176 unsigned short vendor
;
180 void __iomem
*mmio
= uc_priv
->mmio_base
;
181 u32 tmp
, cap_save
, cmd
;
183 void __iomem
*port_mmio
;
186 debug("ahci_host_init: start\n");
188 cap_save
= readl(mmio
+ HOST_CAP
);
189 cap_save
&= ((1 << 28) | (1 << 17));
190 cap_save
|= (1 << 27); /* Staggered Spin-up. Not needed. */
192 ret
= ahci_reset(uc_priv
->mmio_base
);
196 writel_with_flush(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
197 writel(cap_save
, mmio
+ HOST_CAP
);
198 writel_with_flush(0xf, mmio
+ HOST_PORTS_IMPL
);
200 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
201 # ifdef CONFIG_DM_PCI
202 if (pplat
->vendor
== PCI_VENDOR_ID_INTEL
) {
205 dm_pci_read_config16(dev
, 0x92, &tmp16
);
206 dm_pci_write_config16(dev
, 0x92, tmp16
| 0xf);
209 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
211 if (vendor
== PCI_VENDOR_ID_INTEL
) {
213 pci_read_config_word(pdev
, 0x92, &tmp16
);
215 pci_write_config_word(pdev
, 0x92, tmp16
);
219 uc_priv
->cap
= readl(mmio
+ HOST_CAP
);
220 uc_priv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
221 port_map
= uc_priv
->port_map
;
222 uc_priv
->n_ports
= (uc_priv
->cap
& 0x1f) + 1;
224 debug("cap 0x%x port_map 0x%x n_ports %d\n",
225 uc_priv
->cap
, uc_priv
->port_map
, uc_priv
->n_ports
);
227 if (uc_priv
->n_ports
> CONFIG_SYS_SCSI_MAX_SCSI_ID
)
228 uc_priv
->n_ports
= CONFIG_SYS_SCSI_MAX_SCSI_ID
;
230 for (i
= 0; i
< uc_priv
->n_ports
; i
++) {
231 if (!(port_map
& (1 << i
)))
233 uc_priv
->port
[i
].port_mmio
= ahci_port_base(mmio
, i
);
234 port_mmio
= (u8
*)uc_priv
->port
[i
].port_mmio
;
235 ahci_setup_port(&uc_priv
->port
[i
], mmio
, i
);
237 /* make sure port is not active */
238 tmp
= readl(port_mmio
+ PORT_CMD
);
239 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
240 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
241 debug("Port %d is active. Deactivating.\n", i
);
242 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
243 PORT_CMD_FIS_RX
| PORT_CMD_START
);
244 writel_with_flush(tmp
, port_mmio
+ PORT_CMD
);
246 /* spec says 500 msecs for each bit, so
247 * this is slightly incorrect.
252 #ifdef CONFIG_SUNXI_AHCI
253 sunxi_dma_init(port_mmio
);
256 /* Add the spinup command to whatever mode bits may
257 * already be on in the command register.
259 cmd
= readl(port_mmio
+ PORT_CMD
);
260 cmd
|= PORT_CMD_SPIN_UP
;
261 writel_with_flush(cmd
, port_mmio
+ PORT_CMD
);
263 /* Bring up SATA link. */
264 ret
= ahci_link_up(uc_priv
, i
);
266 printf("SATA link %d timeout.\n", i
);
269 debug("SATA link ok.\n");
272 /* Clear error status */
273 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
275 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
277 debug("Spinning up device on SATA port %d... ", i
);
280 while (j
< WAIT_MS_SPINUP
) {
281 tmp
= readl(port_mmio
+ PORT_TFDATA
);
282 if (!(tmp
& (ATA_BUSY
| ATA_DRQ
)))
285 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
286 tmp
&= PORT_SCR_STAT_DET_MASK
;
287 if (tmp
== PORT_SCR_STAT_DET_PHYRDY
)
292 tmp
= readl(port_mmio
+ PORT_SCR_STAT
) & PORT_SCR_STAT_DET_MASK
;
293 if (tmp
== PORT_SCR_STAT_DET_COMINIT
) {
294 debug("SATA link %d down (COMINIT received), retrying...\n", i
);
299 printf("Target spinup took %d ms.\n", j
);
300 if (j
== WAIT_MS_SPINUP
)
305 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
306 debug("PORT_SCR_ERR 0x%x\n", tmp
);
307 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
309 /* ack any pending irq events for this port */
310 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
311 debug("PORT_IRQ_STAT 0x%x\n", tmp
);
313 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
315 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
317 /* register linkup ports */
318 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
319 debug("SATA port %d status: 0x%x\n", i
, tmp
);
320 if ((tmp
& PORT_SCR_STAT_DET_MASK
) == PORT_SCR_STAT_DET_PHYRDY
)
321 uc_priv
->link_port_map
|= (0x01 << i
);
324 tmp
= readl(mmio
+ HOST_CTL
);
325 debug("HOST_CTL 0x%x\n", tmp
);
326 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
327 tmp
= readl(mmio
+ HOST_CTL
);
328 debug("HOST_CTL 0x%x\n", tmp
);
329 #if !defined(CONFIG_DM_SCSI)
330 #ifndef CONFIG_SCSI_AHCI_PLAT
331 # ifdef CONFIG_DM_PCI
332 dm_pci_read_config16(dev
, PCI_COMMAND
, &tmp16
);
333 tmp
|= PCI_COMMAND_MASTER
;
334 dm_pci_write_config16(dev
, PCI_COMMAND
, tmp16
);
336 pci_read_config_word(pdev
, PCI_COMMAND
, &tmp16
);
337 tmp
|= PCI_COMMAND_MASTER
;
338 pci_write_config_word(pdev
, PCI_COMMAND
, tmp16
);
346 static void ahci_print_info(struct ahci_uc_priv
*uc_priv
)
348 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
349 # if defined(CONFIG_DM_PCI)
350 struct udevice
*dev
= uc_priv
->dev
;
352 pci_dev_t pdev
= uc_priv
->dev
;
356 void __iomem
*mmio
= uc_priv
->mmio_base
;
357 u32 vers
, cap
, cap2
, impl
, speed
;
361 vers
= readl(mmio
+ HOST_VERSION
);
363 cap2
= readl(mmio
+ HOST_CAP2
);
364 impl
= uc_priv
->port_map
;
366 speed
= (cap
>> 20) & 0xf;
376 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
379 # ifdef CONFIG_DM_PCI
380 dm_pci_read_config16(dev
, 0x0a, &cc
);
382 pci_read_config_word(pdev
, 0x0a, &cc
);
386 else if (cc
== 0x0106)
388 else if (cc
== 0x0104)
393 printf("AHCI %02x%02x.%02x%02x "
394 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
399 ((cap
>> 8) & 0x1f) + 1, (cap
& 0x1f) + 1, speed_s
, impl
, scc_s
);
405 cap
& (1 << 31) ? "64bit " : "",
406 cap
& (1 << 30) ? "ncq " : "",
407 cap
& (1 << 28) ? "ilck " : "",
408 cap
& (1 << 27) ? "stag " : "",
409 cap
& (1 << 26) ? "pm " : "",
410 cap
& (1 << 25) ? "led " : "",
411 cap
& (1 << 24) ? "clo " : "",
412 cap
& (1 << 19) ? "nz " : "",
413 cap
& (1 << 18) ? "only " : "",
414 cap
& (1 << 17) ? "pmp " : "",
415 cap
& (1 << 16) ? "fbss " : "",
416 cap
& (1 << 15) ? "pio " : "",
417 cap
& (1 << 14) ? "slum " : "",
418 cap
& (1 << 13) ? "part " : "",
419 cap
& (1 << 7) ? "ccc " : "",
420 cap
& (1 << 6) ? "ems " : "",
421 cap
& (1 << 5) ? "sxs " : "",
422 cap2
& (1 << 2) ? "apst " : "",
423 cap2
& (1 << 1) ? "nvmp " : "",
424 cap2
& (1 << 0) ? "boh " : "");
427 #ifndef CONFIG_SCSI_AHCI_PLAT
428 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
429 static int ahci_init_one(struct udevice
*dev
)
431 static int ahci_init_one(pci_dev_t dev
)
434 struct ahci_uc_priv
*uc_priv
;
435 #if !defined(CONFIG_DM_SCSI)
440 probe_ent
= malloc(sizeof(struct ahci_uc_priv
));
442 printf("%s: No memory for uc_priv\n", __func__
);
447 memset(uc_priv
, 0, sizeof(struct ahci_uc_priv
));
450 uc_priv
->host_flags
= ATA_FLAG_SATA
455 uc_priv
->pio_mask
= 0x1f;
456 uc_priv
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
458 #if !defined(CONFIG_DM_SCSI)
460 uc_priv
->mmio_base
= dm_pci_map_bar(dev
, PCI_BASE_ADDRESS_5
,
464 * JMicron-specific fixup:
465 * make sure we're in AHCI mode
467 dm_pci_read_config16(dev
, PCI_VENDOR_ID
, &vendor
);
468 if (vendor
== 0x197b)
469 dm_pci_write_config8(dev
, 0x41, 0xa1);
471 uc_priv
->mmio_base
= pci_map_bar(dev
, PCI_BASE_ADDRESS_5
,
475 * JMicron-specific fixup:
476 * make sure we're in AHCI mode
478 pci_read_config_word(dev
, PCI_VENDOR_ID
, &vendor
);
479 if (vendor
== 0x197b)
480 pci_write_config_byte(dev
, 0x41, 0xa1);
483 struct scsi_platdata
*plat
= dev_get_uclass_platdata(dev
);
484 uc_priv
->mmio_base
= (void *)plat
->base
;
487 debug("ahci mmio_base=0x%p\n", uc_priv
->mmio_base
);
488 /* initialize adapter */
489 rc
= ahci_host_init(uc_priv
);
493 ahci_print_info(uc_priv
);
502 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
504 static int ahci_fill_sg(struct ahci_uc_priv
*uc_priv
, u8 port
,
505 unsigned char *buf
, int buf_len
)
507 struct ahci_ioports
*pp
= &(uc_priv
->port
[port
]);
508 struct ahci_sg
*ahci_sg
= pp
->cmd_tbl_sg
;
512 sg_count
= ((buf_len
- 1) / MAX_DATA_BYTE_COUNT
) + 1;
513 if (sg_count
> AHCI_MAX_SG
) {
514 printf("Error:Too much sg!\n");
518 for (i
= 0; i
< sg_count
; i
++) {
520 cpu_to_le32((unsigned long) buf
+ i
* MAX_DATA_BYTE_COUNT
);
521 ahci_sg
->addr_hi
= 0;
522 ahci_sg
->flags_size
= cpu_to_le32(0x3fffff &
523 (buf_len
< MAX_DATA_BYTE_COUNT
525 : (MAX_DATA_BYTE_COUNT
- 1)));
527 buf_len
-= MAX_DATA_BYTE_COUNT
;
534 static void ahci_fill_cmd_slot(struct ahci_ioports
*pp
, u32 opts
)
536 pp
->cmd_slot
->opts
= cpu_to_le32(opts
);
537 pp
->cmd_slot
->status
= 0;
538 pp
->cmd_slot
->tbl_addr
= cpu_to_le32((u32
)pp
->cmd_tbl
& 0xffffffff);
539 #ifdef CONFIG_PHYS_64BIT
540 pp
->cmd_slot
->tbl_addr_hi
=
541 cpu_to_le32((u32
)(((pp
->cmd_tbl
) >> 16) >> 16));
545 static int wait_spinup(void __iomem
*port_mmio
)
550 start
= get_timer(0);
552 tf_data
= readl(port_mmio
+ PORT_TFDATA
);
553 if (!(tf_data
& ATA_BUSY
))
555 } while (get_timer(start
) < WAIT_MS_SPINUP
);
560 static int ahci_port_start(struct ahci_uc_priv
*uc_priv
, u8 port
)
562 struct ahci_ioports
*pp
= &(uc_priv
->port
[port
]);
563 void __iomem
*port_mmio
= pp
->port_mmio
;
567 debug("Enter start port: %d\n", port
);
568 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
569 debug("Port %d status: %x\n", port
, port_status
);
570 if ((port_status
& 0xf) != 0x03) {
571 printf("No Link on this port!\n");
575 mem
= malloc(AHCI_PORT_PRIV_DMA_SZ
+ 2048);
578 printf("%s: No mem for table!\n", __func__
);
582 /* Aligned to 2048-bytes */
583 mem
= memalign(2048, AHCI_PORT_PRIV_DMA_SZ
);
584 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
587 * First item in chunk of DMA memory: 32-slot command table,
588 * 32 bytes each in size
591 (struct ahci_cmd_hdr
*)(uintptr_t)virt_to_phys((void *)mem
);
592 debug("cmd_slot = %p\n", pp
->cmd_slot
);
593 mem
+= (AHCI_CMD_SLOT_SZ
+ 224);
596 * Second item: Received-FIS area
598 pp
->rx_fis
= virt_to_phys((void *)mem
);
599 mem
+= AHCI_RX_FIS_SZ
;
602 * Third item: data area for storing a single command
603 * and its scatter-gather table
605 pp
->cmd_tbl
= virt_to_phys((void *)mem
);
606 debug("cmd_tbl_dma = %lx\n", pp
->cmd_tbl
);
608 mem
+= AHCI_CMD_TBL_HDR
;
610 (struct ahci_sg
*)(uintptr_t)virt_to_phys((void *)mem
);
612 writel_with_flush((unsigned long)pp
->cmd_slot
,
613 port_mmio
+ PORT_LST_ADDR
);
615 writel_with_flush(pp
->rx_fis
, port_mmio
+ PORT_FIS_ADDR
);
617 #ifdef CONFIG_SUNXI_AHCI
618 sunxi_dma_init(port_mmio
);
621 writel_with_flush(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
622 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
623 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
625 debug("Exit start port %d\n", port
);
628 * Make sure interface is not busy based on error and status
629 * information from task file data register before proceeding
631 return wait_spinup(port_mmio
);
635 static int ahci_device_data_io(struct ahci_uc_priv
*uc_priv
, u8 port
, u8
*fis
,
636 int fis_len
, u8
*buf
, int buf_len
, u8 is_write
)
639 struct ahci_ioports
*pp
= &(uc_priv
->port
[port
]);
640 void __iomem
*port_mmio
= pp
->port_mmio
;
645 debug("Enter %s: for port %d\n", __func__
, port
);
647 if (port
> uc_priv
->n_ports
) {
648 printf("Invalid port number %d\n", port
);
652 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
653 if ((port_status
& 0xf) != 0x03) {
654 debug("No Link on port %d!\n", port
);
658 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, fis_len
);
660 sg_count
= ahci_fill_sg(uc_priv
, port
, buf
, buf_len
);
661 opts
= (fis_len
>> 2) | (sg_count
<< 16) | (is_write
<< 6);
662 ahci_fill_cmd_slot(pp
, opts
);
664 ahci_dcache_flush_sata_cmd(pp
);
665 ahci_dcache_flush_range((unsigned long)buf
, (unsigned long)buf_len
);
667 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
669 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
670 WAIT_MS_DATAIO
, 0x1)) {
671 printf("timeout exit!\n");
675 ahci_dcache_invalidate_range((unsigned long)buf
,
676 (unsigned long)buf_len
);
677 debug("%s: %d byte transferred.\n", __func__
, pp
->cmd_slot
->status
);
683 static char *ata_id_strcpy(u16
*target
, u16
*src
, int len
)
686 for (i
= 0; i
< len
/ 2; i
++)
687 target
[i
] = swab16(src
[i
]);
688 return (char *)target
;
692 * SCSI INQUIRY command operation.
694 static int ata_scsiop_inquiry(struct ahci_uc_priv
*uc_priv
,
695 struct scsi_cmd
*pccb
)
697 static const u8 hdr
[] = {
700 0x5, /* claim SPC-3 version compatibility */
706 ALLOC_CACHE_ALIGN_BUFFER(u16
, tmpid
, ATA_ID_WORDS
);
709 /* Clean ccb data buffer */
710 memset(pccb
->pdata
, 0, pccb
->datalen
);
712 memcpy(pccb
->pdata
, hdr
, sizeof(hdr
));
714 if (pccb
->datalen
<= 35)
717 memset(fis
, 0, sizeof(fis
));
718 /* Construct the FIS */
719 fis
[0] = 0x27; /* Host to device FIS. */
720 fis
[1] = 1 << 7; /* Command FIS. */
721 fis
[2] = ATA_CMD_ID_ATA
; /* Command byte. */
723 /* Read id from sata */
726 if (ahci_device_data_io(uc_priv
, port
, (u8
*)&fis
, sizeof(fis
),
727 (u8
*)tmpid
, ATA_ID_WORDS
* 2, 0)) {
728 debug("scsi_ahci: SCSI inquiry command failure.\n");
732 if (!uc_priv
->ataid
[port
]) {
733 uc_priv
->ataid
[port
] = malloc(ATA_ID_WORDS
* 2);
734 if (!uc_priv
->ataid
[port
]) {
735 printf("%s: No memory for ataid[port]\n", __func__
);
740 idbuf
= uc_priv
->ataid
[port
];
742 memcpy(idbuf
, tmpid
, ATA_ID_WORDS
* 2);
743 ata_swap_buf_le16(idbuf
, ATA_ID_WORDS
);
745 memcpy(&pccb
->pdata
[8], "ATA ", 8);
746 ata_id_strcpy((u16
*)&pccb
->pdata
[16], &idbuf
[ATA_ID_PROD
], 16);
747 ata_id_strcpy((u16
*)&pccb
->pdata
[32], &idbuf
[ATA_ID_FW_REV
], 4);
757 * SCSI READ10/WRITE10 command operation.
759 static int ata_scsiop_read_write(struct ahci_uc_priv
*uc_priv
,
760 struct scsi_cmd
*pccb
, u8 is_write
)
765 u8
*user_buffer
= pccb
->pdata
;
766 u32 user_buffer_size
= pccb
->datalen
;
768 /* Retrieve the base LBA number from the ccb structure. */
769 if (pccb
->cmd
[0] == SCSI_READ16
) {
770 memcpy(&lba
, pccb
->cmd
+ 2, 8);
771 lba
= be64_to_cpu(lba
);
774 memcpy(&temp
, pccb
->cmd
+ 2, 4);
775 lba
= be32_to_cpu(temp
);
779 * Retrieve the base LBA number and the block count from
782 * For 10-byte and 16-byte SCSI R/W commands, transfer
783 * length 0 means transfer 0 block of data.
784 * However, for ATA R/W commands, sector count 0 means
785 * 256 or 65536 sectors, not 0 sectors as in SCSI.
787 * WARNING: one or two older ATA drives treat 0 as 0...
789 if (pccb
->cmd
[0] == SCSI_READ16
)
790 blocks
= (((u16
)pccb
->cmd
[13]) << 8) | ((u16
) pccb
->cmd
[14]);
792 blocks
= (((u16
)pccb
->cmd
[7]) << 8) | ((u16
) pccb
->cmd
[8]);
794 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU
"\n",
795 is_write
? "write" : "read", blocks
, lba
);
798 memset(fis
, 0, sizeof(fis
));
799 fis
[0] = 0x27; /* Host to device FIS. */
800 fis
[1] = 1 << 7; /* Command FIS. */
801 /* Command byte (read/write). */
802 fis
[2] = is_write
? ATA_CMD_WRITE_EXT
: ATA_CMD_READ_EXT
;
805 u16 now_blocks
; /* number of blocks per iteration */
806 u32 transfer_size
; /* number of bytes per iteration */
808 now_blocks
= min((u16
)MAX_SATA_BLOCKS_READ_WRITE
, blocks
);
810 transfer_size
= ATA_SECT_SIZE
* now_blocks
;
811 if (transfer_size
> user_buffer_size
) {
812 printf("scsi_ahci: Error: buffer too small.\n");
817 * LBA48 SATA command but only use 32bit address range within
818 * that (unless we've enabled 64bit LBA support). The next
819 * smaller command range (28bit) is too small.
821 fis
[4] = (lba
>> 0) & 0xff;
822 fis
[5] = (lba
>> 8) & 0xff;
823 fis
[6] = (lba
>> 16) & 0xff;
824 fis
[7] = 1 << 6; /* device reg: set LBA mode */
825 fis
[8] = ((lba
>> 24) & 0xff);
826 #ifdef CONFIG_SYS_64BIT_LBA
827 if (pccb
->cmd
[0] == SCSI_READ16
) {
828 fis
[9] = ((lba
>> 32) & 0xff);
829 fis
[10] = ((lba
>> 40) & 0xff);
833 fis
[3] = 0xe0; /* features */
835 /* Block (sector) count */
836 fis
[12] = (now_blocks
>> 0) & 0xff;
837 fis
[13] = (now_blocks
>> 8) & 0xff;
839 /* Read/Write from ahci */
840 if (ahci_device_data_io(uc_priv
, pccb
->target
, (u8
*)&fis
,
841 sizeof(fis
), user_buffer
, transfer_size
,
843 debug("scsi_ahci: SCSI %s10 command failure.\n",
844 is_write
? "WRITE" : "READ");
848 /* If this transaction is a write, do a following flush.
849 * Writes in u-boot are so rare, and the logic to know when is
850 * the last write and do a flush only there is sufficiently
851 * difficult. Just do a flush after every write. This incurs,
852 * usually, one extra flush when the rare writes do happen.
855 if (-EIO
== ata_io_flush(uc_priv
, pccb
->target
))
858 user_buffer
+= transfer_size
;
859 user_buffer_size
-= transfer_size
;
860 blocks
-= now_blocks
;
869 * SCSI READ CAPACITY10 command operation.
871 static int ata_scsiop_read_capacity10(struct ahci_uc_priv
*uc_priv
,
872 struct scsi_cmd
*pccb
)
878 if (!uc_priv
->ataid
[pccb
->target
]) {
879 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
881 "\tPlease run SCSI command INQUIRY first!\n");
885 cap64
= ata_id_n_sectors(uc_priv
->ataid
[pccb
->target
]);
886 if (cap64
> 0x100000000ULL
)
889 cap
= cpu_to_be32(cap64
);
890 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
892 block_size
= cpu_to_be32((u32
)512);
893 memcpy(&pccb
->pdata
[4], &block_size
, 4);
900 * SCSI READ CAPACITY16 command operation.
902 static int ata_scsiop_read_capacity16(struct ahci_uc_priv
*uc_priv
,
903 struct scsi_cmd
*pccb
)
908 if (!uc_priv
->ataid
[pccb
->target
]) {
909 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
911 "\tPlease run SCSI command INQUIRY first!\n");
915 cap
= ata_id_n_sectors(uc_priv
->ataid
[pccb
->target
]);
916 cap
= cpu_to_be64(cap
);
917 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
919 block_size
= cpu_to_be64((u64
)512);
920 memcpy(&pccb
->pdata
[8], &block_size
, 8);
927 * SCSI TEST UNIT READY command operation.
929 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv
*uc_priv
,
930 struct scsi_cmd
*pccb
)
932 return (uc_priv
->ataid
[pccb
->target
]) ? 0 : -EPERM
;
936 int scsi_exec(struct scsi_cmd
*pccb
)
938 struct ahci_uc_priv
*uc_priv
= probe_ent
;
941 switch (pccb
->cmd
[0]) {
944 ret
= ata_scsiop_read_write(uc_priv
, pccb
, 0);
947 ret
= ata_scsiop_read_write(uc_priv
, pccb
, 1);
949 case SCSI_RD_CAPAC10
:
950 ret
= ata_scsiop_read_capacity10(uc_priv
, pccb
);
952 case SCSI_RD_CAPAC16
:
953 ret
= ata_scsiop_read_capacity16(uc_priv
, pccb
);
956 ret
= ata_scsiop_test_unit_ready(uc_priv
, pccb
);
959 ret
= ata_scsiop_inquiry(uc_priv
, pccb
);
962 printf("Unsupport SCSI command 0x%02x\n", pccb
->cmd
[0]);
967 debug("SCSI command 0x%02x ret errno %d\n", pccb
->cmd
[0], ret
);
974 static int ahci_start_ports(struct ahci_uc_priv
*uc_priv
)
979 linkmap
= uc_priv
->link_port_map
;
981 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
982 if (((linkmap
>> i
) & 0x01)) {
983 if (ahci_port_start(uc_priv
, (u8
) i
)) {
984 printf("Can not start port %d\n", i
);
993 #if defined(CONFIG_DM_SCSI)
994 void scsi_low_level_init(int busdevfunc
, struct udevice
*dev
)
996 void scsi_low_level_init(int busdevfunc
)
999 struct ahci_uc_priv
*uc_priv
;
1001 #ifndef CONFIG_SCSI_AHCI_PLAT
1002 # if defined(CONFIG_DM_PCI)
1003 struct udevice
*dev
;
1006 ret
= dm_pci_bus_find_bdf(busdevfunc
, &dev
);
1010 # elif defined(CONFIG_DM_SCSI)
1013 ahci_init_one(busdevfunc
);
1016 uc_priv
= probe_ent
;
1018 ahci_start_ports(uc_priv
);
1021 #ifdef CONFIG_SCSI_AHCI_PLAT
1022 int ahci_init(void __iomem
*base
)
1024 struct ahci_uc_priv
*uc_priv
;
1027 probe_ent
= malloc(sizeof(struct ahci_uc_priv
));
1029 printf("%s: No memory for uc_priv\n", __func__
);
1033 uc_priv
= probe_ent
;
1034 memset(uc_priv
, 0, sizeof(struct ahci_uc_priv
));
1036 uc_priv
->host_flags
= ATA_FLAG_SATA
1037 | ATA_FLAG_NO_LEGACY
1040 | ATA_FLAG_NO_ATAPI
;
1041 uc_priv
->pio_mask
= 0x1f;
1042 uc_priv
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
1044 uc_priv
->mmio_base
= base
;
1046 /* initialize adapter */
1047 rc
= ahci_host_init(uc_priv
);
1051 ahci_print_info(uc_priv
);
1053 rc
= ahci_start_ports(uc_priv
);
1059 void __weak
scsi_init(void)
1066 * In the general case of generic rotating media it makes sense to have a
1067 * flush capability. It probably even makes sense in the case of SSDs because
1068 * one cannot always know for sure what kind of internal cache/flush mechanism
1069 * is embodied therein. At first it was planned to invoke this after the last
1070 * write to disk and before rebooting. In practice, knowing, a priori, which
1071 * is the last write is difficult. Because writing to the disk in u-boot is
1072 * very rare, this flush command will be invoked after every block write.
1074 static int ata_io_flush(struct ahci_uc_priv
*uc_priv
, u8 port
)
1077 struct ahci_ioports
*pp
= &(uc_priv
->port
[port
]);
1078 void __iomem
*port_mmio
= pp
->port_mmio
;
1079 u32 cmd_fis_len
= 5; /* five dwords */
1081 /* Preset the FIS */
1083 fis
[0] = 0x27; /* Host to device FIS. */
1084 fis
[1] = 1 << 7; /* Command FIS. */
1085 fis
[2] = ATA_CMD_FLUSH_EXT
;
1087 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, 20);
1088 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
1089 ahci_dcache_flush_sata_cmd(pp
);
1090 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
1092 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
1093 WAIT_MS_FLUSH
, 0x1)) {
1094 debug("scsi_ahci: flush command timeout on port %d.\n", port
);
1102 __weak
void scsi_bus_reset(void)