drivers/ata/dwc_ahsata.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  * Terry Lv <r65388@freescale.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <ahci.h>
  10 #include <dm.h>
  11 #include <dwc_ahsata.h>
  12 #include <fis.h>
  13 #include <libata.h>
  14 #include <malloc.h>
  15 #include <memalign.h>
  16 #include <sata.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <linux/bitops.h>
  21 #include <linux/ctype.h>
  22 #include <linux/errno.h>
  23 #include "dwc_ahsata_priv.h"
  24
  25 struct sata_port_regs {
  26         u32 clb;
  27         u32 clbu;
  28         u32 fb;
  29         u32 fbu;
  30         u32 is;
  31         u32 ie;
  32         u32 cmd;
  33         u32 res1[1];
  34         u32 tfd;
  35         u32 sig;
  36         u32 ssts;
  37         u32 sctl;
  38         u32 serr;
  39         u32 sact;
  40         u32 ci;
  41         u32 sntf;
  42         u32 res2[1];
  43         u32 dmacr;
  44         u32 res3[1];
  45         u32 phycr;
  46         u32 physr;
  47 };
  48
  49 struct sata_host_regs {
  50         u32 cap;
  51         u32 ghc;
  52         u32 is;
  53         u32 pi;
  54         u32 vs;
  55         u32 ccc_ctl;
  56         u32 ccc_ports;
  57         u32 res1[2];
  58         u32 cap2;
  59         u32 res2[30];
  60         u32 bistafr;
  61         u32 bistcr;
  62         u32 bistfctr;
  63         u32 bistsr;
  64         u32 bistdecr;
  65         u32 res3[2];
  66         u32 oobr;
  67         u32 res4[8];
  68         u32 timer1ms;
  69         u32 res5[1];
  70         u32 gparam1r;
  71         u32 gparam2r;
  72         u32 pparamr;
  73         u32 testr;
  74         u32 versionr;
  75         u32 idr;
  76 };
  77
  78 #define MAX_DATA_BYTES_PER_SG  (4 * 1024 * 1024)
  79 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
  80
  81 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
  82
  83 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
  84 {
  85         return base + 0x100 + (port * 0x80);
  86 }
  87
  88 static int waiting_for_cmd_completed(u8 *offset,
  89                                         int timeout_msec,
  90                                         u32 sign)
  91 {
  92         int i;
  93         u32 status;
  94
  95         for (i = 0;
  96                 ((status = readl(offset)) & sign) && i < timeout_msec;
  97                 ++i)
  98                 mdelay(1);
  99
 100         return (i < timeout_msec) ? 0 : -1;
 101 }
 102
 103 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
 104 {
 105         struct sata_host_regs *host_mmio = uc_priv->mmio_base;
 106
 107         writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
 108         writel(0x02060b14, &host_mmio->oobr);
 109
 110         return 0;
 111 }
 112
 113 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
 114 {
 115         u32 tmp, cap_save, num_ports;
 116         int i, j, timeout = 1000;
 117         struct sata_port_regs *port_mmio = NULL;
 118         struct sata_host_regs *host_mmio = uc_priv->mmio_base;
 119         int clk = mxc_get_clock(MXC_SATA_CLK);
 120
 121         cap_save = readl(&host_mmio->cap);
 122         cap_save |= SATA_HOST_CAP_SSS;
 123
 124         /* global controller reset */
 125         tmp = readl(&host_mmio->ghc);
 126         if ((tmp & SATA_HOST_GHC_HR) == 0)
 127                 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
 128
 129         while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
 130                 ;
 131
 132         if (timeout <= 0) {
 133                 debug("controller reset failed (0x%x)\n", tmp);
 134                 return -1;
 135         }
 136
 137         /* Set timer 1ms */
 138         writel(clk / 1000, &host_mmio->timer1ms);
 139
 140         ahci_setup_oobr(uc_priv, 0);
 141
 142         writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
 143         writel(cap_save, &host_mmio->cap);
 144         num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
 145         writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
 146
 147         /*
 148          * Determine which Ports are implemented by the DWC_ahsata,
 149          * by reading the PI register. This bit map value aids the
 150          * software to determine how many Ports are available and
 151          * which Port registers need to be initialized.
 152          */
 153         uc_priv->cap = readl(&host_mmio->cap);
 154         uc_priv->port_map = readl(&host_mmio->pi);
 155
 156         /* Determine how many command slots the HBA supports */
 157         uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
 158
 159         debug("cap 0x%x  port_map 0x%x  n_ports %d\n",
 160                 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
 161
 162         for (i = 0; i < uc_priv->n_ports; i++) {
 163                 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
 164                 port_mmio = uc_priv->port[i].port_mmio;
 165
 166                 /* Ensure that the DWC_ahsata is in idle state */
 167                 tmp = readl(&port_mmio->cmd);
 168
 169                 /*
 170                  * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
 171                  * are all cleared, the Port is in an idle state.
 172                  */
 173                 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
 174                         SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
 175
 176                         /*
 177                          * System software places a Port into the idle state by
 178                          * clearing P#CMD.ST and waiting for P#CMD.CR to return
 179                          * 0 when read.
 180                          */
 181                         tmp &= ~SATA_PORT_CMD_ST;
 182                         writel_with_flush(tmp, &port_mmio->cmd);
 183
 184                         /*
 185                          * spec says 500 msecs for each bit, so
 186                          * this is slightly incorrect.
 187                          */
 188                         mdelay(500);
 189
 190                         timeout = 1000;
 191                         while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
 192                                 && --timeout)
 193                                 ;
 194
 195                         if (timeout <= 0) {
 196                                 debug("port reset failed (0x%x)\n", tmp);
 197                                 return -1;
 198                         }
 199                 }
 200
 201                 /* Spin-up device */
 202                 tmp = readl(&port_mmio->cmd);
 203                 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
 204
 205                 /* Wait for spin-up to finish */
 206                 timeout = 1000;
 207                 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
 208                         && --timeout)
 209                         ;
 210                 if (timeout <= 0) {
 211                         debug("Spin-Up can't finish!\n");
 212                         return -1;
 213                 }
 214
 215                 for (j = 0; j < 100; ++j) {
 216                         mdelay(10);
 217                         tmp = readl(&port_mmio->ssts);
 218                         if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
 219                                 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
 220                                 break;
 221                 }
 222
 223                 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
 224                 timeout = 1000;
 225                 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X)
 226                         && --timeout)
 227                         ;
 228                 if (timeout <= 0) {
 229                         debug("Can't find DIAG_X set!\n");
 230                         return -1;
 231                 }
 232
 233                 /*
 234                  * For each implemented Port, clear the P#SERR
 235                  * register, by writing ones to each implemented\
 236                  * bit location.
 237                  */
 238                 tmp = readl(&port_mmio->serr);
 239                 debug("P#SERR 0x%x\n",
 240                                 tmp);
 241                 writel(tmp, &port_mmio->serr);
 242
 243                 /* Ack any pending irq events for this port */
 244                 tmp = readl(&host_mmio->is);
 245                 debug("IS 0x%x\n", tmp);
 246                 if (tmp)
 247                         writel(tmp, &host_mmio->is);
 248
 249                 writel(1 << i, &host_mmio->is);
 250
 251                 /* set irq mask (enables interrupts) */
 252                 writel(DEF_PORT_IRQ, &port_mmio->ie);
 253
 254                 /* register linkup ports */
 255                 tmp = readl(&port_mmio->ssts);
 256                 debug("Port %d status: 0x%x\n", i, tmp);
 257                 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
 258                         uc_priv->link_port_map |= (0x01 << i);
 259         }
 260
 261         tmp = readl(&host_mmio->ghc);
 262         debug("GHC 0x%x\n", tmp);
 263         writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
 264         tmp = readl(&host_mmio->ghc);
 265         debug("GHC 0x%x\n", tmp);
 266
 267         return 0;
 268 }
 269
 270 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
 271 {
 272         struct sata_host_regs *host_mmio = uc_priv->mmio_base;
 273         u32 vers, cap, impl, speed;
 274         const char *speed_s;
 275         const char *scc_s;
 276
 277         vers = readl(&host_mmio->vs);
 278         cap = uc_priv->cap;
 279         impl = uc_priv->port_map;
 280
 281         speed = (cap & SATA_HOST_CAP_ISS_MASK)
 282                 >> SATA_HOST_CAP_ISS_OFFSET;
 283         if (speed == 1)
 284                 speed_s = "1.5";
 285         else if (speed == 2)
 286                 speed_s = "3";
 287         else
 288                 speed_s = "?";
 289
 290         scc_s = "SATA";
 291
 292         printf("AHCI %02x%02x.%02x%02x "
 293                 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
 294                 (vers >> 24) & 0xff,
 295                 (vers >> 16) & 0xff,
 296                 (vers >> 8) & 0xff,
 297                 vers & 0xff,
 298                 ((cap >> 8) & 0x1f) + 1,
 299                 (cap & 0x1f) + 1,
 300                 speed_s,
 301                 impl,
 302                 scc_s);
 303
 304         printf("flags: "
 305                 "%s%s%s%s%s%s"
 306                 "%s%s%s%s%s%s%s\n",
 307                 cap & (1 << 31) ? "64bit " : "",
 308                 cap & (1 << 30) ? "ncq " : "",
 309                 cap & (1 << 28) ? "ilck " : "",
 310                 cap & (1 << 27) ? "stag " : "",
 311                 cap & (1 << 26) ? "pm " : "",
 312                 cap & (1 << 25) ? "led " : "",
 313                 cap & (1 << 24) ? "clo " : "",
 314                 cap & (1 << 19) ? "nz " : "",
 315                 cap & (1 << 18) ? "only " : "",
 316                 cap & (1 << 17) ? "pmp " : "",
 317                 cap & (1 << 15) ? "pio " : "",
 318                 cap & (1 << 14) ? "slum " : "",
 319                 cap & (1 << 13) ? "part " : "");
 320 }
 321
 322 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
 323                         unsigned char *buf, int buf_len)
 324 {
 325         struct ahci_ioports *pp = &uc_priv->port[port];
 326         struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
 327         u32 sg_count, max_bytes;
 328         int i;
 329
 330         max_bytes = MAX_DATA_BYTES_PER_SG;
 331         sg_count = ((buf_len - 1) / max_bytes) + 1;
 332         if (sg_count > AHCI_MAX_SG) {
 333                 printf("Error:Too much sg!\n");
 334                 return -1;
 335         }
 336
 337         for (i = 0; i < sg_count; i++) {
 338                 ahci_sg->addr =
 339                         cpu_to_le32((u32)buf + i * max_bytes);
 340                 ahci_sg->addr_hi = 0;
 341                 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
 342                                         (buf_len < max_bytes
 343                                         ? (buf_len - 1)
 344                                         : (max_bytes - 1)));
 345                 ahci_sg++;
 346                 buf_len -= max_bytes;
 347         }
 348
 349         return sg_count;
 350 }
 351
 352 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
 353 {
 354         struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
 355                                         AHCI_CMD_SLOT_SZ * cmd_slot);
 356
 357         memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
 358         cmd_hdr->opts = cpu_to_le32(opts);
 359         cmd_hdr->status = 0;
 360         pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
 361 #ifdef CONFIG_PHYS_64BIT
 362         pp->cmd_slot->tbl_addr_hi =
 363             cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
 364 #endif
 365 }
 366
 367 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
 368
 369 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
 370                              struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
 371                              s32 is_write)
 372 {
 373         struct ahci_ioports *pp = &uc_priv->port[port];
 374         struct sata_port_regs *port_mmio = pp->port_mmio;
 375         u32 opts;
 376         int sg_count = 0, cmd_slot = 0;
 377
 378         cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
 379         if (32 == cmd_slot) {
 380                 printf("Can't find empty command slot!\n");
 381                 return 0;
 382         }
 383
 384         /* Check xfer length */
 385         if (buf_len > MAX_BYTES_PER_TRANS) {
 386                 printf("Max transfer length is %dB\n\r",
 387                         MAX_BYTES_PER_TRANS);
 388                 return 0;
 389         }
 390
 391         memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
 392         if (buf && buf_len)
 393                 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
 394         opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
 395         if (is_write) {
 396                 opts |= 0x40;
 397                 flush_cache((ulong)buf, buf_len);
 398         }
 399         ahci_fill_cmd_slot(pp, cmd_slot, opts);
 400
 401         flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
 402         writel_with_flush(1 << cmd_slot, &port_mmio->ci);
 403
 404         if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
 405                                       0x1 << cmd_slot)) {
 406                 printf("timeout exit!\n");
 407                 return -1;
 408         }
 409         invalidate_dcache_range((int)(pp->cmd_slot),
 410                                 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
 411         debug("ahci_exec_ata_cmd: %d byte transferred.\n",
 412               pp->cmd_slot->status);
 413         if (!is_write)
 414                 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
 415
 416         return buf_len;
 417 }
 418
 419 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
 420 {
 421         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 422         struct sata_fis_h2d *cfis = &h2d;
 423
 424         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 425         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 426         cfis->pm_port_c = 1 << 7;
 427         cfis->command = ATA_CMD_SET_FEATURES;
 428         cfis->features = SETFEATURES_XFER;
 429         cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
 430
 431         ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
 432 }
 433
 434 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 435 {
 436         struct ahci_ioports *pp = &uc_priv->port[port];
 437         struct sata_port_regs *port_mmio = pp->port_mmio;
 438         u32 port_status;
 439         u32 mem;
 440         int timeout = 10000000;
 441
 442         debug("Enter start port: %d\n", port);
 443         port_status = readl(&port_mmio->ssts);
 444         debug("Port %d status: %x\n", port, port_status);
 445         if ((port_status & 0xf) != 0x03) {
 446                 printf("No Link on this port!\n");
 447                 return -1;
 448         }
 449
 450         mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
 451         if (!mem) {
 452                 free(pp);
 453                 printf("No mem for table!\n");
 454                 return -ENOMEM;
 455         }
 456
 457         mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
 458         memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
 459
 460         /*
 461          * First item in chunk of DMA memory: 32-slot command table,
 462          * 32 bytes each in size
 463          */
 464         pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
 465         debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
 466         mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
 467
 468         /*
 469          * Second item: Received-FIS area, 256-Byte aligned
 470          */
 471         pp->rx_fis = mem;
 472         mem += AHCI_RX_FIS_SZ;
 473
 474         /*
 475          * Third item: data area for storing a single command
 476          * and its scatter-gather table
 477          */
 478         pp->cmd_tbl = mem;
 479         debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
 480
 481         mem += AHCI_CMD_TBL_HDR;
 482
 483         writel_with_flush(0x00004444, &port_mmio->dmacr);
 484         pp->cmd_tbl_sg = (struct ahci_sg *)mem;
 485         writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
 486         writel_with_flush(pp->rx_fis, &port_mmio->fb);
 487
 488         /* Enable FRE */
 489         writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
 490                           &port_mmio->cmd);
 491
 492         /* Wait device ready */
 493         while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
 494                 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
 495                 && --timeout)
 496                 ;
 497         if (timeout <= 0) {
 498                 debug("Device not ready for BSY, DRQ and"
 499                         "ERR in TFD!\n");
 500                 return -1;
 501         }
 502
 503         writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
 504                           PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
 505                           PORT_CMD_START, &port_mmio->cmd);
 506
 507         debug("Exit start port %d\n", port);
 508
 509         return 0;
 510 }
 511
 512 static void dwc_ahsata_print_info(struct blk_desc *pdev)
 513 {
 514         printf("SATA Device Info:\n\r");
 515 #ifdef CONFIG_SYS_64BIT_LBA
 516         printf("S/N: %s\n\rProduct model number: %s\n\r"
 517                 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
 518                 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
 519 #else
 520         printf("S/N: %s\n\rProduct model number: %s\n\r"
 521                 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
 522                 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
 523 #endif
 524 }
 525
 526 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
 527 {
 528         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 529         struct sata_fis_h2d *cfis = &h2d;
 530         u8 port = uc_priv->hard_port_no;
 531
 532         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 533
 534         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 535         cfis->pm_port_c = 0x80; /* is command */
 536         cfis->command = ATA_CMD_ID_ATA;
 537
 538         ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
 539                           READ_CMD);
 540         ata_swap_buf_le16(id, ATA_ID_WORDS);
 541 }
 542
 543 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
 544 {
 545         uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
 546         uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
 547         debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
 548 }
 549
 550 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
 551                              u32 blkcnt, u8 *buffer, int is_write)
 552 {
 553         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 554         struct sata_fis_h2d *cfis = &h2d;
 555         u8 port = uc_priv->hard_port_no;
 556         u32 block;
 557
 558         block = start;
 559
 560         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 561
 562         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 563         cfis->pm_port_c = 0x80; /* is command */
 564         cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
 565         cfis->device = ATA_LBA;
 566
 567         cfis->device |= (block >> 24) & 0xf;
 568         cfis->lba_high = (block >> 16) & 0xff;
 569         cfis->lba_mid = (block >> 8) & 0xff;
 570         cfis->lba_low = block & 0xff;
 571         cfis->sector_count = (u8)(blkcnt & 0xff);
 572
 573         if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
 574                               ATA_SECT_SIZE * blkcnt, is_write) > 0)
 575                 return blkcnt;
 576         else
 577                 return 0;
 578 }
 579
 580 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
 581 {
 582         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 583         struct sata_fis_h2d *cfis = &h2d;
 584         u8 port = uc_priv->hard_port_no;
 585
 586         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 587
 588         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 589         cfis->pm_port_c = 0x80; /* is command */
 590         cfis->command = ATA_CMD_FLUSH;
 591
 592         ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
 593 }
 594
 595 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
 596                                  lbaint_t blkcnt, u8 *buffer, int is_write)
 597 {
 598         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 599         struct sata_fis_h2d *cfis = &h2d;
 600         u8 port = uc_priv->hard_port_no;
 601         u64 block;
 602
 603         block = (u64)start;
 604
 605         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 606
 607         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 608         cfis->pm_port_c = 0x80; /* is command */
 609
 610         cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
 611                                  : ATA_CMD_READ_EXT;
 612
 613         cfis->lba_high_exp = (block >> 40) & 0xff;
 614         cfis->lba_mid_exp = (block >> 32) & 0xff;
 615         cfis->lba_low_exp = (block >> 24) & 0xff;
 616         cfis->lba_high = (block >> 16) & 0xff;
 617         cfis->lba_mid = (block >> 8) & 0xff;
 618         cfis->lba_low = block & 0xff;
 619         cfis->device = ATA_LBA;
 620         cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
 621         cfis->sector_count = blkcnt & 0xff;
 622
 623         if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
 624                               ATA_SECT_SIZE * blkcnt, is_write) > 0)
 625                 return blkcnt;
 626         else
 627                 return 0;
 628 }
 629
 630 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
 631 {
 632         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 633         struct sata_fis_h2d *cfis = &h2d;
 634         u8 port = uc_priv->hard_port_no;
 635
 636         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 637
 638         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 639         cfis->pm_port_c = 0x80; /* is command */
 640         cfis->command = ATA_CMD_FLUSH_EXT;
 641
 642         ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
 643 }
 644
 645 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
 646 {
 647         if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
 648                 uc_priv->flags |= SATA_FLAG_WCACHE;
 649         if (ata_id_has_flush(id))
 650                 uc_priv->flags |= SATA_FLAG_FLUSH;
 651         if (ata_id_has_flush_ext(id))
 652                 uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
 653 }
 654
 655 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
 656                                   lbaint_t blkcnt, const void *buffer,
 657                                   int is_write)
 658 {
 659         u32 start, blks;
 660         u8 *addr;
 661         int max_blks;
 662
 663         start = blknr;
 664         blks = blkcnt;
 665         addr = (u8 *)buffer;
 666
 667         max_blks = ATA_MAX_SECTORS_LBA48;
 668
 669         do {
 670                 if (blks > max_blks) {
 671                         if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
 672                                                               max_blks, addr,
 673                                                               is_write))
 674                                 return 0;
 675                         start += max_blks;
 676                         blks -= max_blks;
 677                         addr += ATA_SECT_SIZE * max_blks;
 678                 } else {
 679                         if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
 680                                                           addr, is_write))
 681                                 return 0;
 682                         start += blks;
 683                         blks = 0;
 684                         addr += ATA_SECT_SIZE * blks;
 685                 }
 686         } while (blks != 0);
 687
 688         return blkcnt;
 689 }
 690
 691 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
 692                                   lbaint_t blkcnt, const void *buffer,
 693                                   int is_write)
 694 {
 695         u32 start, blks;
 696         u8 *addr;
 697         int max_blks;
 698
 699         start = blknr;
 700         blks = blkcnt;
 701         addr = (u8 *)buffer;
 702
 703         max_blks = ATA_MAX_SECTORS;
 704         do {
 705                 if (blks > max_blks) {
 706                         if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
 707                                                           max_blks, addr,
 708                                                           is_write))
 709                                 return 0;
 710                         start += max_blks;
 711                         blks -= max_blks;
 712                         addr += ATA_SECT_SIZE * max_blks;
 713                 } else {
 714                         if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
 715                                                       addr, is_write))
 716                                 return 0;
 717                         start += blks;
 718                         blks = 0;
 719                         addr += ATA_SECT_SIZE * blks;
 720                 }
 721         } while (blks != 0);
 722
 723         return blkcnt;
 724 }
 725
 726 static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
 727 {
 728         u32 linkmap;
 729         int i;
 730
 731         linkmap = uc_priv->link_port_map;
 732
 733         if (0 == linkmap) {
 734                 printf("No port device detected!\n");
 735                 return -ENXIO;
 736         }
 737
 738         for (i = 0; i < uc_priv->n_ports; i++) {
 739                 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
 740                         if (ahci_port_start(uc_priv, (u8)i)) {
 741                                 printf("Can not start port %d\n", i);
 742                                 return 1;
 743                         }
 744                         uc_priv->hard_port_no = i;
 745                         break;
 746                 }
 747         }
 748
 749         return 0;
 750 }
 751
 752 static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
 753                                   struct blk_desc *pdev)
 754 {
 755         u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
 756         u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
 757         u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
 758         u64 n_sectors;
 759         u8 port = uc_priv->hard_port_no;
 760         ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
 761
 762         /* Identify device to get information */
 763         dwc_ahsata_identify(uc_priv, id);
 764
 765         /* Serial number */
 766         ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
 767         memcpy(pdev->product, serial, sizeof(serial));
 768
 769         /* Firmware version */
 770         ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
 771         memcpy(pdev->revision, firmware, sizeof(firmware));
 772
 773         /* Product model */
 774         ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
 775         memcpy(pdev->vendor, product, sizeof(product));
 776
 777         /* Totoal sectors */
 778         n_sectors = ata_id_n_sectors(id);
 779         pdev->lba = (u32)n_sectors;
 780
 781         pdev->type = DEV_TYPE_HARDDISK;
 782         pdev->blksz = ATA_SECT_SIZE;
 783         pdev->lun = 0;
 784
 785         /* Check if support LBA48 */
 786         if (ata_id_has_lba48(id)) {
 787                 pdev->lba48 = 1;
 788                 debug("Device support LBA48\n\r");
 789         }
 790
 791         /* Get the NCQ queue depth from device */
 792         uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
 793         uc_priv->flags |= ata_id_queue_depth(id);
 794
 795         /* Get the xfer mode from device */
 796         dwc_ahsata_xfer_mode(uc_priv, id);
 797
 798         /* Get the write cache status from device */
 799         dwc_ahsata_init_wcache(uc_priv, id);
 800
 801         /* Set the xfer mode to highest speed */
 802         ahci_set_feature(uc_priv, port);
 803
 804         dwc_ahsata_print_info(pdev);
 805
 806         return 0;
 807 }
 808
 809 /*
 810  * SATA interface between low level driver and command layer
 811  */
 812 static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
 813                               struct blk_desc *desc, ulong blknr,
 814                               lbaint_t blkcnt, void *buffer)
 815 {
 816         u32 rc;
 817
 818         if (desc->lba48)
 819                 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
 820                                             READ_CMD);
 821         else
 822                 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
 823                                             READ_CMD);
 824
 825         return rc;
 826 }
 827
 828 static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
 829                                struct blk_desc *desc, ulong blknr,
 830                                lbaint_t blkcnt, const void *buffer)
 831 {
 832         u32 rc;
 833         u32 flags = uc_priv->flags;
 834
 835         if (desc->lba48) {
 836                 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
 837                                             WRITE_CMD);
 838                 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
 839                         dwc_ahsata_flush_cache_ext(uc_priv);
 840         } else {
 841                 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
 842                                             WRITE_CMD);
 843                 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
 844                         dwc_ahsata_flush_cache(uc_priv);
 845         }
 846
 847         return rc;
 848 }
 849
 850 #if !CONFIG_IS_ENABLED(AHCI)
 851 static int ahci_init_one(int pdev)
 852 {
 853         int rc;
 854         struct ahci_uc_priv *uc_priv = NULL;
 855
 856         uc_priv = malloc(sizeof(struct ahci_uc_priv));
 857         memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
 858         uc_priv->dev = pdev;
 859
 860         uc_priv->host_flags = ATA_FLAG_SATA
 861                                 | ATA_FLAG_NO_LEGACY
 862                                 | ATA_FLAG_MMIO
 863                                 | ATA_FLAG_PIO_DMA
 864                                 | ATA_FLAG_NO_ATAPI;
 865
 866         uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
 867
 868         /* initialize adapter */
 869         rc = ahci_host_init(uc_priv);
 870         if (rc)
 871                 goto err_out;
 872
 873         ahci_print_info(uc_priv);
 874
 875         /* Save the uc_private struct to block device struct */
 876         sata_dev_desc[pdev].priv = uc_priv;
 877
 878         return 0;
 879
 880 err_out:
 881         return rc;
 882 }
 883
 884 int init_sata(int dev)
 885 {
 886         struct ahci_uc_priv *uc_priv = NULL;
 887
 888 #if defined(CONFIG_MX6)
 889         if (!is_mx6dq() && !is_mx6dqp())
 890                 return 1;
 891 #endif
 892         if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
 893                 printf("The sata index %d is out of ranges\n\r", dev);
 894                 return -1;
 895         }
 896
 897         ahci_init_one(dev);
 898
 899         uc_priv = sata_dev_desc[dev].priv;
 900
 901         return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
 902 }
 903
 904 int reset_sata(int dev)
 905 {
 906         struct ahci_uc_priv *uc_priv;
 907         struct sata_host_regs *host_mmio;
 908
 909         if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
 910                 printf("The sata index %d is out of ranges\n\r", dev);
 911                 return -1;
 912         }
 913
 914         uc_priv = sata_dev_desc[dev].priv;
 915         if (NULL == uc_priv)
 916                 /* not initialized, so nothing to reset */
 917                 return 0;
 918
 919         host_mmio = uc_priv->mmio_base;
 920         setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
 921         while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
 922                 udelay(100);
 923
 924         return 0;
 925 }
 926
 927 int sata_port_status(int dev, int port)
 928 {
 929         struct sata_port_regs *port_mmio;
 930         struct ahci_uc_priv *uc_priv = NULL;
 931
 932         if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
 933                 return -EINVAL;
 934
 935         if (sata_dev_desc[dev].priv == NULL)
 936                 return -ENODEV;
 937
 938         uc_priv = sata_dev_desc[dev].priv;
 939         port_mmio = uc_priv->port[port].port_mmio;
 940
 941         return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
 942 }
 943
 944 /*
 945  * SATA interface between low level driver and command layer
 946  */
 947 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
 948 {
 949         struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
 950
 951         return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
 952                                 buffer);
 953 }
 954
 955 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
 956 {
 957         struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
 958
 959         return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
 960                                  buffer);
 961 }
 962
 963 int scan_sata(int dev)
 964 {
 965         struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
 966         struct blk_desc *pdev = &sata_dev_desc[dev];
 967
 968         return dwc_ahsata_scan_common(uc_priv, pdev);
 969 }
 970 #endif /* CONFIG_IS_ENABLED(AHCI) */
 971
 972 #if CONFIG_IS_ENABLED(AHCI)
 973
 974 int dwc_ahsata_port_status(struct udevice *dev, int port)
 975 {
 976         struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 977         struct sata_port_regs *port_mmio;
 978
 979         port_mmio = uc_priv->port[port].port_mmio;
 980         return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
 981 }
 982
 983 int dwc_ahsata_bus_reset(struct udevice *dev)
 984 {
 985         struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 986         struct sata_host_regs *host_mmio = uc_priv->mmio_base;
 987
 988         setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
 989         while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
 990                 udelay(100);
 991
 992         return 0;
 993 }
 994
 995 int dwc_ahsata_scan(struct udevice *dev)
 996 {
 997         struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 998         struct blk_desc *desc;
 999         struct udevice *blk;
1000         int ret;
1001
1002         /*
1003         * Create only one block device and do detection
1004         * to make sure that there won't be a lot of
1005         * block devices created
1006         */
1007         device_find_first_child(dev, &blk);
1008         if (!blk) {
1009                 ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
1010                                          IF_TYPE_SATA, -1, 512, 0, &blk);
1011                 if (ret) {
1012                         debug("Can't create device\n");
1013                         return ret;
1014                 }
1015         }
1016
1017         desc = dev_get_uclass_platdata(blk);
1018         ret = dwc_ahsata_scan_common(uc_priv, desc);
1019         if (ret) {
1020                 debug("%s: Failed to scan bus\n", __func__);
1021                 return ret;
1022         }
1023
1024         return 0;
1025 }
1026
1027 int dwc_ahsata_probe(struct udevice *dev)
1028 {
1029         struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1030         int ret;
1031
1032         uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
1033                         ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
1034         uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
1035
1036         /* initialize adapter */
1037         ret = ahci_host_init(uc_priv);
1038         if (ret)
1039                 return ret;
1040
1041         ahci_print_info(uc_priv);
1042
1043         return dwc_ahci_start_ports(uc_priv);
1044 }
1045
1046 static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
1047                              lbaint_t blkcnt, void *buffer)
1048 {
1049         struct blk_desc *desc = dev_get_uclass_platdata(blk);
1050         struct udevice *dev = dev_get_parent(blk);
1051         struct ahci_uc_priv *uc_priv;
1052
1053         uc_priv = dev_get_uclass_priv(dev);
1054         return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
1055 }
1056
1057 static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
1058                               lbaint_t blkcnt, const void *buffer)
1059 {
1060         struct blk_desc *desc = dev_get_uclass_platdata(blk);
1061         struct udevice *dev = dev_get_parent(blk);
1062         struct ahci_uc_priv *uc_priv;
1063
1064         uc_priv = dev_get_uclass_priv(dev);
1065         return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
1066 }
1067
1068 static const struct blk_ops dwc_ahsata_blk_ops = {
1069         .read   = dwc_ahsata_read,
1070         .write  = dwc_ahsata_write,
1071 };
1072
1073 U_BOOT_DRIVER(dwc_ahsata_blk) = {
1074         .name           = "dwc_ahsata_blk",
1075         .id             = UCLASS_BLK,
1076         .ops            = &dwc_ahsata_blk_ops,
1077 };
1078
1079 #endif