1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * libata-sff.c - helper library for PCI IDE BMDMA
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
10 * Copyright 2003-2006 Jeff Garzik
12 * libata documentation is available via 'make {ps|pdf}docs',
13 * as Documentation/driver-api/libata.rst
15 * Hardware documentation available from http://www.t13.org/ and
16 * http://www.sata-io.org/
19 #include <linux/kernel.h>
20 #include <linux/gfp.h>
21 #include <linux/pci.h>
22 #include <linux/module.h>
23 #include <linux/libata.h>
24 #include <linux/highmem.h>
28 static struct workqueue_struct
*ata_sff_wq
;
30 const struct ata_port_operations ata_sff_port_ops
= {
31 .inherits
= &ata_base_port_ops
,
33 .qc_prep
= ata_noop_qc_prep
,
34 .qc_issue
= ata_sff_qc_issue
,
35 .qc_fill_rtf
= ata_sff_qc_fill_rtf
,
37 .freeze
= ata_sff_freeze
,
39 .prereset
= ata_sff_prereset
,
40 .softreset
= ata_sff_softreset
,
41 .hardreset
= sata_sff_hardreset
,
42 .postreset
= ata_sff_postreset
,
43 .error_handler
= ata_sff_error_handler
,
45 .sff_dev_select
= ata_sff_dev_select
,
46 .sff_check_status
= ata_sff_check_status
,
47 .sff_tf_load
= ata_sff_tf_load
,
48 .sff_tf_read
= ata_sff_tf_read
,
49 .sff_exec_command
= ata_sff_exec_command
,
50 .sff_data_xfer
= ata_sff_data_xfer
,
51 .sff_drain_fifo
= ata_sff_drain_fifo
,
53 .lost_interrupt
= ata_sff_lost_interrupt
,
55 EXPORT_SYMBOL_GPL(ata_sff_port_ops
);
58 * ata_sff_check_status - Read device status reg & clear interrupt
59 * @ap: port where the device is
61 * Reads ATA taskfile status register for currently-selected device
62 * and return its value. This also clears pending interrupts
66 * Inherited from caller.
68 u8
ata_sff_check_status(struct ata_port
*ap
)
70 return ioread8(ap
->ioaddr
.status_addr
);
72 EXPORT_SYMBOL_GPL(ata_sff_check_status
);
75 * ata_sff_altstatus - Read device alternate status reg
76 * @ap: port where the device is
78 * Reads ATA taskfile alternate status register for
79 * currently-selected device and return its value.
81 * Note: may NOT be used as the check_altstatus() entry in
82 * ata_port_operations.
85 * Inherited from caller.
87 static u8
ata_sff_altstatus(struct ata_port
*ap
)
89 if (ap
->ops
->sff_check_altstatus
)
90 return ap
->ops
->sff_check_altstatus(ap
);
92 return ioread8(ap
->ioaddr
.altstatus_addr
);
96 * ata_sff_irq_status - Check if the device is busy
97 * @ap: port where the device is
99 * Determine if the port is currently busy. Uses altstatus
100 * if available in order to avoid clearing shared IRQ status
101 * when finding an IRQ source. Non ctl capable devices don't
102 * share interrupt lines fortunately for us.
105 * Inherited from caller.
107 static u8
ata_sff_irq_status(struct ata_port
*ap
)
111 if (ap
->ops
->sff_check_altstatus
|| ap
->ioaddr
.altstatus_addr
) {
112 status
= ata_sff_altstatus(ap
);
113 /* Not us: We are busy */
114 if (status
& ATA_BUSY
)
117 /* Clear INTRQ latch */
118 status
= ap
->ops
->sff_check_status(ap
);
123 * ata_sff_sync - Flush writes
124 * @ap: Port to wait for.
127 * If we have an mmio device with no ctl and no altstatus
128 * method this will fail. No such devices are known to exist.
131 * Inherited from caller.
134 static void ata_sff_sync(struct ata_port
*ap
)
136 if (ap
->ops
->sff_check_altstatus
)
137 ap
->ops
->sff_check_altstatus(ap
);
138 else if (ap
->ioaddr
.altstatus_addr
)
139 ioread8(ap
->ioaddr
.altstatus_addr
);
143 * ata_sff_pause - Flush writes and wait 400nS
144 * @ap: Port to pause for.
147 * If we have an mmio device with no ctl and no altstatus
148 * method this will fail. No such devices are known to exist.
151 * Inherited from caller.
154 void ata_sff_pause(struct ata_port
*ap
)
159 EXPORT_SYMBOL_GPL(ata_sff_pause
);
162 * ata_sff_dma_pause - Pause before commencing DMA
163 * @ap: Port to pause for.
165 * Perform I/O fencing and ensure sufficient cycle delays occur
166 * for the HDMA1:0 transition
169 void ata_sff_dma_pause(struct ata_port
*ap
)
171 if (ap
->ops
->sff_check_altstatus
|| ap
->ioaddr
.altstatus_addr
) {
172 /* An altstatus read will cause the needed delay without
173 messing up the IRQ status */
174 ata_sff_altstatus(ap
);
177 /* There are no DMA controllers without ctl. BUG here to ensure
178 we never violate the HDMA1:0 transition timing and risk
182 EXPORT_SYMBOL_GPL(ata_sff_dma_pause
);
185 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
186 * @ap: port containing status register to be polled
187 * @tmout_pat: impatience timeout in msecs
188 * @tmout: overall timeout in msecs
190 * Sleep until ATA Status register bit BSY clears,
191 * or a timeout occurs.
194 * Kernel thread context (may sleep).
197 * 0 on success, -errno otherwise.
199 int ata_sff_busy_sleep(struct ata_port
*ap
,
200 unsigned long tmout_pat
, unsigned long tmout
)
202 unsigned long timer_start
, timeout
;
205 status
= ata_sff_busy_wait(ap
, ATA_BUSY
, 300);
206 timer_start
= jiffies
;
207 timeout
= ata_deadline(timer_start
, tmout_pat
);
208 while (status
!= 0xff && (status
& ATA_BUSY
) &&
209 time_before(jiffies
, timeout
)) {
211 status
= ata_sff_busy_wait(ap
, ATA_BUSY
, 3);
214 if (status
!= 0xff && (status
& ATA_BUSY
))
216 "port is slow to respond, please be patient (Status 0x%x)\n",
219 timeout
= ata_deadline(timer_start
, tmout
);
220 while (status
!= 0xff && (status
& ATA_BUSY
) &&
221 time_before(jiffies
, timeout
)) {
223 status
= ap
->ops
->sff_check_status(ap
);
229 if (status
& ATA_BUSY
) {
231 "port failed to respond (%lu secs, Status 0x%x)\n",
232 DIV_ROUND_UP(tmout
, 1000), status
);
238 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep
);
240 static int ata_sff_check_ready(struct ata_link
*link
)
242 u8 status
= link
->ap
->ops
->sff_check_status(link
->ap
);
244 return ata_check_ready(status
);
248 * ata_sff_wait_ready - sleep until BSY clears, or timeout
249 * @link: SFF link to wait ready status for
250 * @deadline: deadline jiffies for the operation
252 * Sleep until ATA Status register bit BSY clears, or timeout
256 * Kernel thread context (may sleep).
259 * 0 on success, -errno otherwise.
261 int ata_sff_wait_ready(struct ata_link
*link
, unsigned long deadline
)
263 return ata_wait_ready(link
, deadline
, ata_sff_check_ready
);
265 EXPORT_SYMBOL_GPL(ata_sff_wait_ready
);
268 * ata_sff_set_devctl - Write device control reg
269 * @ap: port where the device is
270 * @ctl: value to write
272 * Writes ATA taskfile device control register.
274 * Note: may NOT be used as the sff_set_devctl() entry in
275 * ata_port_operations.
278 * Inherited from caller.
280 static void ata_sff_set_devctl(struct ata_port
*ap
, u8 ctl
)
282 if (ap
->ops
->sff_set_devctl
)
283 ap
->ops
->sff_set_devctl(ap
, ctl
);
285 iowrite8(ctl
, ap
->ioaddr
.ctl_addr
);
289 * ata_sff_dev_select - Select device 0/1 on ATA bus
290 * @ap: ATA channel to manipulate
291 * @device: ATA device (numbered from zero) to select
293 * Use the method defined in the ATA specification to
294 * make either device 0, or device 1, active on the
295 * ATA channel. Works with both PIO and MMIO.
297 * May be used as the dev_select() entry in ata_port_operations.
302 void ata_sff_dev_select(struct ata_port
*ap
, unsigned int device
)
307 tmp
= ATA_DEVICE_OBS
;
309 tmp
= ATA_DEVICE_OBS
| ATA_DEV1
;
311 iowrite8(tmp
, ap
->ioaddr
.device_addr
);
312 ata_sff_pause(ap
); /* needed; also flushes, for mmio */
314 EXPORT_SYMBOL_GPL(ata_sff_dev_select
);
317 * ata_dev_select - Select device 0/1 on ATA bus
318 * @ap: ATA channel to manipulate
319 * @device: ATA device (numbered from zero) to select
320 * @wait: non-zero to wait for Status register BSY bit to clear
321 * @can_sleep: non-zero if context allows sleeping
323 * Use the method defined in the ATA specification to
324 * make either device 0, or device 1, active on the
327 * This is a high-level version of ata_sff_dev_select(), which
328 * additionally provides the services of inserting the proper
329 * pauses and status polling, where needed.
334 static void ata_dev_select(struct ata_port
*ap
, unsigned int device
,
335 unsigned int wait
, unsigned int can_sleep
)
337 if (ata_msg_probe(ap
))
338 ata_port_info(ap
, "ata_dev_select: ENTER, device %u, wait %u\n",
344 ap
->ops
->sff_dev_select(ap
, device
);
347 if (can_sleep
&& ap
->link
.device
[device
].class == ATA_DEV_ATAPI
)
354 * ata_sff_irq_on - Enable interrupts on a port.
355 * @ap: Port on which interrupts are enabled.
357 * Enable interrupts on a legacy IDE device using MMIO or PIO,
358 * wait for idle, clear any pending interrupts.
360 * Note: may NOT be used as the sff_irq_on() entry in
361 * ata_port_operations.
364 * Inherited from caller.
366 void ata_sff_irq_on(struct ata_port
*ap
)
368 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
370 if (ap
->ops
->sff_irq_on
) {
371 ap
->ops
->sff_irq_on(ap
);
375 ap
->ctl
&= ~ATA_NIEN
;
376 ap
->last_ctl
= ap
->ctl
;
378 if (ap
->ops
->sff_set_devctl
|| ioaddr
->ctl_addr
)
379 ata_sff_set_devctl(ap
, ap
->ctl
);
382 if (ap
->ops
->sff_irq_clear
)
383 ap
->ops
->sff_irq_clear(ap
);
385 EXPORT_SYMBOL_GPL(ata_sff_irq_on
);
388 * ata_sff_tf_load - send taskfile registers to host controller
389 * @ap: Port to which output is sent
390 * @tf: ATA taskfile register set
392 * Outputs ATA taskfile to standard ATA host controller.
395 * Inherited from caller.
397 void ata_sff_tf_load(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
399 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
400 unsigned int is_addr
= tf
->flags
& ATA_TFLAG_ISADDR
;
402 if (tf
->ctl
!= ap
->last_ctl
) {
403 if (ioaddr
->ctl_addr
)
404 iowrite8(tf
->ctl
, ioaddr
->ctl_addr
);
405 ap
->last_ctl
= tf
->ctl
;
409 if (is_addr
&& (tf
->flags
& ATA_TFLAG_LBA48
)) {
410 WARN_ON_ONCE(!ioaddr
->ctl_addr
);
411 iowrite8(tf
->hob_feature
, ioaddr
->feature_addr
);
412 iowrite8(tf
->hob_nsect
, ioaddr
->nsect_addr
);
413 iowrite8(tf
->hob_lbal
, ioaddr
->lbal_addr
);
414 iowrite8(tf
->hob_lbam
, ioaddr
->lbam_addr
);
415 iowrite8(tf
->hob_lbah
, ioaddr
->lbah_addr
);
416 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
425 iowrite8(tf
->feature
, ioaddr
->feature_addr
);
426 iowrite8(tf
->nsect
, ioaddr
->nsect_addr
);
427 iowrite8(tf
->lbal
, ioaddr
->lbal_addr
);
428 iowrite8(tf
->lbam
, ioaddr
->lbam_addr
);
429 iowrite8(tf
->lbah
, ioaddr
->lbah_addr
);
430 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
438 if (tf
->flags
& ATA_TFLAG_DEVICE
) {
439 iowrite8(tf
->device
, ioaddr
->device_addr
);
440 VPRINTK("device 0x%X\n", tf
->device
);
445 EXPORT_SYMBOL_GPL(ata_sff_tf_load
);
448 * ata_sff_tf_read - input device's ATA taskfile shadow registers
449 * @ap: Port from which input is read
450 * @tf: ATA taskfile register set for storing input
452 * Reads ATA taskfile registers for currently-selected device
453 * into @tf. Assumes the device has a fully SFF compliant task file
454 * layout and behaviour. If you device does not (eg has a different
455 * status method) then you will need to provide a replacement tf_read
458 * Inherited from caller.
460 void ata_sff_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
462 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
464 tf
->command
= ata_sff_check_status(ap
);
465 tf
->feature
= ioread8(ioaddr
->error_addr
);
466 tf
->nsect
= ioread8(ioaddr
->nsect_addr
);
467 tf
->lbal
= ioread8(ioaddr
->lbal_addr
);
468 tf
->lbam
= ioread8(ioaddr
->lbam_addr
);
469 tf
->lbah
= ioread8(ioaddr
->lbah_addr
);
470 tf
->device
= ioread8(ioaddr
->device_addr
);
472 if (tf
->flags
& ATA_TFLAG_LBA48
) {
473 if (likely(ioaddr
->ctl_addr
)) {
474 iowrite8(tf
->ctl
| ATA_HOB
, ioaddr
->ctl_addr
);
475 tf
->hob_feature
= ioread8(ioaddr
->error_addr
);
476 tf
->hob_nsect
= ioread8(ioaddr
->nsect_addr
);
477 tf
->hob_lbal
= ioread8(ioaddr
->lbal_addr
);
478 tf
->hob_lbam
= ioread8(ioaddr
->lbam_addr
);
479 tf
->hob_lbah
= ioread8(ioaddr
->lbah_addr
);
480 iowrite8(tf
->ctl
, ioaddr
->ctl_addr
);
481 ap
->last_ctl
= tf
->ctl
;
486 EXPORT_SYMBOL_GPL(ata_sff_tf_read
);
489 * ata_sff_exec_command - issue ATA command to host controller
490 * @ap: port to which command is being issued
491 * @tf: ATA taskfile register set
493 * Issues ATA command, with proper synchronization with interrupt
494 * handler / other threads.
497 * spin_lock_irqsave(host lock)
499 void ata_sff_exec_command(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
501 DPRINTK("ata%u: cmd 0x%X\n", ap
->print_id
, tf
->command
);
503 iowrite8(tf
->command
, ap
->ioaddr
.command_addr
);
506 EXPORT_SYMBOL_GPL(ata_sff_exec_command
);
509 * ata_tf_to_host - issue ATA taskfile to host controller
510 * @ap: port to which command is being issued
511 * @tf: ATA taskfile register set
513 * Issues ATA taskfile register set to ATA host controller,
514 * with proper synchronization with interrupt handler and
518 * spin_lock_irqsave(host lock)
520 static inline void ata_tf_to_host(struct ata_port
*ap
,
521 const struct ata_taskfile
*tf
)
523 ap
->ops
->sff_tf_load(ap
, tf
);
524 ap
->ops
->sff_exec_command(ap
, tf
);
528 * ata_sff_data_xfer - Transfer data by PIO
529 * @qc: queued command
531 * @buflen: buffer length
534 * Transfer data from/to the device data register by PIO.
537 * Inherited from caller.
542 unsigned int ata_sff_data_xfer(struct ata_queued_cmd
*qc
, unsigned char *buf
,
543 unsigned int buflen
, int rw
)
545 struct ata_port
*ap
= qc
->dev
->link
->ap
;
546 void __iomem
*data_addr
= ap
->ioaddr
.data_addr
;
547 unsigned int words
= buflen
>> 1;
549 /* Transfer multiple of 2 bytes */
551 ioread16_rep(data_addr
, buf
, words
);
553 iowrite16_rep(data_addr
, buf
, words
);
555 /* Transfer trailing byte, if any. */
556 if (unlikely(buflen
& 0x01)) {
557 unsigned char pad
[2] = { };
559 /* Point buf to the tail of buffer */
563 * Use io*16_rep() accessors here as well to avoid pointlessly
564 * swapping bytes to and from on the big endian machines...
567 ioread16_rep(data_addr
, pad
, 1);
571 iowrite16_rep(data_addr
, pad
, 1);
578 EXPORT_SYMBOL_GPL(ata_sff_data_xfer
);
581 * ata_sff_data_xfer32 - Transfer data by PIO
582 * @qc: queued command
584 * @buflen: buffer length
587 * Transfer data from/to the device data register by PIO using 32bit
591 * Inherited from caller.
597 unsigned int ata_sff_data_xfer32(struct ata_queued_cmd
*qc
, unsigned char *buf
,
598 unsigned int buflen
, int rw
)
600 struct ata_device
*dev
= qc
->dev
;
601 struct ata_port
*ap
= dev
->link
->ap
;
602 void __iomem
*data_addr
= ap
->ioaddr
.data_addr
;
603 unsigned int words
= buflen
>> 2;
604 int slop
= buflen
& 3;
606 if (!(ap
->pflags
& ATA_PFLAG_PIO32
))
607 return ata_sff_data_xfer(qc
, buf
, buflen
, rw
);
609 /* Transfer multiple of 4 bytes */
611 ioread32_rep(data_addr
, buf
, words
);
613 iowrite32_rep(data_addr
, buf
, words
);
615 /* Transfer trailing bytes, if any */
616 if (unlikely(slop
)) {
617 unsigned char pad
[4] = { };
619 /* Point buf to the tail of buffer */
620 buf
+= buflen
- slop
;
623 * Use io*_rep() accessors here as well to avoid pointlessly
624 * swapping bytes to and from on the big endian machines...
628 ioread16_rep(data_addr
, pad
, 1);
630 ioread32_rep(data_addr
, pad
, 1);
631 memcpy(buf
, pad
, slop
);
633 memcpy(pad
, buf
, slop
);
635 iowrite16_rep(data_addr
, pad
, 1);
637 iowrite32_rep(data_addr
, pad
, 1);
640 return (buflen
+ 1) & ~1;
642 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32
);
645 * ata_pio_sector - Transfer a sector of data.
646 * @qc: Command on going
648 * Transfer qc->sect_size bytes of data from/to the ATA device.
651 * Inherited from caller.
653 static void ata_pio_sector(struct ata_queued_cmd
*qc
)
655 int do_write
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
656 struct ata_port
*ap
= qc
->ap
;
661 if (qc
->curbytes
== qc
->nbytes
- qc
->sect_size
)
662 ap
->hsm_task_state
= HSM_ST_LAST
;
664 page
= sg_page(qc
->cursg
);
665 offset
= qc
->cursg
->offset
+ qc
->cursg_ofs
;
667 /* get the current page and offset */
668 page
= nth_page(page
, (offset
>> PAGE_SHIFT
));
671 DPRINTK("data %s\n", qc
->tf
.flags
& ATA_TFLAG_WRITE
? "write" : "read");
673 /* do the actual data transfer */
674 buf
= kmap_atomic(page
);
675 ap
->ops
->sff_data_xfer(qc
, buf
+ offset
, qc
->sect_size
, do_write
);
678 if (!do_write
&& !PageSlab(page
))
679 flush_dcache_page(page
);
681 qc
->curbytes
+= qc
->sect_size
;
682 qc
->cursg_ofs
+= qc
->sect_size
;
684 if (qc
->cursg_ofs
== qc
->cursg
->length
) {
685 qc
->cursg
= sg_next(qc
->cursg
);
691 * ata_pio_sectors - Transfer one or many sectors.
692 * @qc: Command on going
694 * Transfer one or many sectors of data from/to the
695 * ATA device for the DRQ request.
698 * Inherited from caller.
700 static void ata_pio_sectors(struct ata_queued_cmd
*qc
)
702 if (is_multi_taskfile(&qc
->tf
)) {
703 /* READ/WRITE MULTIPLE */
706 WARN_ON_ONCE(qc
->dev
->multi_count
== 0);
708 nsect
= min((qc
->nbytes
- qc
->curbytes
) / qc
->sect_size
,
709 qc
->dev
->multi_count
);
715 ata_sff_sync(qc
->ap
); /* flush */
719 * atapi_send_cdb - Write CDB bytes to hardware
720 * @ap: Port to which ATAPI device is attached.
721 * @qc: Taskfile currently active
723 * When device has indicated its readiness to accept
724 * a CDB, this function is called. Send the CDB.
729 static void atapi_send_cdb(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
732 DPRINTK("send cdb\n");
733 WARN_ON_ONCE(qc
->dev
->cdb_len
< 12);
735 ap
->ops
->sff_data_xfer(qc
, qc
->cdb
, qc
->dev
->cdb_len
, 1);
737 /* FIXME: If the CDB is for DMA do we need to do the transition delay
738 or is bmdma_start guaranteed to do it ? */
739 switch (qc
->tf
.protocol
) {
741 ap
->hsm_task_state
= HSM_ST
;
743 case ATAPI_PROT_NODATA
:
744 ap
->hsm_task_state
= HSM_ST_LAST
;
746 #ifdef CONFIG_ATA_BMDMA
748 ap
->hsm_task_state
= HSM_ST_LAST
;
750 ap
->ops
->bmdma_start(qc
);
752 #endif /* CONFIG_ATA_BMDMA */
759 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
760 * @qc: Command on going
761 * @bytes: number of bytes
763 * Transfer Transfer data from/to the ATAPI device.
766 * Inherited from caller.
769 static int __atapi_pio_bytes(struct ata_queued_cmd
*qc
, unsigned int bytes
)
771 int rw
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
) ? WRITE
: READ
;
772 struct ata_port
*ap
= qc
->ap
;
773 struct ata_device
*dev
= qc
->dev
;
774 struct ata_eh_info
*ehi
= &dev
->link
->eh_info
;
775 struct scatterlist
*sg
;
778 unsigned int offset
, count
, consumed
;
783 ata_ehi_push_desc(ehi
, "unexpected or too much trailing data "
784 "buf=%u cur=%u bytes=%u",
785 qc
->nbytes
, qc
->curbytes
, bytes
);
790 offset
= sg
->offset
+ qc
->cursg_ofs
;
792 /* get the current page and offset */
793 page
= nth_page(page
, (offset
>> PAGE_SHIFT
));
796 /* don't overrun current sg */
797 count
= min(sg
->length
- qc
->cursg_ofs
, bytes
);
799 /* don't cross page boundaries */
800 count
= min(count
, (unsigned int)PAGE_SIZE
- offset
);
802 DPRINTK("data %s\n", qc
->tf
.flags
& ATA_TFLAG_WRITE
? "write" : "read");
804 /* do the actual data transfer */
805 buf
= kmap_atomic(page
);
806 consumed
= ap
->ops
->sff_data_xfer(qc
, buf
+ offset
, count
, rw
);
809 bytes
-= min(bytes
, consumed
);
810 qc
->curbytes
+= count
;
811 qc
->cursg_ofs
+= count
;
813 if (qc
->cursg_ofs
== sg
->length
) {
814 qc
->cursg
= sg_next(qc
->cursg
);
819 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
820 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
821 * check correctly as it doesn't know if it is the last request being
822 * made. Somebody should implement a proper sanity check.
830 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
831 * @qc: Command on going
833 * Transfer Transfer data from/to the ATAPI device.
836 * Inherited from caller.
838 static void atapi_pio_bytes(struct ata_queued_cmd
*qc
)
840 struct ata_port
*ap
= qc
->ap
;
841 struct ata_device
*dev
= qc
->dev
;
842 struct ata_eh_info
*ehi
= &dev
->link
->eh_info
;
843 unsigned int ireason
, bc_lo
, bc_hi
, bytes
;
844 int i_write
, do_write
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
) ? 1 : 0;
846 /* Abuse qc->result_tf for temp storage of intermediate TF
847 * here to save some kernel stack usage.
848 * For normal completion, qc->result_tf is not relevant. For
849 * error, qc->result_tf is later overwritten by ata_qc_complete().
850 * So, the correctness of qc->result_tf is not affected.
852 ap
->ops
->sff_tf_read(ap
, &qc
->result_tf
);
853 ireason
= qc
->result_tf
.nsect
;
854 bc_lo
= qc
->result_tf
.lbam
;
855 bc_hi
= qc
->result_tf
.lbah
;
856 bytes
= (bc_hi
<< 8) | bc_lo
;
858 /* shall be cleared to zero, indicating xfer of data */
859 if (unlikely(ireason
& ATAPI_COD
))
862 /* make sure transfer direction matches expected */
863 i_write
= ((ireason
& ATAPI_IO
) == 0) ? 1 : 0;
864 if (unlikely(do_write
!= i_write
))
867 if (unlikely(!bytes
))
870 VPRINTK("ata%u: xfering %d bytes\n", ap
->print_id
, bytes
);
872 if (unlikely(__atapi_pio_bytes(qc
, bytes
)))
874 ata_sff_sync(ap
); /* flush */
879 ata_ehi_push_desc(ehi
, "ATAPI check failed (ireason=0x%x bytes=%u)",
882 qc
->err_mask
|= AC_ERR_HSM
;
883 ap
->hsm_task_state
= HSM_ST_ERR
;
887 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
888 * @ap: the target ata_port
892 * 1 if ok in workqueue, 0 otherwise.
894 static inline int ata_hsm_ok_in_wq(struct ata_port
*ap
,
895 struct ata_queued_cmd
*qc
)
897 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
900 if (ap
->hsm_task_state
== HSM_ST_FIRST
) {
901 if (qc
->tf
.protocol
== ATA_PROT_PIO
&&
902 (qc
->tf
.flags
& ATA_TFLAG_WRITE
))
905 if (ata_is_atapi(qc
->tf
.protocol
) &&
906 !(qc
->dev
->flags
& ATA_DFLAG_CDB_INTR
))
914 * ata_hsm_qc_complete - finish a qc running on standard HSM
915 * @qc: Command to complete
916 * @in_wq: 1 if called from workqueue, 0 otherwise
918 * Finish @qc which is running on standard HSM.
921 * If @in_wq is zero, spin_lock_irqsave(host lock).
922 * Otherwise, none on entry and grabs host lock.
924 static void ata_hsm_qc_complete(struct ata_queued_cmd
*qc
, int in_wq
)
926 struct ata_port
*ap
= qc
->ap
;
928 if (ap
->ops
->error_handler
) {
930 /* EH might have kicked in while host lock is
933 qc
= ata_qc_from_tag(ap
, qc
->tag
);
935 if (likely(!(qc
->err_mask
& AC_ERR_HSM
))) {
942 if (likely(!(qc
->err_mask
& AC_ERR_HSM
)))
957 * ata_sff_hsm_move - move the HSM to the next state.
958 * @ap: the target ata_port
960 * @status: current device status
961 * @in_wq: 1 if called from workqueue, 0 otherwise
964 * 1 when poll next status needed, 0 otherwise.
966 int ata_sff_hsm_move(struct ata_port
*ap
, struct ata_queued_cmd
*qc
,
967 u8 status
, int in_wq
)
969 struct ata_link
*link
= qc
->dev
->link
;
970 struct ata_eh_info
*ehi
= &link
->eh_info
;
973 lockdep_assert_held(ap
->lock
);
975 WARN_ON_ONCE((qc
->flags
& ATA_QCFLAG_ACTIVE
) == 0);
977 /* Make sure ata_sff_qc_issue() does not throw things
978 * like DMA polling into the workqueue. Notice that
979 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
981 WARN_ON_ONCE(in_wq
!= ata_hsm_ok_in_wq(ap
, qc
));
984 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
985 ap
->print_id
, qc
->tf
.protocol
, ap
->hsm_task_state
, status
);
987 switch (ap
->hsm_task_state
) {
989 /* Send first data block or PACKET CDB */
991 /* If polling, we will stay in the work queue after
992 * sending the data. Otherwise, interrupt handler
993 * takes over after sending the data.
995 poll_next
= (qc
->tf
.flags
& ATA_TFLAG_POLLING
);
997 /* check device status */
998 if (unlikely((status
& ATA_DRQ
) == 0)) {
999 /* handle BSY=0, DRQ=0 as error */
1000 if (likely(status
& (ATA_ERR
| ATA_DF
)))
1001 /* device stops HSM for abort/error */
1002 qc
->err_mask
|= AC_ERR_DEV
;
1004 /* HSM violation. Let EH handle this */
1005 ata_ehi_push_desc(ehi
,
1006 "ST_FIRST: !(DRQ|ERR|DF)");
1007 qc
->err_mask
|= AC_ERR_HSM
;
1010 ap
->hsm_task_state
= HSM_ST_ERR
;
1014 /* Device should not ask for data transfer (DRQ=1)
1015 * when it finds something wrong.
1016 * We ignore DRQ here and stop the HSM by
1017 * changing hsm_task_state to HSM_ST_ERR and
1018 * let the EH abort the command or reset the device.
1020 if (unlikely(status
& (ATA_ERR
| ATA_DF
))) {
1021 /* Some ATAPI tape drives forget to clear the ERR bit
1022 * when doing the next command (mostly request sense).
1023 * We ignore ERR here to workaround and proceed sending
1026 if (!(qc
->dev
->horkage
& ATA_HORKAGE_STUCK_ERR
)) {
1027 ata_ehi_push_desc(ehi
, "ST_FIRST: "
1028 "DRQ=1 with device error, "
1029 "dev_stat 0x%X", status
);
1030 qc
->err_mask
|= AC_ERR_HSM
;
1031 ap
->hsm_task_state
= HSM_ST_ERR
;
1036 if (qc
->tf
.protocol
== ATA_PROT_PIO
) {
1037 /* PIO data out protocol.
1038 * send first data block.
1041 /* ata_pio_sectors() might change the state
1042 * to HSM_ST_LAST. so, the state is changed here
1043 * before ata_pio_sectors().
1045 ap
->hsm_task_state
= HSM_ST
;
1046 ata_pio_sectors(qc
);
1049 atapi_send_cdb(ap
, qc
);
1051 /* if polling, ata_sff_pio_task() handles the rest.
1052 * otherwise, interrupt handler takes over from here.
1057 /* complete command or read/write the data register */
1058 if (qc
->tf
.protocol
== ATAPI_PROT_PIO
) {
1059 /* ATAPI PIO protocol */
1060 if ((status
& ATA_DRQ
) == 0) {
1061 /* No more data to transfer or device error.
1062 * Device error will be tagged in HSM_ST_LAST.
1064 ap
->hsm_task_state
= HSM_ST_LAST
;
1068 /* Device should not ask for data transfer (DRQ=1)
1069 * when it finds something wrong.
1070 * We ignore DRQ here and stop the HSM by
1071 * changing hsm_task_state to HSM_ST_ERR and
1072 * let the EH abort the command or reset the device.
1074 if (unlikely(status
& (ATA_ERR
| ATA_DF
))) {
1075 ata_ehi_push_desc(ehi
, "ST-ATAPI: "
1076 "DRQ=1 with device error, "
1077 "dev_stat 0x%X", status
);
1078 qc
->err_mask
|= AC_ERR_HSM
;
1079 ap
->hsm_task_state
= HSM_ST_ERR
;
1083 atapi_pio_bytes(qc
);
1085 if (unlikely(ap
->hsm_task_state
== HSM_ST_ERR
))
1086 /* bad ireason reported by device */
1090 /* ATA PIO protocol */
1091 if (unlikely((status
& ATA_DRQ
) == 0)) {
1092 /* handle BSY=0, DRQ=0 as error */
1093 if (likely(status
& (ATA_ERR
| ATA_DF
))) {
1094 /* device stops HSM for abort/error */
1095 qc
->err_mask
|= AC_ERR_DEV
;
1097 /* If diagnostic failed and this is
1098 * IDENTIFY, it's likely a phantom
1099 * device. Mark hint.
1101 if (qc
->dev
->horkage
&
1102 ATA_HORKAGE_DIAGNOSTIC
)
1106 /* HSM violation. Let EH handle this.
1107 * Phantom devices also trigger this
1108 * condition. Mark hint.
1110 ata_ehi_push_desc(ehi
, "ST-ATA: "
1111 "DRQ=0 without device error, "
1112 "dev_stat 0x%X", status
);
1113 qc
->err_mask
|= AC_ERR_HSM
|
1117 ap
->hsm_task_state
= HSM_ST_ERR
;
1121 /* For PIO reads, some devices may ask for
1122 * data transfer (DRQ=1) alone with ERR=1.
1123 * We respect DRQ here and transfer one
1124 * block of junk data before changing the
1125 * hsm_task_state to HSM_ST_ERR.
1127 * For PIO writes, ERR=1 DRQ=1 doesn't make
1128 * sense since the data block has been
1129 * transferred to the device.
1131 if (unlikely(status
& (ATA_ERR
| ATA_DF
))) {
1132 /* data might be corrputed */
1133 qc
->err_mask
|= AC_ERR_DEV
;
1135 if (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
)) {
1136 ata_pio_sectors(qc
);
1137 status
= ata_wait_idle(ap
);
1140 if (status
& (ATA_BUSY
| ATA_DRQ
)) {
1141 ata_ehi_push_desc(ehi
, "ST-ATA: "
1142 "BUSY|DRQ persists on ERR|DF, "
1143 "dev_stat 0x%X", status
);
1144 qc
->err_mask
|= AC_ERR_HSM
;
1147 /* There are oddball controllers with
1148 * status register stuck at 0x7f and
1149 * lbal/m/h at zero which makes it
1150 * pass all other presence detection
1151 * mechanisms we have. Set NODEV_HINT
1152 * for it. Kernel bz#7241.
1155 qc
->err_mask
|= AC_ERR_NODEV_HINT
;
1157 /* ata_pio_sectors() might change the
1158 * state to HSM_ST_LAST. so, the state
1159 * is changed after ata_pio_sectors().
1161 ap
->hsm_task_state
= HSM_ST_ERR
;
1165 ata_pio_sectors(qc
);
1167 if (ap
->hsm_task_state
== HSM_ST_LAST
&&
1168 (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))) {
1170 status
= ata_wait_idle(ap
);
1179 if (unlikely(!ata_ok(status
))) {
1180 qc
->err_mask
|= __ac_err_mask(status
);
1181 ap
->hsm_task_state
= HSM_ST_ERR
;
1185 /* no more data to transfer */
1186 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1187 ap
->print_id
, qc
->dev
->devno
, status
);
1189 WARN_ON_ONCE(qc
->err_mask
& (AC_ERR_DEV
| AC_ERR_HSM
));
1191 ap
->hsm_task_state
= HSM_ST_IDLE
;
1193 /* complete taskfile transaction */
1194 ata_hsm_qc_complete(qc
, in_wq
);
1200 ap
->hsm_task_state
= HSM_ST_IDLE
;
1202 /* complete taskfile transaction */
1203 ata_hsm_qc_complete(qc
, in_wq
);
1209 WARN(true, "ata%d: SFF host state machine in invalid state %d",
1210 ap
->print_id
, ap
->hsm_task_state
);
1215 EXPORT_SYMBOL_GPL(ata_sff_hsm_move
);
1217 void ata_sff_queue_work(struct work_struct
*work
)
1219 queue_work(ata_sff_wq
, work
);
1221 EXPORT_SYMBOL_GPL(ata_sff_queue_work
);
1223 void ata_sff_queue_delayed_work(struct delayed_work
*dwork
, unsigned long delay
)
1225 queue_delayed_work(ata_sff_wq
, dwork
, delay
);
1227 EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work
);
1229 void ata_sff_queue_pio_task(struct ata_link
*link
, unsigned long delay
)
1231 struct ata_port
*ap
= link
->ap
;
1233 WARN_ON((ap
->sff_pio_task_link
!= NULL
) &&
1234 (ap
->sff_pio_task_link
!= link
));
1235 ap
->sff_pio_task_link
= link
;
1237 /* may fail if ata_sff_flush_pio_task() in progress */
1238 ata_sff_queue_delayed_work(&ap
->sff_pio_task
, msecs_to_jiffies(delay
));
1240 EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task
);
1242 void ata_sff_flush_pio_task(struct ata_port
*ap
)
1246 cancel_delayed_work_sync(&ap
->sff_pio_task
);
1249 * We wanna reset the HSM state to IDLE. If we do so without
1250 * grabbing the port lock, critical sections protected by it which
1251 * expect the HSM state to stay stable may get surprised. For
1252 * example, we may set IDLE in between the time
1253 * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
1254 * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
1256 spin_lock_irq(ap
->lock
);
1257 ap
->hsm_task_state
= HSM_ST_IDLE
;
1258 spin_unlock_irq(ap
->lock
);
1260 ap
->sff_pio_task_link
= NULL
;
1262 if (ata_msg_ctl(ap
))
1263 ata_port_dbg(ap
, "%s: EXIT\n", __func__
);
1266 static void ata_sff_pio_task(struct work_struct
*work
)
1268 struct ata_port
*ap
=
1269 container_of(work
, struct ata_port
, sff_pio_task
.work
);
1270 struct ata_link
*link
= ap
->sff_pio_task_link
;
1271 struct ata_queued_cmd
*qc
;
1275 spin_lock_irq(ap
->lock
);
1277 BUG_ON(ap
->sff_pio_task_link
== NULL
);
1278 /* qc can be NULL if timeout occurred */
1279 qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1281 ap
->sff_pio_task_link
= NULL
;
1286 WARN_ON_ONCE(ap
->hsm_task_state
== HSM_ST_IDLE
);
1289 * This is purely heuristic. This is a fast path.
1290 * Sometimes when we enter, BSY will be cleared in
1291 * a chk-status or two. If not, the drive is probably seeking
1292 * or something. Snooze for a couple msecs, then
1293 * chk-status again. If still busy, queue delayed work.
1295 status
= ata_sff_busy_wait(ap
, ATA_BUSY
, 5);
1296 if (status
& ATA_BUSY
) {
1297 spin_unlock_irq(ap
->lock
);
1299 spin_lock_irq(ap
->lock
);
1301 status
= ata_sff_busy_wait(ap
, ATA_BUSY
, 10);
1302 if (status
& ATA_BUSY
) {
1303 ata_sff_queue_pio_task(link
, ATA_SHORT_PAUSE
);
1309 * hsm_move() may trigger another command to be processed.
1310 * clean the link beforehand.
1312 ap
->sff_pio_task_link
= NULL
;
1314 poll_next
= ata_sff_hsm_move(ap
, qc
, status
, 1);
1316 /* another command or interrupt handler
1317 * may be running at this point.
1322 spin_unlock_irq(ap
->lock
);
1326 * ata_sff_qc_issue - issue taskfile to a SFF controller
1327 * @qc: command to issue to device
1329 * This function issues a PIO or NODATA command to a SFF
1333 * spin_lock_irqsave(host lock)
1336 * Zero on success, AC_ERR_* mask on failure
1338 unsigned int ata_sff_qc_issue(struct ata_queued_cmd
*qc
)
1340 struct ata_port
*ap
= qc
->ap
;
1341 struct ata_link
*link
= qc
->dev
->link
;
1343 /* Use polling pio if the LLD doesn't handle
1344 * interrupt driven pio and atapi CDB interrupt.
1346 if (ap
->flags
& ATA_FLAG_PIO_POLLING
)
1347 qc
->tf
.flags
|= ATA_TFLAG_POLLING
;
1349 /* select the device */
1350 ata_dev_select(ap
, qc
->dev
->devno
, 1, 0);
1352 /* start the command */
1353 switch (qc
->tf
.protocol
) {
1354 case ATA_PROT_NODATA
:
1355 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
1356 ata_qc_set_polling(qc
);
1358 ata_tf_to_host(ap
, &qc
->tf
);
1359 ap
->hsm_task_state
= HSM_ST_LAST
;
1361 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
1362 ata_sff_queue_pio_task(link
, 0);
1367 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
1368 ata_qc_set_polling(qc
);
1370 ata_tf_to_host(ap
, &qc
->tf
);
1372 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
) {
1373 /* PIO data out protocol */
1374 ap
->hsm_task_state
= HSM_ST_FIRST
;
1375 ata_sff_queue_pio_task(link
, 0);
1377 /* always send first data block using the
1378 * ata_sff_pio_task() codepath.
1381 /* PIO data in protocol */
1382 ap
->hsm_task_state
= HSM_ST
;
1384 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
1385 ata_sff_queue_pio_task(link
, 0);
1387 /* if polling, ata_sff_pio_task() handles the
1388 * rest. otherwise, interrupt handler takes
1395 case ATAPI_PROT_PIO
:
1396 case ATAPI_PROT_NODATA
:
1397 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
1398 ata_qc_set_polling(qc
);
1400 ata_tf_to_host(ap
, &qc
->tf
);
1402 ap
->hsm_task_state
= HSM_ST_FIRST
;
1404 /* send cdb by polling if no cdb interrupt */
1405 if ((!(qc
->dev
->flags
& ATA_DFLAG_CDB_INTR
)) ||
1406 (qc
->tf
.flags
& ATA_TFLAG_POLLING
))
1407 ata_sff_queue_pio_task(link
, 0);
1411 return AC_ERR_SYSTEM
;
1416 EXPORT_SYMBOL_GPL(ata_sff_qc_issue
);
1419 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1420 * @qc: qc to fill result TF for
1422 * @qc is finished and result TF needs to be filled. Fill it
1423 * using ->sff_tf_read.
1426 * spin_lock_irqsave(host lock)
1429 * true indicating that result TF is successfully filled.
1431 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd
*qc
)
1433 qc
->ap
->ops
->sff_tf_read(qc
->ap
, &qc
->result_tf
);
1436 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf
);
1438 static unsigned int ata_sff_idle_irq(struct ata_port
*ap
)
1440 ap
->stats
.idle_irq
++;
1443 if ((ap
->stats
.idle_irq
% 1000) == 0) {
1444 ap
->ops
->sff_check_status(ap
);
1445 if (ap
->ops
->sff_irq_clear
)
1446 ap
->ops
->sff_irq_clear(ap
);
1447 ata_port_warn(ap
, "irq trap\n");
1451 return 0; /* irq not handled */
1454 static unsigned int __ata_sff_port_intr(struct ata_port
*ap
,
1455 struct ata_queued_cmd
*qc
,
1460 VPRINTK("ata%u: protocol %d task_state %d\n",
1461 ap
->print_id
, qc
->tf
.protocol
, ap
->hsm_task_state
);
1463 /* Check whether we are expecting interrupt in this state */
1464 switch (ap
->hsm_task_state
) {
1466 /* Some pre-ATAPI-4 devices assert INTRQ
1467 * at this state when ready to receive CDB.
1470 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1471 * The flag was turned on only for atapi devices. No
1472 * need to check ata_is_atapi(qc->tf.protocol) again.
1474 if (!(qc
->dev
->flags
& ATA_DFLAG_CDB_INTR
))
1475 return ata_sff_idle_irq(ap
);
1478 return ata_sff_idle_irq(ap
);
1483 /* check main status, clearing INTRQ if needed */
1484 status
= ata_sff_irq_status(ap
);
1485 if (status
& ATA_BUSY
) {
1487 /* BMDMA engine is already stopped, we're screwed */
1488 qc
->err_mask
|= AC_ERR_HSM
;
1489 ap
->hsm_task_state
= HSM_ST_ERR
;
1491 return ata_sff_idle_irq(ap
);
1494 /* clear irq events */
1495 if (ap
->ops
->sff_irq_clear
)
1496 ap
->ops
->sff_irq_clear(ap
);
1498 ata_sff_hsm_move(ap
, qc
, status
, 0);
1500 return 1; /* irq handled */
1504 * ata_sff_port_intr - Handle SFF port interrupt
1505 * @ap: Port on which interrupt arrived (possibly...)
1506 * @qc: Taskfile currently active in engine
1508 * Handle port interrupt for given queued command.
1511 * spin_lock_irqsave(host lock)
1514 * One if interrupt was handled, zero if not (shared irq).
1516 unsigned int ata_sff_port_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
1518 return __ata_sff_port_intr(ap
, qc
, false);
1520 EXPORT_SYMBOL_GPL(ata_sff_port_intr
);
1522 static inline irqreturn_t
__ata_sff_interrupt(int irq
, void *dev_instance
,
1523 unsigned int (*port_intr
)(struct ata_port
*, struct ata_queued_cmd
*))
1525 struct ata_host
*host
= dev_instance
;
1526 bool retried
= false;
1528 unsigned int handled
, idle
, polling
;
1529 unsigned long flags
;
1531 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1532 spin_lock_irqsave(&host
->lock
, flags
);
1535 handled
= idle
= polling
= 0;
1536 for (i
= 0; i
< host
->n_ports
; i
++) {
1537 struct ata_port
*ap
= host
->ports
[i
];
1538 struct ata_queued_cmd
*qc
;
1540 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
1542 if (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
))
1543 handled
|= port_intr(ap
, qc
);
1551 * If no port was expecting IRQ but the controller is actually
1552 * asserting IRQ line, nobody cared will ensue. Check IRQ
1553 * pending status if available and clear spurious IRQ.
1555 if (!handled
&& !retried
) {
1558 for (i
= 0; i
< host
->n_ports
; i
++) {
1559 struct ata_port
*ap
= host
->ports
[i
];
1561 if (polling
& (1 << i
))
1564 if (!ap
->ops
->sff_irq_check
||
1565 !ap
->ops
->sff_irq_check(ap
))
1568 if (idle
& (1 << i
)) {
1569 ap
->ops
->sff_check_status(ap
);
1570 if (ap
->ops
->sff_irq_clear
)
1571 ap
->ops
->sff_irq_clear(ap
);
1573 /* clear INTRQ and check if BUSY cleared */
1574 if (!(ap
->ops
->sff_check_status(ap
) & ATA_BUSY
))
1577 * With command in flight, we can't do
1578 * sff_irq_clear() w/o racing with completion.
1589 spin_unlock_irqrestore(&host
->lock
, flags
);
1591 return IRQ_RETVAL(handled
);
1595 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1596 * @irq: irq line (unused)
1597 * @dev_instance: pointer to our ata_host information structure
1599 * Default interrupt handler for PCI IDE devices. Calls
1600 * ata_sff_port_intr() for each port that is not disabled.
1603 * Obtains host lock during operation.
1606 * IRQ_NONE or IRQ_HANDLED.
1608 irqreturn_t
ata_sff_interrupt(int irq
, void *dev_instance
)
1610 return __ata_sff_interrupt(irq
, dev_instance
, ata_sff_port_intr
);
1612 EXPORT_SYMBOL_GPL(ata_sff_interrupt
);
1615 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1616 * @ap: port that appears to have timed out
1618 * Called from the libata error handlers when the core code suspects
1619 * an interrupt has been lost. If it has complete anything we can and
1620 * then return. Interface must support altstatus for this faster
1621 * recovery to occur.
1624 * Caller holds host lock
1627 void ata_sff_lost_interrupt(struct ata_port
*ap
)
1630 struct ata_queued_cmd
*qc
;
1632 /* Only one outstanding command per SFF channel */
1633 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
1634 /* We cannot lose an interrupt on a non-existent or polled command */
1635 if (!qc
|| qc
->tf
.flags
& ATA_TFLAG_POLLING
)
1637 /* See if the controller thinks it is still busy - if so the command
1638 isn't a lost IRQ but is still in progress */
1639 status
= ata_sff_altstatus(ap
);
1640 if (status
& ATA_BUSY
)
1643 /* There was a command running, we are no longer busy and we have
1645 ata_port_warn(ap
, "lost interrupt (Status 0x%x)\n",
1647 /* Run the host interrupt logic as if the interrupt had not been
1649 ata_sff_port_intr(ap
, qc
);
1651 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt
);
1654 * ata_sff_freeze - Freeze SFF controller port
1655 * @ap: port to freeze
1657 * Freeze SFF controller port.
1660 * Inherited from caller.
1662 void ata_sff_freeze(struct ata_port
*ap
)
1664 ap
->ctl
|= ATA_NIEN
;
1665 ap
->last_ctl
= ap
->ctl
;
1667 if (ap
->ops
->sff_set_devctl
|| ap
->ioaddr
.ctl_addr
)
1668 ata_sff_set_devctl(ap
, ap
->ctl
);
1670 /* Under certain circumstances, some controllers raise IRQ on
1671 * ATA_NIEN manipulation. Also, many controllers fail to mask
1672 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1674 ap
->ops
->sff_check_status(ap
);
1676 if (ap
->ops
->sff_irq_clear
)
1677 ap
->ops
->sff_irq_clear(ap
);
1679 EXPORT_SYMBOL_GPL(ata_sff_freeze
);
1682 * ata_sff_thaw - Thaw SFF controller port
1685 * Thaw SFF controller port.
1688 * Inherited from caller.
1690 void ata_sff_thaw(struct ata_port
*ap
)
1692 /* clear & re-enable interrupts */
1693 ap
->ops
->sff_check_status(ap
);
1694 if (ap
->ops
->sff_irq_clear
)
1695 ap
->ops
->sff_irq_clear(ap
);
1698 EXPORT_SYMBOL_GPL(ata_sff_thaw
);
1701 * ata_sff_prereset - prepare SFF link for reset
1702 * @link: SFF link to be reset
1703 * @deadline: deadline jiffies for the operation
1705 * SFF link @link is about to be reset. Initialize it. It first
1706 * calls ata_std_prereset() and wait for !BSY if the port is
1710 * Kernel thread context (may sleep)
1713 * 0 on success, -errno otherwise.
1715 int ata_sff_prereset(struct ata_link
*link
, unsigned long deadline
)
1717 struct ata_eh_context
*ehc
= &link
->eh_context
;
1720 rc
= ata_std_prereset(link
, deadline
);
1724 /* if we're about to do hardreset, nothing more to do */
1725 if (ehc
->i
.action
& ATA_EH_HARDRESET
)
1728 /* wait for !BSY if we don't know that no device is attached */
1729 if (!ata_link_offline(link
)) {
1730 rc
= ata_sff_wait_ready(link
, deadline
);
1731 if (rc
&& rc
!= -ENODEV
) {
1733 "device not ready (errno=%d), forcing hardreset\n",
1735 ehc
->i
.action
|= ATA_EH_HARDRESET
;
1741 EXPORT_SYMBOL_GPL(ata_sff_prereset
);
1744 * ata_devchk - PATA device presence detection
1745 * @ap: ATA channel to examine
1746 * @device: Device to examine (starting at zero)
1748 * This technique was originally described in
1749 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1750 * later found its way into the ATA/ATAPI spec.
1752 * Write a pattern to the ATA shadow registers,
1753 * and if a device is present, it will respond by
1754 * correctly storing and echoing back the
1755 * ATA shadow register contents.
1760 static unsigned int ata_devchk(struct ata_port
*ap
, unsigned int device
)
1762 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
1765 ap
->ops
->sff_dev_select(ap
, device
);
1767 iowrite8(0x55, ioaddr
->nsect_addr
);
1768 iowrite8(0xaa, ioaddr
->lbal_addr
);
1770 iowrite8(0xaa, ioaddr
->nsect_addr
);
1771 iowrite8(0x55, ioaddr
->lbal_addr
);
1773 iowrite8(0x55, ioaddr
->nsect_addr
);
1774 iowrite8(0xaa, ioaddr
->lbal_addr
);
1776 nsect
= ioread8(ioaddr
->nsect_addr
);
1777 lbal
= ioread8(ioaddr
->lbal_addr
);
1779 if ((nsect
== 0x55) && (lbal
== 0xaa))
1780 return 1; /* we found a device */
1782 return 0; /* nothing found */
1786 * ata_sff_dev_classify - Parse returned ATA device signature
1787 * @dev: ATA device to classify (starting at zero)
1788 * @present: device seems present
1789 * @r_err: Value of error register on completion
1791 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1792 * an ATA/ATAPI-defined set of values is placed in the ATA
1793 * shadow registers, indicating the results of device detection
1796 * Select the ATA device, and read the values from the ATA shadow
1797 * registers. Then parse according to the Error register value,
1798 * and the spec-defined values examined by ata_dev_classify().
1804 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1806 unsigned int ata_sff_dev_classify(struct ata_device
*dev
, int present
,
1809 struct ata_port
*ap
= dev
->link
->ap
;
1810 struct ata_taskfile tf
;
1814 ap
->ops
->sff_dev_select(ap
, dev
->devno
);
1816 memset(&tf
, 0, sizeof(tf
));
1818 ap
->ops
->sff_tf_read(ap
, &tf
);
1823 /* see if device passed diags: continue and warn later */
1825 /* diagnostic fail : do nothing _YET_ */
1826 dev
->horkage
|= ATA_HORKAGE_DIAGNOSTIC
;
1829 else if ((dev
->devno
== 0) && (err
== 0x81))
1832 return ATA_DEV_NONE
;
1834 /* determine if device is ATA or ATAPI */
1835 class = ata_dev_classify(&tf
);
1837 if (class == ATA_DEV_UNKNOWN
) {
1838 /* If the device failed diagnostic, it's likely to
1839 * have reported incorrect device signature too.
1840 * Assume ATA device if the device seems present but
1841 * device signature is invalid with diagnostic
1844 if (present
&& (dev
->horkage
& ATA_HORKAGE_DIAGNOSTIC
))
1845 class = ATA_DEV_ATA
;
1847 class = ATA_DEV_NONE
;
1848 } else if ((class == ATA_DEV_ATA
) &&
1849 (ap
->ops
->sff_check_status(ap
) == 0))
1850 class = ATA_DEV_NONE
;
1854 EXPORT_SYMBOL_GPL(ata_sff_dev_classify
);
1857 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1858 * @link: SFF link which is just reset
1859 * @devmask: mask of present devices
1860 * @deadline: deadline jiffies for the operation
1862 * Wait devices attached to SFF @link to become ready after
1863 * reset. It contains preceding 150ms wait to avoid accessing TF
1864 * status register too early.
1867 * Kernel thread context (may sleep).
1870 * 0 on success, -ENODEV if some or all of devices in @devmask
1871 * don't seem to exist. -errno on other errors.
1873 int ata_sff_wait_after_reset(struct ata_link
*link
, unsigned int devmask
,
1874 unsigned long deadline
)
1876 struct ata_port
*ap
= link
->ap
;
1877 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
1878 unsigned int dev0
= devmask
& (1 << 0);
1879 unsigned int dev1
= devmask
& (1 << 1);
1882 ata_msleep(ap
, ATA_WAIT_AFTER_RESET
);
1884 /* always check readiness of the master device */
1885 rc
= ata_sff_wait_ready(link
, deadline
);
1886 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1887 * and TF status is 0xff, bail out on it too.
1892 /* if device 1 was found in ata_devchk, wait for register
1893 * access briefly, then wait for BSY to clear.
1898 ap
->ops
->sff_dev_select(ap
, 1);
1900 /* Wait for register access. Some ATAPI devices fail
1901 * to set nsect/lbal after reset, so don't waste too
1902 * much time on it. We're gonna wait for !BSY anyway.
1904 for (i
= 0; i
< 2; i
++) {
1907 nsect
= ioread8(ioaddr
->nsect_addr
);
1908 lbal
= ioread8(ioaddr
->lbal_addr
);
1909 if ((nsect
== 1) && (lbal
== 1))
1911 ata_msleep(ap
, 50); /* give drive a breather */
1914 rc
= ata_sff_wait_ready(link
, deadline
);
1922 /* is all this really necessary? */
1923 ap
->ops
->sff_dev_select(ap
, 0);
1925 ap
->ops
->sff_dev_select(ap
, 1);
1927 ap
->ops
->sff_dev_select(ap
, 0);
1931 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset
);
1933 static int ata_bus_softreset(struct ata_port
*ap
, unsigned int devmask
,
1934 unsigned long deadline
)
1936 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
1938 DPRINTK("ata%u: bus reset via SRST\n", ap
->print_id
);
1940 if (ap
->ioaddr
.ctl_addr
) {
1941 /* software reset. causes dev0 to be selected */
1942 iowrite8(ap
->ctl
, ioaddr
->ctl_addr
);
1943 udelay(20); /* FIXME: flush */
1944 iowrite8(ap
->ctl
| ATA_SRST
, ioaddr
->ctl_addr
);
1945 udelay(20); /* FIXME: flush */
1946 iowrite8(ap
->ctl
, ioaddr
->ctl_addr
);
1947 ap
->last_ctl
= ap
->ctl
;
1950 /* wait the port to become ready */
1951 return ata_sff_wait_after_reset(&ap
->link
, devmask
, deadline
);
1955 * ata_sff_softreset - reset host port via ATA SRST
1956 * @link: ATA link to reset
1957 * @classes: resulting classes of attached devices
1958 * @deadline: deadline jiffies for the operation
1960 * Reset host port using ATA SRST.
1963 * Kernel thread context (may sleep)
1966 * 0 on success, -errno otherwise.
1968 int ata_sff_softreset(struct ata_link
*link
, unsigned int *classes
,
1969 unsigned long deadline
)
1971 struct ata_port
*ap
= link
->ap
;
1972 unsigned int slave_possible
= ap
->flags
& ATA_FLAG_SLAVE_POSS
;
1973 unsigned int devmask
= 0;
1979 /* determine if device 0/1 are present */
1980 if (ata_devchk(ap
, 0))
1981 devmask
|= (1 << 0);
1982 if (slave_possible
&& ata_devchk(ap
, 1))
1983 devmask
|= (1 << 1);
1985 /* select device 0 again */
1986 ap
->ops
->sff_dev_select(ap
, 0);
1988 /* issue bus reset */
1989 DPRINTK("about to softreset, devmask=%x\n", devmask
);
1990 rc
= ata_bus_softreset(ap
, devmask
, deadline
);
1991 /* if link is occupied, -ENODEV too is an error */
1992 if (rc
&& (rc
!= -ENODEV
|| sata_scr_valid(link
))) {
1993 ata_link_err(link
, "SRST failed (errno=%d)\n", rc
);
1997 /* determine by signature whether we have ATA or ATAPI devices */
1998 classes
[0] = ata_sff_dev_classify(&link
->device
[0],
1999 devmask
& (1 << 0), &err
);
2000 if (slave_possible
&& err
!= 0x81)
2001 classes
[1] = ata_sff_dev_classify(&link
->device
[1],
2002 devmask
& (1 << 1), &err
);
2004 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes
[0], classes
[1]);
2007 EXPORT_SYMBOL_GPL(ata_sff_softreset
);
2010 * sata_sff_hardreset - reset host port via SATA phy reset
2011 * @link: link to reset
2012 * @class: resulting class of attached device
2013 * @deadline: deadline jiffies for the operation
2015 * SATA phy-reset host port using DET bits of SControl register,
2016 * wait for !BSY and classify the attached device.
2019 * Kernel thread context (may sleep)
2022 * 0 on success, -errno otherwise.
2024 int sata_sff_hardreset(struct ata_link
*link
, unsigned int *class,
2025 unsigned long deadline
)
2027 struct ata_eh_context
*ehc
= &link
->eh_context
;
2028 const unsigned long *timing
= sata_ehc_deb_timing(ehc
);
2032 rc
= sata_link_hardreset(link
, timing
, deadline
, &online
,
2033 ata_sff_check_ready
);
2035 *class = ata_sff_dev_classify(link
->device
, 1, NULL
);
2037 DPRINTK("EXIT, class=%u\n", *class);
2040 EXPORT_SYMBOL_GPL(sata_sff_hardreset
);
2043 * ata_sff_postreset - SFF postreset callback
2044 * @link: the target SFF ata_link
2045 * @classes: classes of attached devices
2047 * This function is invoked after a successful reset. It first
2048 * calls ata_std_postreset() and performs SFF specific postreset
2052 * Kernel thread context (may sleep)
2054 void ata_sff_postreset(struct ata_link
*link
, unsigned int *classes
)
2056 struct ata_port
*ap
= link
->ap
;
2058 ata_std_postreset(link
, classes
);
2060 /* is double-select really necessary? */
2061 if (classes
[0] != ATA_DEV_NONE
)
2062 ap
->ops
->sff_dev_select(ap
, 1);
2063 if (classes
[1] != ATA_DEV_NONE
)
2064 ap
->ops
->sff_dev_select(ap
, 0);
2066 /* bail out if no device is present */
2067 if (classes
[0] == ATA_DEV_NONE
&& classes
[1] == ATA_DEV_NONE
) {
2068 DPRINTK("EXIT, no device\n");
2072 /* set up device control */
2073 if (ap
->ops
->sff_set_devctl
|| ap
->ioaddr
.ctl_addr
) {
2074 ata_sff_set_devctl(ap
, ap
->ctl
);
2075 ap
->last_ctl
= ap
->ctl
;
2078 EXPORT_SYMBOL_GPL(ata_sff_postreset
);
2081 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2084 * Drain the FIFO and device of any stuck data following a command
2085 * failing to complete. In some cases this is necessary before a
2086 * reset will recover the device.
2090 void ata_sff_drain_fifo(struct ata_queued_cmd
*qc
)
2093 struct ata_port
*ap
;
2095 /* We only need to flush incoming data when a command was running */
2096 if (qc
== NULL
|| qc
->dma_dir
== DMA_TO_DEVICE
)
2100 /* Drain up to 64K of data before we give up this recovery method */
2101 for (count
= 0; (ap
->ops
->sff_check_status(ap
) & ATA_DRQ
)
2102 && count
< 65536; count
+= 2)
2103 ioread16(ap
->ioaddr
.data_addr
);
2105 /* Can become DEBUG later */
2107 ata_port_dbg(ap
, "drained %d bytes to clear DRQ\n", count
);
2110 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo
);
2113 * ata_sff_error_handler - Stock error handler for SFF controller
2114 * @ap: port to handle error for
2116 * Stock error handler for SFF controller. It can handle both
2117 * PATA and SATA controllers. Many controllers should be able to
2118 * use this EH as-is or with some added handling before and
2122 * Kernel thread context (may sleep)
2124 void ata_sff_error_handler(struct ata_port
*ap
)
2126 ata_reset_fn_t softreset
= ap
->ops
->softreset
;
2127 ata_reset_fn_t hardreset
= ap
->ops
->hardreset
;
2128 struct ata_queued_cmd
*qc
;
2129 unsigned long flags
;
2131 qc
= __ata_qc_from_tag(ap
, ap
->link
.active_tag
);
2132 if (qc
&& !(qc
->flags
& ATA_QCFLAG_FAILED
))
2135 spin_lock_irqsave(ap
->lock
, flags
);
2138 * We *MUST* do FIFO draining before we issue a reset as
2139 * several devices helpfully clear their internal state and
2140 * will lock solid if we touch the data port post reset. Pass
2141 * qc in case anyone wants to do different PIO/DMA recovery or
2142 * has per command fixups
2144 if (ap
->ops
->sff_drain_fifo
)
2145 ap
->ops
->sff_drain_fifo(qc
);
2147 spin_unlock_irqrestore(ap
->lock
, flags
);
2149 /* ignore built-in hardresets if SCR access is not available */
2150 if ((hardreset
== sata_std_hardreset
||
2151 hardreset
== sata_sff_hardreset
) && !sata_scr_valid(&ap
->link
))
2154 ata_do_eh(ap
, ap
->ops
->prereset
, softreset
, hardreset
,
2155 ap
->ops
->postreset
);
2157 EXPORT_SYMBOL_GPL(ata_sff_error_handler
);
2160 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2161 * @ioaddr: IO address structure to be initialized
2163 * Utility function which initializes data_addr, error_addr,
2164 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2165 * device_addr, status_addr, and command_addr to standard offsets
2166 * relative to cmd_addr.
2168 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2170 void ata_sff_std_ports(struct ata_ioports
*ioaddr
)
2172 ioaddr
->data_addr
= ioaddr
->cmd_addr
+ ATA_REG_DATA
;
2173 ioaddr
->error_addr
= ioaddr
->cmd_addr
+ ATA_REG_ERR
;
2174 ioaddr
->feature_addr
= ioaddr
->cmd_addr
+ ATA_REG_FEATURE
;
2175 ioaddr
->nsect_addr
= ioaddr
->cmd_addr
+ ATA_REG_NSECT
;
2176 ioaddr
->lbal_addr
= ioaddr
->cmd_addr
+ ATA_REG_LBAL
;
2177 ioaddr
->lbam_addr
= ioaddr
->cmd_addr
+ ATA_REG_LBAM
;
2178 ioaddr
->lbah_addr
= ioaddr
->cmd_addr
+ ATA_REG_LBAH
;
2179 ioaddr
->device_addr
= ioaddr
->cmd_addr
+ ATA_REG_DEVICE
;
2180 ioaddr
->status_addr
= ioaddr
->cmd_addr
+ ATA_REG_STATUS
;
2181 ioaddr
->command_addr
= ioaddr
->cmd_addr
+ ATA_REG_CMD
;
2183 EXPORT_SYMBOL_GPL(ata_sff_std_ports
);
2187 static int ata_resources_present(struct pci_dev
*pdev
, int port
)
2191 /* Check the PCI resources for this channel are enabled */
2193 for (i
= 0; i
< 2; i
++) {
2194 if (pci_resource_start(pdev
, port
+ i
) == 0 ||
2195 pci_resource_len(pdev
, port
+ i
) == 0)
2202 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2203 * @host: target ATA host
2205 * Acquire native PCI ATA resources for @host and initialize the
2206 * first two ports of @host accordingly. Ports marked dummy are
2207 * skipped and allocation failure makes the port dummy.
2209 * Note that native PCI resources are valid even for legacy hosts
2210 * as we fix up pdev resources array early in boot, so this
2211 * function can be used for both native and legacy SFF hosts.
2214 * Inherited from calling layer (may sleep).
2217 * 0 if at least one port is initialized, -ENODEV if no port is
2220 int ata_pci_sff_init_host(struct ata_host
*host
)
2222 struct device
*gdev
= host
->dev
;
2223 struct pci_dev
*pdev
= to_pci_dev(gdev
);
2224 unsigned int mask
= 0;
2227 /* request, iomap BARs and init port addresses accordingly */
2228 for (i
= 0; i
< 2; i
++) {
2229 struct ata_port
*ap
= host
->ports
[i
];
2231 void __iomem
* const *iomap
;
2233 if (ata_port_is_dummy(ap
))
2236 /* Discard disabled ports. Some controllers show
2237 * their unused channels this way. Disabled ports are
2240 if (!ata_resources_present(pdev
, i
)) {
2241 ap
->ops
= &ata_dummy_port_ops
;
2245 rc
= pcim_iomap_regions(pdev
, 0x3 << base
,
2246 dev_driver_string(gdev
));
2249 "failed to request/iomap BARs for port %d (errno=%d)\n",
2252 pcim_pin_device(pdev
);
2253 ap
->ops
= &ata_dummy_port_ops
;
2256 host
->iomap
= iomap
= pcim_iomap_table(pdev
);
2258 ap
->ioaddr
.cmd_addr
= iomap
[base
];
2259 ap
->ioaddr
.altstatus_addr
=
2260 ap
->ioaddr
.ctl_addr
= (void __iomem
*)
2261 ((unsigned long)iomap
[base
+ 1] | ATA_PCI_CTL_OFS
);
2262 ata_sff_std_ports(&ap
->ioaddr
);
2264 ata_port_desc(ap
, "cmd 0x%llx ctl 0x%llx",
2265 (unsigned long long)pci_resource_start(pdev
, base
),
2266 (unsigned long long)pci_resource_start(pdev
, base
+ 1));
2272 dev_err(gdev
, "no available native port\n");
2278 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host
);
2281 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2282 * @pdev: target PCI device
2283 * @ppi: array of port_info, must be enough for two ports
2284 * @r_host: out argument for the initialized ATA host
2286 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2287 * all PCI resources and initialize it accordingly in one go.
2290 * Inherited from calling layer (may sleep).
2293 * 0 on success, -errno otherwise.
2295 int ata_pci_sff_prepare_host(struct pci_dev
*pdev
,
2296 const struct ata_port_info
* const *ppi
,
2297 struct ata_host
**r_host
)
2299 struct ata_host
*host
;
2302 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
))
2305 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, 2);
2307 dev_err(&pdev
->dev
, "failed to allocate ATA host\n");
2312 rc
= ata_pci_sff_init_host(host
);
2316 devres_remove_group(&pdev
->dev
, NULL
);
2321 devres_release_group(&pdev
->dev
, NULL
);
2324 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host
);
2327 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2328 * @host: target SFF ATA host
2329 * @irq_handler: irq_handler used when requesting IRQ(s)
2330 * @sht: scsi_host_template to use when registering the host
2332 * This is the counterpart of ata_host_activate() for SFF ATA
2333 * hosts. This separate helper is necessary because SFF hosts
2334 * use two separate interrupts in legacy mode.
2337 * Inherited from calling layer (may sleep).
2340 * 0 on success, -errno otherwise.
2342 int ata_pci_sff_activate_host(struct ata_host
*host
,
2343 irq_handler_t irq_handler
,
2344 struct scsi_host_template
*sht
)
2346 struct device
*dev
= host
->dev
;
2347 struct pci_dev
*pdev
= to_pci_dev(dev
);
2348 const char *drv_name
= dev_driver_string(host
->dev
);
2349 int legacy_mode
= 0, rc
;
2351 rc
= ata_host_start(host
);
2355 if ((pdev
->class >> 8) == PCI_CLASS_STORAGE_IDE
) {
2359 * ATA spec says we should use legacy mode when one
2360 * port is in legacy mode, but disabled ports on some
2361 * PCI hosts appear as fixed legacy ports, e.g SB600/700
2362 * on which the secondary port is not wired, so
2363 * ignore ports that are marked as 'dummy' during
2366 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &tmp8
);
2367 if (!ata_port_is_dummy(host
->ports
[0]))
2369 if (!ata_port_is_dummy(host
->ports
[1]))
2371 if ((tmp8
& mask
) != mask
)
2375 if (!devres_open_group(dev
, NULL
, GFP_KERNEL
))
2378 if (!legacy_mode
&& pdev
->irq
) {
2381 rc
= devm_request_irq(dev
, pdev
->irq
, irq_handler
,
2382 IRQF_SHARED
, drv_name
, host
);
2386 for (i
= 0; i
< 2; i
++) {
2387 if (ata_port_is_dummy(host
->ports
[i
]))
2389 ata_port_desc(host
->ports
[i
], "irq %d", pdev
->irq
);
2391 } else if (legacy_mode
) {
2392 if (!ata_port_is_dummy(host
->ports
[0])) {
2393 rc
= devm_request_irq(dev
, ATA_PRIMARY_IRQ(pdev
),
2394 irq_handler
, IRQF_SHARED
,
2399 ata_port_desc(host
->ports
[0], "irq %d",
2400 ATA_PRIMARY_IRQ(pdev
));
2403 if (!ata_port_is_dummy(host
->ports
[1])) {
2404 rc
= devm_request_irq(dev
, ATA_SECONDARY_IRQ(pdev
),
2405 irq_handler
, IRQF_SHARED
,
2410 ata_port_desc(host
->ports
[1], "irq %d",
2411 ATA_SECONDARY_IRQ(pdev
));
2415 rc
= ata_host_register(host
, sht
);
2418 devres_remove_group(dev
, NULL
);
2420 devres_release_group(dev
, NULL
);
2424 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host
);
2426 static const struct ata_port_info
*ata_sff_find_valid_pi(
2427 const struct ata_port_info
* const *ppi
)
2431 /* look up the first valid port_info */
2432 for (i
= 0; i
< 2 && ppi
[i
]; i
++)
2433 if (ppi
[i
]->port_ops
!= &ata_dummy_port_ops
)
2439 static int ata_pci_init_one(struct pci_dev
*pdev
,
2440 const struct ata_port_info
* const *ppi
,
2441 struct scsi_host_template
*sht
, void *host_priv
,
2442 int hflags
, bool bmdma
)
2444 struct device
*dev
= &pdev
->dev
;
2445 const struct ata_port_info
*pi
;
2446 struct ata_host
*host
= NULL
;
2451 pi
= ata_sff_find_valid_pi(ppi
);
2453 dev_err(&pdev
->dev
, "no valid port_info specified\n");
2457 if (!devres_open_group(dev
, NULL
, GFP_KERNEL
))
2460 rc
= pcim_enable_device(pdev
);
2464 #ifdef CONFIG_ATA_BMDMA
2466 /* prepare and activate BMDMA host */
2467 rc
= ata_pci_bmdma_prepare_host(pdev
, ppi
, &host
);
2470 /* prepare and activate SFF host */
2471 rc
= ata_pci_sff_prepare_host(pdev
, ppi
, &host
);
2474 host
->private_data
= host_priv
;
2475 host
->flags
|= hflags
;
2477 #ifdef CONFIG_ATA_BMDMA
2479 pci_set_master(pdev
);
2480 rc
= ata_pci_sff_activate_host(host
, ata_bmdma_interrupt
, sht
);
2483 rc
= ata_pci_sff_activate_host(host
, ata_sff_interrupt
, sht
);
2486 devres_remove_group(&pdev
->dev
, NULL
);
2488 devres_release_group(&pdev
->dev
, NULL
);
2494 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2495 * @pdev: Controller to be initialized
2496 * @ppi: array of port_info, must be enough for two ports
2497 * @sht: scsi_host_template to use when registering the host
2498 * @host_priv: host private_data
2499 * @hflag: host flags
2501 * This is a helper function which can be called from a driver's
2502 * xxx_init_one() probe function if the hardware uses traditional
2503 * IDE taskfile registers and is PIO only.
2506 * Nobody makes a single channel controller that appears solely as
2507 * the secondary legacy port on PCI.
2510 * Inherited from PCI layer (may sleep).
2513 * Zero on success, negative on errno-based value on error.
2515 int ata_pci_sff_init_one(struct pci_dev
*pdev
,
2516 const struct ata_port_info
* const *ppi
,
2517 struct scsi_host_template
*sht
, void *host_priv
, int hflag
)
2519 return ata_pci_init_one(pdev
, ppi
, sht
, host_priv
, hflag
, 0);
2521 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one
);
2523 #endif /* CONFIG_PCI */
2529 #ifdef CONFIG_ATA_BMDMA
2531 const struct ata_port_operations ata_bmdma_port_ops
= {
2532 .inherits
= &ata_sff_port_ops
,
2534 .error_handler
= ata_bmdma_error_handler
,
2535 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
2537 .qc_prep
= ata_bmdma_qc_prep
,
2538 .qc_issue
= ata_bmdma_qc_issue
,
2540 .sff_irq_clear
= ata_bmdma_irq_clear
,
2541 .bmdma_setup
= ata_bmdma_setup
,
2542 .bmdma_start
= ata_bmdma_start
,
2543 .bmdma_stop
= ata_bmdma_stop
,
2544 .bmdma_status
= ata_bmdma_status
,
2546 .port_start
= ata_bmdma_port_start
,
2548 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops
);
2550 const struct ata_port_operations ata_bmdma32_port_ops
= {
2551 .inherits
= &ata_bmdma_port_ops
,
2553 .sff_data_xfer
= ata_sff_data_xfer32
,
2554 .port_start
= ata_bmdma_port_start32
,
2556 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops
);
2559 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2560 * @qc: Metadata associated with taskfile to be transferred
2562 * Fill PCI IDE PRD (scatter-gather) table with segments
2563 * associated with the current disk command.
2566 * spin_lock_irqsave(host lock)
2569 static void ata_bmdma_fill_sg(struct ata_queued_cmd
*qc
)
2571 struct ata_port
*ap
= qc
->ap
;
2572 struct ata_bmdma_prd
*prd
= ap
->bmdma_prd
;
2573 struct scatterlist
*sg
;
2574 unsigned int si
, pi
;
2577 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
2581 /* determine if physical DMA addr spans 64K boundary.
2582 * Note h/w doesn't support 64-bit, so we unconditionally
2583 * truncate dma_addr_t to u32.
2585 addr
= (u32
) sg_dma_address(sg
);
2586 sg_len
= sg_dma_len(sg
);
2589 offset
= addr
& 0xffff;
2591 if ((offset
+ sg_len
) > 0x10000)
2592 len
= 0x10000 - offset
;
2594 prd
[pi
].addr
= cpu_to_le32(addr
);
2595 prd
[pi
].flags_len
= cpu_to_le32(len
& 0xffff);
2596 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi
, addr
, len
);
2604 prd
[pi
- 1].flags_len
|= cpu_to_le32(ATA_PRD_EOT
);
2608 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2609 * @qc: Metadata associated with taskfile to be transferred
2611 * Fill PCI IDE PRD (scatter-gather) table with segments
2612 * associated with the current disk command. Perform the fill
2613 * so that we avoid writing any length 64K records for
2614 * controllers that don't follow the spec.
2617 * spin_lock_irqsave(host lock)
2620 static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd
*qc
)
2622 struct ata_port
*ap
= qc
->ap
;
2623 struct ata_bmdma_prd
*prd
= ap
->bmdma_prd
;
2624 struct scatterlist
*sg
;
2625 unsigned int si
, pi
;
2628 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
2630 u32 sg_len
, len
, blen
;
2632 /* determine if physical DMA addr spans 64K boundary.
2633 * Note h/w doesn't support 64-bit, so we unconditionally
2634 * truncate dma_addr_t to u32.
2636 addr
= (u32
) sg_dma_address(sg
);
2637 sg_len
= sg_dma_len(sg
);
2640 offset
= addr
& 0xffff;
2642 if ((offset
+ sg_len
) > 0x10000)
2643 len
= 0x10000 - offset
;
2645 blen
= len
& 0xffff;
2646 prd
[pi
].addr
= cpu_to_le32(addr
);
2648 /* Some PATA chipsets like the CS5530 can't
2649 cope with 0x0000 meaning 64K as the spec
2651 prd
[pi
].flags_len
= cpu_to_le32(0x8000);
2653 prd
[++pi
].addr
= cpu_to_le32(addr
+ 0x8000);
2655 prd
[pi
].flags_len
= cpu_to_le32(blen
);
2656 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi
, addr
, len
);
2664 prd
[pi
- 1].flags_len
|= cpu_to_le32(ATA_PRD_EOT
);
2668 * ata_bmdma_qc_prep - Prepare taskfile for submission
2669 * @qc: Metadata associated with taskfile to be prepared
2671 * Prepare ATA taskfile for submission.
2674 * spin_lock_irqsave(host lock)
2676 void ata_bmdma_qc_prep(struct ata_queued_cmd
*qc
)
2678 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
2681 ata_bmdma_fill_sg(qc
);
2683 EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep
);
2686 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2687 * @qc: Metadata associated with taskfile to be prepared
2689 * Prepare ATA taskfile for submission.
2692 * spin_lock_irqsave(host lock)
2694 void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd
*qc
)
2696 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
2699 ata_bmdma_fill_sg_dumb(qc
);
2701 EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep
);
2704 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2705 * @qc: command to issue to device
2707 * This function issues a PIO, NODATA or DMA command to a
2708 * SFF/BMDMA controller. PIO and NODATA are handled by
2709 * ata_sff_qc_issue().
2712 * spin_lock_irqsave(host lock)
2715 * Zero on success, AC_ERR_* mask on failure
2717 unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd
*qc
)
2719 struct ata_port
*ap
= qc
->ap
;
2720 struct ata_link
*link
= qc
->dev
->link
;
2722 /* defer PIO handling to sff_qc_issue */
2723 if (!ata_is_dma(qc
->tf
.protocol
))
2724 return ata_sff_qc_issue(qc
);
2726 /* select the device */
2727 ata_dev_select(ap
, qc
->dev
->devno
, 1, 0);
2729 /* start the command */
2730 switch (qc
->tf
.protocol
) {
2732 WARN_ON_ONCE(qc
->tf
.flags
& ATA_TFLAG_POLLING
);
2734 ap
->ops
->sff_tf_load(ap
, &qc
->tf
); /* load tf registers */
2735 ap
->ops
->bmdma_setup(qc
); /* set up bmdma */
2736 ap
->ops
->bmdma_start(qc
); /* initiate bmdma */
2737 ap
->hsm_task_state
= HSM_ST_LAST
;
2740 case ATAPI_PROT_DMA
:
2741 WARN_ON_ONCE(qc
->tf
.flags
& ATA_TFLAG_POLLING
);
2743 ap
->ops
->sff_tf_load(ap
, &qc
->tf
); /* load tf registers */
2744 ap
->ops
->bmdma_setup(qc
); /* set up bmdma */
2745 ap
->hsm_task_state
= HSM_ST_FIRST
;
2747 /* send cdb by polling if no cdb interrupt */
2748 if (!(qc
->dev
->flags
& ATA_DFLAG_CDB_INTR
))
2749 ata_sff_queue_pio_task(link
, 0);
2754 return AC_ERR_SYSTEM
;
2759 EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue
);
2762 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2763 * @ap: Port on which interrupt arrived (possibly...)
2764 * @qc: Taskfile currently active in engine
2766 * Handle port interrupt for given queued command.
2769 * spin_lock_irqsave(host lock)
2772 * One if interrupt was handled, zero if not (shared irq).
2774 unsigned int ata_bmdma_port_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
2776 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
2778 bool bmdma_stopped
= false;
2779 unsigned int handled
;
2781 if (ap
->hsm_task_state
== HSM_ST_LAST
&& ata_is_dma(qc
->tf
.protocol
)) {
2782 /* check status of DMA engine */
2783 host_stat
= ap
->ops
->bmdma_status(ap
);
2784 VPRINTK("ata%u: host_stat 0x%X\n", ap
->print_id
, host_stat
);
2786 /* if it's not our irq... */
2787 if (!(host_stat
& ATA_DMA_INTR
))
2788 return ata_sff_idle_irq(ap
);
2790 /* before we do anything else, clear DMA-Start bit */
2791 ap
->ops
->bmdma_stop(qc
);
2792 bmdma_stopped
= true;
2794 if (unlikely(host_stat
& ATA_DMA_ERR
)) {
2795 /* error when transferring data to/from memory */
2796 qc
->err_mask
|= AC_ERR_HOST_BUS
;
2797 ap
->hsm_task_state
= HSM_ST_ERR
;
2801 handled
= __ata_sff_port_intr(ap
, qc
, bmdma_stopped
);
2803 if (unlikely(qc
->err_mask
) && ata_is_dma(qc
->tf
.protocol
))
2804 ata_ehi_push_desc(ehi
, "BMDMA stat 0x%x", host_stat
);
2808 EXPORT_SYMBOL_GPL(ata_bmdma_port_intr
);
2811 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2812 * @irq: irq line (unused)
2813 * @dev_instance: pointer to our ata_host information structure
2815 * Default interrupt handler for PCI IDE devices. Calls
2816 * ata_bmdma_port_intr() for each port that is not disabled.
2819 * Obtains host lock during operation.
2822 * IRQ_NONE or IRQ_HANDLED.
2824 irqreturn_t
ata_bmdma_interrupt(int irq
, void *dev_instance
)
2826 return __ata_sff_interrupt(irq
, dev_instance
, ata_bmdma_port_intr
);
2828 EXPORT_SYMBOL_GPL(ata_bmdma_interrupt
);
2831 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2832 * @ap: port to handle error for
2834 * Stock error handler for BMDMA controller. It can handle both
2835 * PATA and SATA controllers. Most BMDMA controllers should be
2836 * able to use this EH as-is or with some added handling before
2840 * Kernel thread context (may sleep)
2842 void ata_bmdma_error_handler(struct ata_port
*ap
)
2844 struct ata_queued_cmd
*qc
;
2845 unsigned long flags
;
2848 qc
= __ata_qc_from_tag(ap
, ap
->link
.active_tag
);
2849 if (qc
&& !(qc
->flags
& ATA_QCFLAG_FAILED
))
2852 /* reset PIO HSM and stop DMA engine */
2853 spin_lock_irqsave(ap
->lock
, flags
);
2855 if (qc
&& ata_is_dma(qc
->tf
.protocol
)) {
2858 host_stat
= ap
->ops
->bmdma_status(ap
);
2860 /* BMDMA controllers indicate host bus error by
2861 * setting DMA_ERR bit and timing out. As it wasn't
2862 * really a timeout event, adjust error mask and
2863 * cancel frozen state.
2865 if (qc
->err_mask
== AC_ERR_TIMEOUT
&& (host_stat
& ATA_DMA_ERR
)) {
2866 qc
->err_mask
= AC_ERR_HOST_BUS
;
2870 ap
->ops
->bmdma_stop(qc
);
2872 /* if we're gonna thaw, make sure IRQ is clear */
2874 ap
->ops
->sff_check_status(ap
);
2875 if (ap
->ops
->sff_irq_clear
)
2876 ap
->ops
->sff_irq_clear(ap
);
2880 spin_unlock_irqrestore(ap
->lock
, flags
);
2883 ata_eh_thaw_port(ap
);
2885 ata_sff_error_handler(ap
);
2887 EXPORT_SYMBOL_GPL(ata_bmdma_error_handler
);
2890 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2891 * @qc: internal command to clean up
2894 * Kernel thread context (may sleep)
2896 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd
*qc
)
2898 struct ata_port
*ap
= qc
->ap
;
2899 unsigned long flags
;
2901 if (ata_is_dma(qc
->tf
.protocol
)) {
2902 spin_lock_irqsave(ap
->lock
, flags
);
2903 ap
->ops
->bmdma_stop(qc
);
2904 spin_unlock_irqrestore(ap
->lock
, flags
);
2907 EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd
);
2910 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2911 * @ap: Port associated with this ATA transaction.
2913 * Clear interrupt and error flags in DMA status register.
2915 * May be used as the irq_clear() entry in ata_port_operations.
2918 * spin_lock_irqsave(host lock)
2920 void ata_bmdma_irq_clear(struct ata_port
*ap
)
2922 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
2927 iowrite8(ioread8(mmio
+ ATA_DMA_STATUS
), mmio
+ ATA_DMA_STATUS
);
2929 EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear
);
2932 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2933 * @qc: Info associated with this ATA transaction.
2936 * spin_lock_irqsave(host lock)
2938 void ata_bmdma_setup(struct ata_queued_cmd
*qc
)
2940 struct ata_port
*ap
= qc
->ap
;
2941 unsigned int rw
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
2944 /* load PRD table addr. */
2945 mb(); /* make sure PRD table writes are visible to controller */
2946 iowrite32(ap
->bmdma_prd_dma
, ap
->ioaddr
.bmdma_addr
+ ATA_DMA_TABLE_OFS
);
2948 /* specify data direction, triple-check start bit is clear */
2949 dmactl
= ioread8(ap
->ioaddr
.bmdma_addr
+ ATA_DMA_CMD
);
2950 dmactl
&= ~(ATA_DMA_WR
| ATA_DMA_START
);
2952 dmactl
|= ATA_DMA_WR
;
2953 iowrite8(dmactl
, ap
->ioaddr
.bmdma_addr
+ ATA_DMA_CMD
);
2955 /* issue r/w command */
2956 ap
->ops
->sff_exec_command(ap
, &qc
->tf
);
2958 EXPORT_SYMBOL_GPL(ata_bmdma_setup
);
2961 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2962 * @qc: Info associated with this ATA transaction.
2965 * spin_lock_irqsave(host lock)
2967 void ata_bmdma_start(struct ata_queued_cmd
*qc
)
2969 struct ata_port
*ap
= qc
->ap
;
2972 /* start host DMA transaction */
2973 dmactl
= ioread8(ap
->ioaddr
.bmdma_addr
+ ATA_DMA_CMD
);
2974 iowrite8(dmactl
| ATA_DMA_START
, ap
->ioaddr
.bmdma_addr
+ ATA_DMA_CMD
);
2976 /* Strictly, one may wish to issue an ioread8() here, to
2977 * flush the mmio write. However, control also passes
2978 * to the hardware at this point, and it will interrupt
2979 * us when we are to resume control. So, in effect,
2980 * we don't care when the mmio write flushes.
2981 * Further, a read of the DMA status register _immediately_
2982 * following the write may not be what certain flaky hardware
2983 * is expected, so I think it is best to not add a readb()
2984 * without first all the MMIO ATA cards/mobos.
2985 * Or maybe I'm just being paranoid.
2987 * FIXME: The posting of this write means I/O starts are
2988 * unnecessarily delayed for MMIO
2991 EXPORT_SYMBOL_GPL(ata_bmdma_start
);
2994 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2995 * @qc: Command we are ending DMA for
2997 * Clears the ATA_DMA_START flag in the dma control register
2999 * May be used as the bmdma_stop() entry in ata_port_operations.
3002 * spin_lock_irqsave(host lock)
3004 void ata_bmdma_stop(struct ata_queued_cmd
*qc
)
3006 struct ata_port
*ap
= qc
->ap
;
3007 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
3009 /* clear start/stop bit */
3010 iowrite8(ioread8(mmio
+ ATA_DMA_CMD
) & ~ATA_DMA_START
,
3011 mmio
+ ATA_DMA_CMD
);
3013 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3014 ata_sff_dma_pause(ap
);
3016 EXPORT_SYMBOL_GPL(ata_bmdma_stop
);
3019 * ata_bmdma_status - Read PCI IDE BMDMA status
3020 * @ap: Port associated with this ATA transaction.
3022 * Read and return BMDMA status register.
3024 * May be used as the bmdma_status() entry in ata_port_operations.
3027 * spin_lock_irqsave(host lock)
3029 u8
ata_bmdma_status(struct ata_port
*ap
)
3031 return ioread8(ap
->ioaddr
.bmdma_addr
+ ATA_DMA_STATUS
);
3033 EXPORT_SYMBOL_GPL(ata_bmdma_status
);
3037 * ata_bmdma_port_start - Set port up for bmdma.
3038 * @ap: Port to initialize
3040 * Called just after data structures for each port are
3041 * initialized. Allocates space for PRD table.
3043 * May be used as the port_start() entry in ata_port_operations.
3046 * Inherited from caller.
3048 int ata_bmdma_port_start(struct ata_port
*ap
)
3050 if (ap
->mwdma_mask
|| ap
->udma_mask
) {
3052 dmam_alloc_coherent(ap
->host
->dev
, ATA_PRD_TBL_SZ
,
3053 &ap
->bmdma_prd_dma
, GFP_KERNEL
);
3060 EXPORT_SYMBOL_GPL(ata_bmdma_port_start
);
3063 * ata_bmdma_port_start32 - Set port up for dma.
3064 * @ap: Port to initialize
3066 * Called just after data structures for each port are
3067 * initialized. Enables 32bit PIO and allocates space for PRD
3070 * May be used as the port_start() entry in ata_port_operations for
3071 * devices that are capable of 32bit PIO.
3074 * Inherited from caller.
3076 int ata_bmdma_port_start32(struct ata_port
*ap
)
3078 ap
->pflags
|= ATA_PFLAG_PIO32
| ATA_PFLAG_PIO32CHANGE
;
3079 return ata_bmdma_port_start(ap
);
3081 EXPORT_SYMBOL_GPL(ata_bmdma_port_start32
);
3086 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3089 * Some PCI ATA devices report simplex mode but in fact can be told to
3090 * enter non simplex mode. This implements the necessary logic to
3091 * perform the task on such devices. Calling it on other devices will
3092 * have -undefined- behaviour.
3094 int ata_pci_bmdma_clear_simplex(struct pci_dev
*pdev
)
3096 unsigned long bmdma
= pci_resource_start(pdev
, 4);
3102 simplex
= inb(bmdma
+ 0x02);
3103 outb(simplex
& 0x60, bmdma
+ 0x02);
3104 simplex
= inb(bmdma
+ 0x02);
3109 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex
);
3111 static void ata_bmdma_nodma(struct ata_host
*host
, const char *reason
)
3115 dev_err(host
->dev
, "BMDMA: %s, falling back to PIO\n", reason
);
3117 for (i
= 0; i
< 2; i
++) {
3118 host
->ports
[i
]->mwdma_mask
= 0;
3119 host
->ports
[i
]->udma_mask
= 0;
3124 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3125 * @host: target ATA host
3127 * Acquire PCI BMDMA resources and initialize @host accordingly.
3130 * Inherited from calling layer (may sleep).
3132 void ata_pci_bmdma_init(struct ata_host
*host
)
3134 struct device
*gdev
= host
->dev
;
3135 struct pci_dev
*pdev
= to_pci_dev(gdev
);
3138 /* No BAR4 allocation: No DMA */
3139 if (pci_resource_start(pdev
, 4) == 0) {
3140 ata_bmdma_nodma(host
, "BAR4 is zero");
3145 * Some controllers require BMDMA region to be initialized
3146 * even if DMA is not in use to clear IRQ status via
3147 * ->sff_irq_clear method. Try to initialize bmdma_addr
3148 * regardless of dma masks.
3150 rc
= dma_set_mask(&pdev
->dev
, ATA_DMA_MASK
);
3152 ata_bmdma_nodma(host
, "failed to set dma mask");
3154 rc
= dma_set_coherent_mask(&pdev
->dev
, ATA_DMA_MASK
);
3156 ata_bmdma_nodma(host
,
3157 "failed to set consistent dma mask");
3160 /* request and iomap DMA region */
3161 rc
= pcim_iomap_regions(pdev
, 1 << 4, dev_driver_string(gdev
));
3163 ata_bmdma_nodma(host
, "failed to request/iomap BAR4");
3166 host
->iomap
= pcim_iomap_table(pdev
);
3168 for (i
= 0; i
< 2; i
++) {
3169 struct ata_port
*ap
= host
->ports
[i
];
3170 void __iomem
*bmdma
= host
->iomap
[4] + 8 * i
;
3172 if (ata_port_is_dummy(ap
))
3175 ap
->ioaddr
.bmdma_addr
= bmdma
;
3176 if ((!(ap
->flags
& ATA_FLAG_IGN_SIMPLEX
)) &&
3177 (ioread8(bmdma
+ 2) & 0x80))
3178 host
->flags
|= ATA_HOST_SIMPLEX
;
3180 ata_port_desc(ap
, "bmdma 0x%llx",
3181 (unsigned long long)pci_resource_start(pdev
, 4) + 8 * i
);
3184 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init
);
3187 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3188 * @pdev: target PCI device
3189 * @ppi: array of port_info, must be enough for two ports
3190 * @r_host: out argument for the initialized ATA host
3192 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3193 * resources and initialize it accordingly in one go.
3196 * Inherited from calling layer (may sleep).
3199 * 0 on success, -errno otherwise.
3201 int ata_pci_bmdma_prepare_host(struct pci_dev
*pdev
,
3202 const struct ata_port_info
* const * ppi
,
3203 struct ata_host
**r_host
)
3207 rc
= ata_pci_sff_prepare_host(pdev
, ppi
, r_host
);
3211 ata_pci_bmdma_init(*r_host
);
3214 EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host
);
3217 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3218 * @pdev: Controller to be initialized
3219 * @ppi: array of port_info, must be enough for two ports
3220 * @sht: scsi_host_template to use when registering the host
3221 * @host_priv: host private_data
3222 * @hflags: host flags
3224 * This function is similar to ata_pci_sff_init_one() but also
3225 * takes care of BMDMA initialization.
3228 * Inherited from PCI layer (may sleep).
3231 * Zero on success, negative on errno-based value on error.
3233 int ata_pci_bmdma_init_one(struct pci_dev
*pdev
,
3234 const struct ata_port_info
* const * ppi
,
3235 struct scsi_host_template
*sht
, void *host_priv
,
3238 return ata_pci_init_one(pdev
, ppi
, sht
, host_priv
, hflags
, 1);
3240 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one
);
3242 #endif /* CONFIG_PCI */
3243 #endif /* CONFIG_ATA_BMDMA */
3246 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3247 * @ap: Port to initialize
3249 * Called on port allocation to initialize SFF/BMDMA specific
3255 void ata_sff_port_init(struct ata_port
*ap
)
3257 INIT_DELAYED_WORK(&ap
->sff_pio_task
, ata_sff_pio_task
);
3258 ap
->ctl
= ATA_DEVCTL_OBS
;
3259 ap
->last_ctl
= 0xFF;
3262 int __init
ata_sff_init(void)
3264 ata_sff_wq
= alloc_workqueue("ata_sff", WQ_MEM_RECLAIM
, WQ_MAX_ACTIVE
);
3271 void ata_sff_exit(void)
3273 destroy_workqueue(ata_sff_wq
);