drivers/ata/pata_ixp4xx_cf.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ixp4xx PATA/Compact Flash driver
   4  * Copyright (C) 2006-07 Tower Technologies
   5  * Author: Alessandro Zummo <a.zummo@towertech.it>
   6  *
   7  * An ATA driver to handle a Compact Flash connected
   8  * to the ixp4xx expansion bus in TrueIDE mode. The CF
   9  * must have it chip selects connected to two CS lines
  10  * on the ixp4xx. In the irq is not available, you might
  11  * want to modify both this driver and libata to run in
  12  * polling mode.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/module.h>
  18 #include <linux/libata.h>
  19 #include <linux/irq.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <scsi/scsi_host.h>
  23
  24 #define DRV_NAME        "pata_ixp4xx_cf"
  25 #define DRV_VERSION     "1.0"
  26
  27 struct ixp4xx_pata {
  28         struct ata_host *host;
  29         struct regmap *rmap;
  30         u32 cmd_csreg;
  31         void __iomem *cmd;
  32         void __iomem *ctl;
  33 };
  34
  35 #define IXP4XX_EXP_TIMING_STRIDE        0x04
  36 /* The timings for the chipselect is in bits 29..16 */
  37 #define IXP4XX_EXP_T1_T5_MASK   GENMASK(29, 16)
  38 #define IXP4XX_EXP_PIO_0_8      0x0a470000
  39 #define IXP4XX_EXP_PIO_1_8      0x06430000
  40 #define IXP4XX_EXP_PIO_2_8      0x02410000
  41 #define IXP4XX_EXP_PIO_3_8      0x00820000
  42 #define IXP4XX_EXP_PIO_4_8      0x00400000
  43 #define IXP4XX_EXP_PIO_0_16     0x29640000
  44 #define IXP4XX_EXP_PIO_1_16     0x05030000
  45 #define IXP4XX_EXP_PIO_2_16     0x00b20000
  46 #define IXP4XX_EXP_PIO_3_16     0x00820000
  47 #define IXP4XX_EXP_PIO_4_16     0x00400000
  48 #define IXP4XX_EXP_BW_MASK      (BIT(6)|BIT(0))
  49 #define IXP4XX_EXP_BYTE_RD16    BIT(6) /* Byte reads on half-word devices */
  50 #define IXP4XX_EXP_BYTE_EN      BIT(0) /* Use 8bit data bus if set */
  51
  52 static void ixp4xx_set_8bit_timing(struct ixp4xx_pata *ixpp, u8 pio_mode)
  53 {
  54         switch (pio_mode) {
  55         case XFER_PIO_0:
  56                 regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
  57                                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_0_8);
  58                 break;
  59         case XFER_PIO_1:
  60                 regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
  61                                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_1_8);
  62                 break;
  63         case XFER_PIO_2:
  64                 regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
  65                                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_2_8);
  66                 break;
  67         case XFER_PIO_3:
  68                 regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
  69                                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_3_8);
  70                 break;
  71         case XFER_PIO_4:
  72                 regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
  73                                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_4_8);
  74                 break;
  75         default:
  76                 break;
  77         }
  78         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
  79                            IXP4XX_EXP_BW_MASK, IXP4XX_EXP_BYTE_RD16|IXP4XX_EXP_BYTE_EN);
  80 }
  81
  82 static void ixp4xx_set_16bit_timing(struct ixp4xx_pata *ixpp, u8 pio_mode)
  83 {
  84         switch (pio_mode){
  85         case XFER_PIO_0:
  86                 regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
  87                                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_0_16);
  88                 break;
  89         case XFER_PIO_1:
  90                 regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
  91                                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_1_16);
  92                 break;
  93         case XFER_PIO_2:
  94                 regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
  95                                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_2_16);
  96                 break;
  97         case XFER_PIO_3:
  98                 regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
  99                                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_3_16);
 100                 break;
 101         case XFER_PIO_4:
 102                 regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
 103                                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_4_16);
 104                 break;
 105         default:
 106                 break;
 107         }
 108         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
 109                            IXP4XX_EXP_BW_MASK, IXP4XX_EXP_BYTE_RD16);
 110 }
 111
 112 /* This sets up the timing on the chipselect CMD accordingly */
 113 static void ixp4xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
 114 {
 115         struct ixp4xx_pata *ixpp = ap->host->private_data;
 116
 117         ata_dev_info(adev, "configured for PIO%d 8bit\n",
 118                        adev->pio_mode - XFER_PIO_0);
 119         ixp4xx_set_8bit_timing(ixpp, adev->pio_mode);
 120 }
 121
 122
 123 static unsigned int ixp4xx_mmio_data_xfer(struct ata_queued_cmd *qc,
 124                                           unsigned char *buf, unsigned int buflen, int rw)
 125 {
 126         unsigned int i;
 127         unsigned int words = buflen >> 1;
 128         u16 *buf16 = (u16 *) buf;
 129         struct ata_device *adev = qc->dev;
 130         struct ata_port *ap = qc->dev->link->ap;
 131         void __iomem *mmio = ap->ioaddr.data_addr;
 132         struct ixp4xx_pata *ixpp = ap->host->private_data;
 133         unsigned long flags;
 134
 135         ata_dev_dbg(adev, "%s %d bytes\n", (rw == READ) ? "READ" : "WRITE",
 136                     buflen);
 137         spin_lock_irqsave(ap->lock, flags);
 138
 139         /* set the expansion bus in 16bit mode and restore
 140          * 8 bit mode after the transaction.
 141          */
 142         ixp4xx_set_16bit_timing(ixpp, adev->pio_mode);
 143         udelay(5);
 144
 145         /* Transfer multiple of 2 bytes */
 146         if (rw == READ)
 147                 for (i = 0; i < words; i++)
 148                         buf16[i] = readw(mmio);
 149         else
 150                 for (i = 0; i < words; i++)
 151                         writew(buf16[i], mmio);
 152
 153         /* Transfer trailing 1 byte, if any. */
 154         if (unlikely(buflen & 0x01)) {
 155                 u16 align_buf[1] = { 0 };
 156                 unsigned char *trailing_buf = buf + buflen - 1;
 157
 158                 if (rw == READ) {
 159                         align_buf[0] = readw(mmio);
 160                         memcpy(trailing_buf, align_buf, 1);
 161                 } else {
 162                         memcpy(align_buf, trailing_buf, 1);
 163                         writew(align_buf[0], mmio);
 164                 }
 165                 words++;
 166         }
 167
 168         ixp4xx_set_8bit_timing(ixpp, adev->pio_mode);
 169         udelay(5);
 170
 171         spin_unlock_irqrestore(ap->lock, flags);
 172
 173         return words << 1;
 174 }
 175
 176 static struct scsi_host_template ixp4xx_sht = {
 177         ATA_PIO_SHT(DRV_NAME),
 178 };
 179
 180 static struct ata_port_operations ixp4xx_port_ops = {
 181         .inherits               = &ata_sff_port_ops,
 182         .sff_data_xfer          = ixp4xx_mmio_data_xfer,
 183         .cable_detect           = ata_cable_40wire,
 184         .set_piomode            = ixp4xx_set_piomode,
 185 };
 186
 187 static struct ata_port_info ixp4xx_port_info = {
 188         .flags          = ATA_FLAG_NO_ATAPI,
 189         .pio_mask       = ATA_PIO4,
 190         .port_ops       = &ixp4xx_port_ops,
 191 };
 192
 193 static void ixp4xx_setup_port(struct ata_port *ap,
 194                               struct ixp4xx_pata *ixpp,
 195                               unsigned long raw_cmd, unsigned long raw_ctl)
 196 {
 197         struct ata_ioports *ioaddr = &ap->ioaddr;
 198
 199         raw_ctl += 0x06;
 200         ioaddr->cmd_addr        = ixpp->cmd;
 201         ioaddr->altstatus_addr  = ixpp->ctl + 0x06;
 202         ioaddr->ctl_addr        = ixpp->ctl + 0x06;
 203
 204         ata_sff_std_ports(ioaddr);
 205
 206         if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
 207                 /* adjust the addresses to handle the address swizzling of the
 208                  * ixp4xx in little endian mode.
 209                  */
 210
 211                 *(unsigned long *)&ioaddr->data_addr            ^= 0x02;
 212                 *(unsigned long *)&ioaddr->cmd_addr             ^= 0x03;
 213                 *(unsigned long *)&ioaddr->altstatus_addr       ^= 0x03;
 214                 *(unsigned long *)&ioaddr->ctl_addr             ^= 0x03;
 215                 *(unsigned long *)&ioaddr->error_addr           ^= 0x03;
 216                 *(unsigned long *)&ioaddr->feature_addr         ^= 0x03;
 217                 *(unsigned long *)&ioaddr->nsect_addr           ^= 0x03;
 218                 *(unsigned long *)&ioaddr->lbal_addr            ^= 0x03;
 219                 *(unsigned long *)&ioaddr->lbam_addr            ^= 0x03;
 220                 *(unsigned long *)&ioaddr->lbah_addr            ^= 0x03;
 221                 *(unsigned long *)&ioaddr->device_addr          ^= 0x03;
 222                 *(unsigned long *)&ioaddr->status_addr          ^= 0x03;
 223                 *(unsigned long *)&ioaddr->command_addr         ^= 0x03;
 224
 225                 raw_cmd ^= 0x03;
 226                 raw_ctl ^= 0x03;
 227         }
 228
 229         ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", raw_cmd, raw_ctl);
 230 }
 231
 232 static int ixp4xx_pata_probe(struct platform_device *pdev)
 233 {
 234         struct resource *cmd, *ctl;
 235         struct ata_port_info pi = ixp4xx_port_info;
 236         const struct ata_port_info *ppi[] = { &pi, NULL };
 237         struct device *dev = &pdev->dev;
 238         struct device_node *np = dev->of_node;
 239         struct ixp4xx_pata *ixpp;
 240         u32 csindex;
 241         int ret;
 242         int irq;
 243
 244         cmd = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 245         ctl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 246
 247         if (!cmd || !ctl)
 248                 return -EINVAL;
 249
 250         ixpp = devm_kzalloc(dev, sizeof(*ixpp), GFP_KERNEL);
 251         if (!ixpp)
 252                 return -ENOMEM;
 253
 254         ixpp->rmap = syscon_node_to_regmap(np->parent);
 255         if (IS_ERR(ixpp->rmap))
 256                 return dev_err_probe(dev, PTR_ERR(ixpp->rmap), "no regmap\n");
 257         /* Inspect our address to figure out what chipselect the CMD is on */
 258         ret = of_property_read_u32_index(np, "reg", 0, &csindex);
 259         if (ret)
 260                 return dev_err_probe(dev, ret, "can't inspect CMD address\n");
 261         dev_info(dev, "using CS%d for PIO timing configuration\n", csindex);
 262         ixpp->cmd_csreg = csindex * IXP4XX_EXP_TIMING_STRIDE;
 263
 264         ixpp->host = ata_host_alloc_pinfo(dev, ppi, 1);
 265         if (!ixpp->host)
 266                 return -ENOMEM;
 267         ixpp->host->private_data = ixpp;
 268
 269         ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
 270         if (ret)
 271                 return ret;
 272
 273         ixpp->cmd = devm_ioremap_resource(dev, cmd);
 274         ixpp->ctl = devm_ioremap_resource(dev, ctl);
 275         if (IS_ERR(ixpp->cmd) || IS_ERR(ixpp->ctl))
 276                 return -ENOMEM;
 277
 278         irq = platform_get_irq(pdev, 0);
 279         if (irq > 0)
 280                 irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
 281         else if (irq < 0)
 282                 return irq;
 283         else
 284                 return -EINVAL;
 285
 286         /* Just one port to set up */
 287         ixp4xx_setup_port(ixpp->host->ports[0], ixpp, cmd->start, ctl->start);
 288
 289         ata_print_version_once(dev, DRV_VERSION);
 290
 291         return ata_host_activate(ixpp->host, irq, ata_sff_interrupt, 0, &ixp4xx_sht);
 292 }
 293
 294 static const struct of_device_id ixp4xx_pata_of_match[] = {
 295         { .compatible = "intel,ixp4xx-compact-flash", },
 296         { /* sentinel */ }
 297 };
 298
 299 static struct platform_driver ixp4xx_pata_platform_driver = {
 300         .driver  = {
 301                 .name   = DRV_NAME,
 302                 .of_match_table = ixp4xx_pata_of_match,
 303         },
 304         .probe          = ixp4xx_pata_probe,
 305         .remove         = ata_platform_remove_one,
 306 };
 307
 308 module_platform_driver(ixp4xx_pata_platform_driver);
 309
 310 MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
 311 MODULE_DESCRIPTION("low-level driver for ixp4xx Compact Flash PATA");
 312 MODULE_LICENSE("GPL");
 313 MODULE_VERSION(DRV_VERSION);
 314 MODULE_ALIAS("platform:" DRV_NAME);