1 #ifndef __ATI_RADEON_FB_H
2 #define __ATI_RADEON_FB_H
4 /***************************************************************
5 * Most of the definitions here are adapted right from XFree86 *
6 ***************************************************************/
9 * Chip families. Must fit in the low 16 bits of a long word
16 CHIP_FAMILY_RS100
, /* U1 (IGP320M) or A3 (IGP320)*/
18 CHIP_FAMILY_RS200
, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
22 CHIP_FAMILY_RS300
, /* Radeon 9000 IGP */
27 CHIP_FAMILY_RV380
, /* RV370/RV380/M22/M24 */
28 CHIP_FAMILY_R420
, /* R420/R423/M18 */
32 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
33 ((rinfo)->family == CHIP_FAMILY_RV200) || \
34 ((rinfo)->family == CHIP_FAMILY_RS100) || \
35 ((rinfo)->family == CHIP_FAMILY_RS200) || \
36 ((rinfo)->family == CHIP_FAMILY_RV250) || \
37 ((rinfo)->family == CHIP_FAMILY_RV280) || \
38 ((rinfo)->family == CHIP_FAMILY_RS300))
40 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
41 ((rinfo)->family == CHIP_FAMILY_RV350) || \
42 ((rinfo)->family == CHIP_FAMILY_R350) || \
43 ((rinfo)->family == CHIP_FAMILY_RV380) || \
44 ((rinfo)->family == CHIP_FAMILY_R420))
46 struct radeonfb_info
{
49 struct pci_device_id pdev
;
66 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
67 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
68 #define INREG16(addr) readw((rinfo->mmio_base)+addr)
69 #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
70 #define INREG(addr) readl((rinfo->mmio_base)+addr)
71 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
73 static inline void _OUTREGP(struct radeonfb_info
*rinfo
, u32 addr
,
84 #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
87 * 2D Engine helper routines
89 static inline void radeon_engine_flush (struct radeonfb_info
*rinfo
)
94 OUTREGP(RB2D_DSTCACHE_CTLSTAT
, RB2D_DC_FLUSH_ALL
,
97 for (i
=0; i
< 2000000; i
++) {
98 if (!(INREG(RB2D_DSTCACHE_CTLSTAT
) & RB2D_DC_BUSY
))
102 printf("radeonfb: Flush Timeout !\n");
105 static inline void _radeon_fifo_wait(struct radeonfb_info
*rinfo
, int entries
)
109 for (i
=0; i
<2000000; i
++) {
110 if ((INREG(RBBM_STATUS
) & 0x7f) >= entries
)
114 printf("radeonfb: FIFO Timeout !\n");
117 static inline void _radeon_engine_idle(struct radeonfb_info
*rinfo
)
121 /* ensure FIFO is empty before waiting for idle */
122 _radeon_fifo_wait (rinfo
, 64);
124 for (i
=0; i
<2000000; i
++) {
125 if (((INREG(RBBM_STATUS
) & GUI_ACTIVE
)) == 0) {
126 radeon_engine_flush (rinfo
);
131 printf("radeonfb: Idle Timeout !\n");
134 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
135 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
136 #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
139 * This structure contains the various registers manipulated by this
140 * driver for setting or restoring a mode. It's mostly copied from
141 * XFree's RADEONSaveRec structure. A few chip settings might still be
142 * tweaked without beeing reflected or saved in these registers though
145 /* Common registers */
147 u32 ovr_wid_left_right
;
148 u32 ovr_wid_top_bottom
;
162 /* Other registers to save for VT switches or driver load/unload */
165 u32 clock_cntl_index
;
169 /* Surface/tiling registers */
170 u32 surf_lower_bound
[8];
171 u32 surf_upper_bound
[8];
178 u32 crtc_h_total_disp
;
179 u32 crtc_h_sync_strt_wid
;
180 u32 crtc_v_total_disp
;
181 u32 crtc_v_sync_strt_wid
;
183 u32 crtc_offset_cntl
;
186 u32 grph_buffer_cntl
;
189 /* CRTC2 registers */
192 u32 disp_output_cntl
;
194 u32 disp2_merge_cntl
;
195 u32 grph2_buffer_cntl
;
196 u32 crtc2_h_total_disp
;
197 u32 crtc2_h_sync_strt_wid
;
198 u32 crtc2_v_total_disp
;
199 u32 crtc2_v_sync_strt_wid
;
201 u32 crtc2_offset_cntl
;
204 /* Flat panel regs */
205 u32 fp_crtc_h_total_disp
;
206 u32 fp_crtc_v_total_disp
;
209 u32 fp_h_sync_strt_wid
;
210 u32 fp2_h_sync_strt_wid
;
213 u32 fp_v_sync_strt_wid
;
214 u32 fp2_v_sync_strt_wid
;
219 u32 tmds_transmitter_cntl
;
221 /* Computed values for PLL */
232 /* Computed values for PLL2 */
233 u32 dot_clock_freq_2
;
246 static inline u32
__INPLL(struct radeonfb_info
*rinfo
, u32 addr
)
250 OUTREG8(CLOCK_CNTL_INDEX
, addr
& 0x0000003f);
251 /* radeon_pll_errata_after_index(rinfo); */
252 data
= INREG(CLOCK_CNTL_DATA
);
253 /* radeon_pll_errata_after_data(rinfo); */
257 static inline void __OUTPLL(struct radeonfb_info
*rinfo
, unsigned int index
,
261 OUTREG8(CLOCK_CNTL_INDEX
, (index
& 0x0000003f) | 0x00000080);
262 /* radeon_pll_errata_after_index(rinfo); */
263 OUTREG(CLOCK_CNTL_DATA
, val
);
264 /* radeon_pll_errata_after_data(rinfo); */
267 static inline void __OUTPLLP(struct radeonfb_info
*rinfo
, unsigned int index
,
272 tmp
= __INPLL(rinfo
, index
);
275 __OUTPLL(rinfo
, index
, tmp
);
278 #define INPLL(addr) __INPLL(rinfo, addr)
279 #define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
280 #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)