2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference on libata and ahci drvier in kernel
14 #include <asm/processor.h>
15 #include <asm/errno.h>
20 #include <linux/ctype.h>
23 static int ata_io_flush(u8 port
);
25 struct ahci_probe_ent
*probe_ent
= NULL
;
26 hd_driveid_t
*ataid
[AHCI_MAX_PORTS
];
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 10000
42 #define WAIT_MS_DATAIO 5000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 4
46 static inline u32
ahci_port_base(u32 base
, u32 port
)
48 return base
+ 0x100 + (port
* 0x80);
52 static void ahci_setup_port(struct ahci_ioports
*port
, unsigned long base
,
53 unsigned int port_idx
)
55 base
= ahci_port_base(base
, port_idx
);
57 port
->cmd_addr
= base
;
58 port
->scr_addr
= base
+ PORT_SCR
;
62 #define msleep(a) udelay(a * 1000)
64 static void ahci_dcache_flush_range(unsigned begin
, unsigned len
)
66 const unsigned long start
= begin
;
67 const unsigned long end
= start
+ len
;
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
70 flush_dcache_range(start
, end
);
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
78 static void ahci_dcache_invalidate_range(unsigned begin
, unsigned len
)
80 const unsigned long start
= begin
;
81 const unsigned long end
= start
+ len
;
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
84 invalidate_dcache_range(start
, end
);
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports
*pp
)
93 ahci_dcache_flush_range((unsigned long)pp
->cmd_slot
,
94 AHCI_PORT_PRIV_DMA_SZ
);
97 static int waiting_for_cmd_completed(volatile u8
*offset
,
104 for (i
= 0; ((status
= readl(offset
)) & sign
) && i
< timeout_msec
; i
++)
107 return (i
< timeout_msec
) ? 0 : -1;
111 static int ahci_host_init(struct ahci_probe_ent
*probe_ent
)
113 #ifndef CONFIG_SCSI_AHCI_PLAT
114 pci_dev_t pdev
= probe_ent
->dev
;
116 unsigned short vendor
;
118 volatile u8
*mmio
= (volatile u8
*)probe_ent
->mmio_base
;
119 u32 tmp
, cap_save
, cmd
;
121 volatile u8
*port_mmio
;
124 debug("ahci_host_init: start\n");
126 cap_save
= readl(mmio
+ HOST_CAP
);
127 cap_save
&= ((1 << 28) | (1 << 17));
128 cap_save
|= (1 << 27); /* Staggered Spin-up. Not needed. */
130 /* global controller reset */
131 tmp
= readl(mmio
+ HOST_CTL
);
132 if ((tmp
& HOST_RESET
) == 0)
133 writel_with_flush(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
135 /* reset must complete within 1 second, or
136 * the hardware should be considered fried.
141 tmp
= readl(mmio
+ HOST_CTL
);
143 debug("controller reset failed (0x%x)\n", tmp
);
146 } while (tmp
& HOST_RESET
);
148 writel_with_flush(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
149 writel(cap_save
, mmio
+ HOST_CAP
);
150 writel_with_flush(0xf, mmio
+ HOST_PORTS_IMPL
);
152 #ifndef CONFIG_SCSI_AHCI_PLAT
153 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
155 if (vendor
== PCI_VENDOR_ID_INTEL
) {
157 pci_read_config_word(pdev
, 0x92, &tmp16
);
159 pci_write_config_word(pdev
, 0x92, tmp16
);
162 probe_ent
->cap
= readl(mmio
+ HOST_CAP
);
163 probe_ent
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
164 port_map
= probe_ent
->port_map
;
165 probe_ent
->n_ports
= (probe_ent
->cap
& 0x1f) + 1;
167 debug("cap 0x%x port_map 0x%x n_ports %d\n",
168 probe_ent
->cap
, probe_ent
->port_map
, probe_ent
->n_ports
);
170 if (probe_ent
->n_ports
> CONFIG_SYS_SCSI_MAX_SCSI_ID
)
171 probe_ent
->n_ports
= CONFIG_SYS_SCSI_MAX_SCSI_ID
;
173 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
174 if (!(port_map
& (1 << i
)))
176 probe_ent
->port
[i
].port_mmio
= ahci_port_base((u32
) mmio
, i
);
177 port_mmio
= (u8
*) probe_ent
->port
[i
].port_mmio
;
178 ahci_setup_port(&probe_ent
->port
[i
], (unsigned long)mmio
, i
);
180 /* make sure port is not active */
181 tmp
= readl(port_mmio
+ PORT_CMD
);
182 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
183 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
184 debug("Port %d is active. Deactivating.\n", i
);
185 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
186 PORT_CMD_FIS_RX
| PORT_CMD_START
);
187 writel_with_flush(tmp
, port_mmio
+ PORT_CMD
);
189 /* spec says 500 msecs for each bit, so
190 * this is slightly incorrect.
195 /* Add the spinup command to whatever mode bits may
196 * already be on in the command register.
198 cmd
= readl(port_mmio
+ PORT_CMD
);
199 cmd
|= PORT_CMD_FIS_RX
;
200 cmd
|= PORT_CMD_SPIN_UP
;
201 writel_with_flush(cmd
, port_mmio
+ PORT_CMD
);
203 /* Bring up SATA link.
204 * SATA link bringup time is usually less than 1 ms; only very
205 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
208 while (j
< WAIT_MS_LINKUP
) {
209 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
210 tmp
&= PORT_SCR_STAT_DET_MASK
;
211 if (tmp
== PORT_SCR_STAT_DET_PHYRDY
)
216 if (j
== WAIT_MS_LINKUP
) {
217 printf("SATA link %d timeout.\n", i
);
220 debug("SATA link ok.\n");
223 /* Clear error status */
224 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
226 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
228 debug("Spinning up device on SATA port %d... ", i
);
231 while (j
< WAIT_MS_SPINUP
) {
232 tmp
= readl(port_mmio
+ PORT_TFDATA
);
233 if (!(tmp
& (ATA_STAT_BUSY
| ATA_STAT_DRQ
)))
238 printf("Target spinup took %d ms.\n", j
);
239 if (j
== WAIT_MS_SPINUP
)
244 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
245 debug("PORT_SCR_ERR 0x%x\n", tmp
);
246 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
248 /* ack any pending irq events for this port */
249 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
250 debug("PORT_IRQ_STAT 0x%x\n", tmp
);
252 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
254 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
256 /* set irq mask (enables interrupts) */
257 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
259 /* register linkup ports */
260 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
261 debug("SATA port %d status: 0x%x\n", i
, tmp
);
262 if ((tmp
& PORT_SCR_STAT_DET_MASK
) == PORT_SCR_STAT_DET_PHYRDY
)
263 probe_ent
->link_port_map
|= (0x01 << i
);
266 tmp
= readl(mmio
+ HOST_CTL
);
267 debug("HOST_CTL 0x%x\n", tmp
);
268 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
269 tmp
= readl(mmio
+ HOST_CTL
);
270 debug("HOST_CTL 0x%x\n", tmp
);
271 #ifndef CONFIG_SCSI_AHCI_PLAT
272 pci_read_config_word(pdev
, PCI_COMMAND
, &tmp16
);
273 tmp
|= PCI_COMMAND_MASTER
;
274 pci_write_config_word(pdev
, PCI_COMMAND
, tmp16
);
280 static void ahci_print_info(struct ahci_probe_ent
*probe_ent
)
282 #ifndef CONFIG_SCSI_AHCI_PLAT
283 pci_dev_t pdev
= probe_ent
->dev
;
286 volatile u8
*mmio
= (volatile u8
*)probe_ent
->mmio_base
;
287 u32 vers
, cap
, cap2
, impl
, speed
;
291 vers
= readl(mmio
+ HOST_VERSION
);
292 cap
= probe_ent
->cap
;
293 cap2
= readl(mmio
+ HOST_CAP2
);
294 impl
= probe_ent
->port_map
;
296 speed
= (cap
>> 20) & 0xf;
306 #ifdef CONFIG_SCSI_AHCI_PLAT
309 pci_read_config_word(pdev
, 0x0a, &cc
);
312 else if (cc
== 0x0106)
314 else if (cc
== 0x0104)
319 printf("AHCI %02x%02x.%02x%02x "
320 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
325 ((cap
>> 8) & 0x1f) + 1, (cap
& 0x1f) + 1, speed_s
, impl
, scc_s
);
331 cap
& (1 << 31) ? "64bit " : "",
332 cap
& (1 << 30) ? "ncq " : "",
333 cap
& (1 << 28) ? "ilck " : "",
334 cap
& (1 << 27) ? "stag " : "",
335 cap
& (1 << 26) ? "pm " : "",
336 cap
& (1 << 25) ? "led " : "",
337 cap
& (1 << 24) ? "clo " : "",
338 cap
& (1 << 19) ? "nz " : "",
339 cap
& (1 << 18) ? "only " : "",
340 cap
& (1 << 17) ? "pmp " : "",
341 cap
& (1 << 16) ? "fbss " : "",
342 cap
& (1 << 15) ? "pio " : "",
343 cap
& (1 << 14) ? "slum " : "",
344 cap
& (1 << 13) ? "part " : "",
345 cap
& (1 << 7) ? "ccc " : "",
346 cap
& (1 << 6) ? "ems " : "",
347 cap
& (1 << 5) ? "sxs " : "",
348 cap2
& (1 << 2) ? "apst " : "",
349 cap2
& (1 << 1) ? "nvmp " : "",
350 cap2
& (1 << 0) ? "boh " : "");
353 #ifndef CONFIG_SCSI_AHCI_PLAT
354 static int ahci_init_one(pci_dev_t pdev
)
359 memset((void *)ataid
, 0, sizeof(hd_driveid_t
*) * AHCI_MAX_PORTS
);
361 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
362 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
363 probe_ent
->dev
= pdev
;
365 probe_ent
->host_flags
= ATA_FLAG_SATA
370 probe_ent
->pio_mask
= 0x1f;
371 probe_ent
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
373 pci_read_config_dword(pdev
, PCI_BASE_ADDRESS_5
, &probe_ent
->mmio_base
);
374 debug("ahci mmio_base=0x%08x\n", probe_ent
->mmio_base
);
377 * JMicron-specific fixup:
378 * make sure we're in AHCI mode
380 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
381 if (vendor
== 0x197b)
382 pci_write_config_byte(pdev
, 0x41, 0xa1);
384 /* initialize adapter */
385 rc
= ahci_host_init(probe_ent
);
389 ahci_print_info(probe_ent
);
398 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
400 static int ahci_fill_sg(u8 port
, unsigned char *buf
, int buf_len
)
402 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
403 struct ahci_sg
*ahci_sg
= pp
->cmd_tbl_sg
;
407 sg_count
= ((buf_len
- 1) / MAX_DATA_BYTE_COUNT
) + 1;
408 if (sg_count
> AHCI_MAX_SG
) {
409 printf("Error:Too much sg!\n");
413 for (i
= 0; i
< sg_count
; i
++) {
415 cpu_to_le32((u32
) buf
+ i
* MAX_DATA_BYTE_COUNT
);
416 ahci_sg
->addr_hi
= 0;
417 ahci_sg
->flags_size
= cpu_to_le32(0x3fffff &
418 (buf_len
< MAX_DATA_BYTE_COUNT
420 : (MAX_DATA_BYTE_COUNT
- 1)));
422 buf_len
-= MAX_DATA_BYTE_COUNT
;
429 static void ahci_fill_cmd_slot(struct ahci_ioports
*pp
, u32 opts
)
431 pp
->cmd_slot
->opts
= cpu_to_le32(opts
);
432 pp
->cmd_slot
->status
= 0;
433 pp
->cmd_slot
->tbl_addr
= cpu_to_le32(pp
->cmd_tbl
& 0xffffffff);
434 pp
->cmd_slot
->tbl_addr_hi
= 0;
438 #ifdef CONFIG_AHCI_SETFEATURES_XFER
439 static void ahci_set_feature(u8 port
)
441 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
442 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
443 u32 cmd_fis_len
= 5; /* five dwords */
447 memset(fis
, 0, sizeof(fis
));
450 fis
[2] = ATA_CMD_SETF
;
451 fis
[3] = SETFEATURES_XFER
;
452 fis
[12] = __ilog2(probe_ent
->udma_mask
+ 1) + 0x40 - 0x01;
454 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, sizeof(fis
));
455 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
456 ahci_dcache_flush_sata_cmd(pp
);
457 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
458 readl(port_mmio
+ PORT_CMD_ISSUE
);
460 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
461 WAIT_MS_DATAIO
, 0x1)) {
462 printf("set feature error on port %d!\n", port
);
468 static int ahci_port_start(u8 port
)
470 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
471 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
475 debug("Enter start port: %d\n", port
);
476 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
477 debug("Port %d status: %x\n", port
, port_status
);
478 if ((port_status
& 0xf) != 0x03) {
479 printf("No Link on this port!\n");
483 mem
= (u32
) malloc(AHCI_PORT_PRIV_DMA_SZ
+ 2048);
486 printf("No mem for table!\n");
490 mem
= (mem
+ 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
491 memset((u8
*) mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
494 * First item in chunk of DMA memory: 32-slot command table,
495 * 32 bytes each in size
498 (struct ahci_cmd_hdr
*)(uintptr_t)virt_to_phys((void *)mem
);
499 debug("cmd_slot = 0x%x\n", (unsigned)pp
->cmd_slot
);
500 mem
+= (AHCI_CMD_SLOT_SZ
+ 224);
503 * Second item: Received-FIS area
505 pp
->rx_fis
= virt_to_phys((void *)mem
);
506 mem
+= AHCI_RX_FIS_SZ
;
509 * Third item: data area for storing a single command
510 * and its scatter-gather table
512 pp
->cmd_tbl
= virt_to_phys((void *)mem
);
513 debug("cmd_tbl_dma = 0x%x\n", pp
->cmd_tbl
);
515 mem
+= AHCI_CMD_TBL_HDR
;
517 (struct ahci_sg
*)(uintptr_t)virt_to_phys((void *)mem
);
519 writel_with_flush((u32
) pp
->cmd_slot
, port_mmio
+ PORT_LST_ADDR
);
521 writel_with_flush(pp
->rx_fis
, port_mmio
+ PORT_FIS_ADDR
);
523 writel_with_flush(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
524 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
525 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
527 debug("Exit start port %d\n", port
);
533 static int ahci_device_data_io(u8 port
, u8
*fis
, int fis_len
, u8
*buf
,
534 int buf_len
, u8 is_write
)
537 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
538 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
543 debug("Enter %s: for port %d\n", __func__
, port
);
545 if (port
> probe_ent
->n_ports
) {
546 printf("Invalid port number %d\n", port
);
550 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
551 if ((port_status
& 0xf) != 0x03) {
552 debug("No Link on port %d!\n", port
);
556 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, fis_len
);
558 sg_count
= ahci_fill_sg(port
, buf
, buf_len
);
559 opts
= (fis_len
>> 2) | (sg_count
<< 16) | (is_write
<< 6);
560 ahci_fill_cmd_slot(pp
, opts
);
562 ahci_dcache_flush_sata_cmd(pp
);
563 ahci_dcache_flush_range((unsigned)buf
, (unsigned)buf_len
);
565 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
567 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
568 WAIT_MS_DATAIO
, 0x1)) {
569 printf("timeout exit!\n");
573 ahci_dcache_invalidate_range((unsigned)buf
, (unsigned)buf_len
);
574 debug("%s: %d byte transferred.\n", __func__
, pp
->cmd_slot
->status
);
580 static char *ata_id_strcpy(u16
*target
, u16
*src
, int len
)
583 for (i
= 0; i
< len
/ 2; i
++)
584 target
[i
] = swab16(src
[i
]);
585 return (char *)target
;
589 static void dump_ataid(hd_driveid_t
*ataid
)
591 debug("(49)ataid->capability = 0x%x\n", ataid
->capability
);
592 debug("(53)ataid->field_valid =0x%x\n", ataid
->field_valid
);
593 debug("(63)ataid->dma_mword = 0x%x\n", ataid
->dma_mword
);
594 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid
->eide_pio_modes
);
595 debug("(75)ataid->queue_depth = 0x%x\n", ataid
->queue_depth
);
596 debug("(80)ataid->major_rev_num = 0x%x\n", ataid
->major_rev_num
);
597 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid
->minor_rev_num
);
598 debug("(82)ataid->command_set_1 = 0x%x\n", ataid
->command_set_1
);
599 debug("(83)ataid->command_set_2 = 0x%x\n", ataid
->command_set_2
);
600 debug("(84)ataid->cfsse = 0x%x\n", ataid
->cfsse
);
601 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid
->cfs_enable_1
);
602 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid
->cfs_enable_2
);
603 debug("(87)ataid->csf_default = 0x%x\n", ataid
->csf_default
);
604 debug("(88)ataid->dma_ultra = 0x%x\n", ataid
->dma_ultra
);
605 debug("(93)ataid->hw_config = 0x%x\n", ataid
->hw_config
);
610 * SCSI INQUIRY command operation.
612 static int ata_scsiop_inquiry(ccb
*pccb
)
614 static const u8 hdr
[] = {
617 0x5, /* claim SPC-3 version compatibility */
625 /* Clean ccb data buffer */
626 memset(pccb
->pdata
, 0, pccb
->datalen
);
628 memcpy(pccb
->pdata
, hdr
, sizeof(hdr
));
630 if (pccb
->datalen
<= 35)
633 memset(fis
, 0, sizeof(fis
));
634 /* Construct the FIS */
635 fis
[0] = 0x27; /* Host to device FIS. */
636 fis
[1] = 1 << 7; /* Command FIS. */
637 fis
[2] = ATA_CMD_IDENT
; /* Command byte. */
639 /* Read id from sata */
641 if (!(tmpid
= malloc(sizeof(hd_driveid_t
))))
644 if (ahci_device_data_io(port
, (u8
*) &fis
, sizeof(fis
), tmpid
,
645 sizeof(hd_driveid_t
), 0)) {
646 debug("scsi_ahci: SCSI inquiry command failure.\n");
653 ataid
[port
] = (hd_driveid_t
*) tmpid
;
655 memcpy(&pccb
->pdata
[8], "ATA ", 8);
656 ata_id_strcpy((u16
*) &pccb
->pdata
[16], (u16
*)ataid
[port
]->model
, 16);
657 ata_id_strcpy((u16
*) &pccb
->pdata
[32], (u16
*)ataid
[port
]->fw_rev
, 4);
659 dump_ataid(ataid
[port
]);
665 * SCSI READ10/WRITE10 command operation.
667 static int ata_scsiop_read_write(ccb
*pccb
, u8 is_write
)
672 u8
*user_buffer
= pccb
->pdata
;
673 u32 user_buffer_size
= pccb
->datalen
;
675 /* Retrieve the base LBA number from the ccb structure. */
676 memcpy(&lba
, pccb
->cmd
+ 2, sizeof(lba
));
677 lba
= be32_to_cpu(lba
);
680 * And the number of blocks.
682 * For 10-byte and 16-byte SCSI R/W commands, transfer
683 * length 0 means transfer 0 block of data.
684 * However, for ATA R/W commands, sector count 0 means
685 * 256 or 65536 sectors, not 0 sectors as in SCSI.
687 * WARNING: one or two older ATA drives treat 0 as 0...
689 blocks
= (((u16
)pccb
->cmd
[7]) << 8) | ((u16
) pccb
->cmd
[8]);
691 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
692 is_write
? "write" : "read", (unsigned)lba
, blocks
);
695 memset(fis
, 0, sizeof(fis
));
696 fis
[0] = 0x27; /* Host to device FIS. */
697 fis
[1] = 1 << 7; /* Command FIS. */
698 /* Command byte (read/write). */
699 fis
[2] = is_write
? ATA_CMD_WRITE_EXT
: ATA_CMD_READ_EXT
;
702 u16 now_blocks
; /* number of blocks per iteration */
703 u32 transfer_size
; /* number of bytes per iteration */
705 now_blocks
= min(MAX_SATA_BLOCKS_READ_WRITE
, blocks
);
707 transfer_size
= ATA_BLOCKSIZE
* now_blocks
;
708 if (transfer_size
> user_buffer_size
) {
709 printf("scsi_ahci: Error: buffer too small.\n");
713 /* LBA48 SATA command but only use 32bit address range within
714 * that. The next smaller command range (28bit) is too small.
716 fis
[4] = (lba
>> 0) & 0xff;
717 fis
[5] = (lba
>> 8) & 0xff;
718 fis
[6] = (lba
>> 16) & 0xff;
719 fis
[7] = 1 << 6; /* device reg: set LBA mode */
720 fis
[8] = ((lba
>> 24) & 0xff);
721 fis
[3] = 0xe0; /* features */
723 /* Block (sector) count */
724 fis
[12] = (now_blocks
>> 0) & 0xff;
725 fis
[13] = (now_blocks
>> 8) & 0xff;
727 /* Read/Write from ahci */
728 if (ahci_device_data_io(pccb
->target
, (u8
*) &fis
, sizeof(fis
),
729 user_buffer
, user_buffer_size
,
731 debug("scsi_ahci: SCSI %s10 command failure.\n",
732 is_write
? "WRITE" : "READ");
736 /* If this transaction is a write, do a following flush.
737 * Writes in u-boot are so rare, and the logic to know when is
738 * the last write and do a flush only there is sufficiently
739 * difficult. Just do a flush after every write. This incurs,
740 * usually, one extra flush when the rare writes do happen.
743 if (-EIO
== ata_io_flush(pccb
->target
))
746 user_buffer
+= transfer_size
;
747 user_buffer_size
-= transfer_size
;
748 blocks
-= now_blocks
;
757 * SCSI READ CAPACITY10 command operation.
759 static int ata_scsiop_read_capacity10(ccb
*pccb
)
764 if (!ataid
[pccb
->target
]) {
765 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
767 "\tPlease run SCSI commmand INQUIRY firstly!\n");
771 cap
= le32_to_cpu(ataid
[pccb
->target
]->lba_capacity
);
772 if (cap
== 0xfffffff) {
773 unsigned short *cap48
= ataid
[pccb
->target
]->lba48_capacity
;
774 if (cap48
[2] || cap48
[3]) {
777 cap
= (le16_to_cpu(cap48
[1]) << 16) |
778 (le16_to_cpu(cap48
[0]));
782 cap
= cpu_to_be32(cap
);
783 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
785 block_size
= cpu_to_be32((u32
)512);
786 memcpy(&pccb
->pdata
[4], &block_size
, 4);
793 * SCSI READ CAPACITY16 command operation.
795 static int ata_scsiop_read_capacity16(ccb
*pccb
)
800 if (!ataid
[pccb
->target
]) {
801 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
803 "\tPlease run SCSI commmand INQUIRY firstly!\n");
807 cap
= le32_to_cpu(ataid
[pccb
->target
]->lba_capacity
);
808 if (cap
== 0xfffffff) {
809 memcpy(&cap
, ataid
[pccb
->target
]->lba48_capacity
, sizeof(cap
));
810 cap
= le64_to_cpu(cap
);
813 cap
= cpu_to_be64(cap
);
814 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
816 block_size
= cpu_to_be64((u64
)512);
817 memcpy(&pccb
->pdata
[8], &block_size
, 8);
824 * SCSI TEST UNIT READY command operation.
826 static int ata_scsiop_test_unit_ready(ccb
*pccb
)
828 return (ataid
[pccb
->target
]) ? 0 : -EPERM
;
832 int scsi_exec(ccb
*pccb
)
836 switch (pccb
->cmd
[0]) {
838 ret
= ata_scsiop_read_write(pccb
, 0);
841 ret
= ata_scsiop_read_write(pccb
, 1);
843 case SCSI_RD_CAPAC10
:
844 ret
= ata_scsiop_read_capacity10(pccb
);
846 case SCSI_RD_CAPAC16
:
847 ret
= ata_scsiop_read_capacity16(pccb
);
850 ret
= ata_scsiop_test_unit_ready(pccb
);
853 ret
= ata_scsiop_inquiry(pccb
);
856 printf("Unsupport SCSI command 0x%02x\n", pccb
->cmd
[0]);
861 debug("SCSI command 0x%02x ret errno %d\n", pccb
->cmd
[0], ret
);
869 void scsi_low_level_init(int busdevfunc
)
874 #ifndef CONFIG_SCSI_AHCI_PLAT
875 ahci_init_one(busdevfunc
);
878 linkmap
= probe_ent
->link_port_map
;
880 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
881 if (((linkmap
>> i
) & 0x01)) {
882 if (ahci_port_start((u8
) i
)) {
883 printf("Can not start port %d\n", i
);
886 #ifdef CONFIG_AHCI_SETFEATURES_XFER
887 ahci_set_feature((u8
) i
);
893 #ifdef CONFIG_SCSI_AHCI_PLAT
894 int ahci_init(u32 base
)
899 memset(ataid
, 0, sizeof(ataid
));
901 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
902 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
904 probe_ent
->host_flags
= ATA_FLAG_SATA
909 probe_ent
->pio_mask
= 0x1f;
910 probe_ent
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
912 probe_ent
->mmio_base
= base
;
914 /* initialize adapter */
915 rc
= ahci_host_init(probe_ent
);
919 ahci_print_info(probe_ent
);
921 linkmap
= probe_ent
->link_port_map
;
923 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
924 if (((linkmap
>> i
) & 0x01)) {
925 if (ahci_port_start((u8
) i
)) {
926 printf("Can not start port %d\n", i
);
929 #ifdef CONFIG_AHCI_SETFEATURES_XFER
930 ahci_set_feature((u8
) i
);
940 * In the general case of generic rotating media it makes sense to have a
941 * flush capability. It probably even makes sense in the case of SSDs because
942 * one cannot always know for sure what kind of internal cache/flush mechanism
943 * is embodied therein. At first it was planned to invoke this after the last
944 * write to disk and before rebooting. In practice, knowing, a priori, which
945 * is the last write is difficult. Because writing to the disk in u-boot is
946 * very rare, this flush command will be invoked after every block write.
948 static int ata_io_flush(u8 port
)
951 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
952 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
953 u32 cmd_fis_len
= 5; /* five dwords */
957 fis
[0] = 0x27; /* Host to device FIS. */
958 fis
[1] = 1 << 7; /* Command FIS. */
959 fis
[2] = ATA_CMD_FLUSH_EXT
;
961 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, 20);
962 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
963 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
965 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
966 WAIT_MS_FLUSH
, 0x1)) {
967 debug("scsi_ahci: flush command timeout on port %d.\n", port
);
975 void scsi_bus_reset(void)
981 void scsi_print_error(ccb
* pccb
)
983 /*The ahci error info can be read in the ahci driver*/