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ahci: provide sunxi SATA driver using AHCI platform framework
[people/ms/u-boot.git] / drivers / block / ahci.c
1 /*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * with the reference on libata and ahci drvier in kernel
9 */
10 #include <common.h>
11
12 #include <command.h>
13 #include <pci.h>
14 #include <asm/processor.h>
15 #include <asm/errno.h>
16 #include <asm/io.h>
17 #include <malloc.h>
18 #include <scsi.h>
19 #include <libata.h>
20 #include <linux/ctype.h>
21 #include <ahci.h>
22
23 static int ata_io_flush(u8 port);
24
25 struct ahci_probe_ent *probe_ent = NULL;
26 u16 *ataid[AHCI_MAX_PORTS];
27
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
29
30 /*
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
34 * needed.
35 */
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
38 #endif
39
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 20000
42 #define WAIT_MS_DATAIO 5000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 200
45
46 static inline u32 ahci_port_base(u32 base, u32 port)
47 {
48 return base + 0x100 + (port * 0x80);
49 }
50
51
52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx)
54 {
55 base = ahci_port_base(base, port_idx);
56
57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
59 }
60
61
62 #define msleep(a) udelay(a * 1000)
63
64 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
65 {
66 const unsigned long start = begin;
67 const unsigned long end = start + len;
68
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end);
71 }
72
73 /*
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
76 * physical RAM.
77 */
78 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
79 {
80 const unsigned long start = begin;
81 const unsigned long end = start + len;
82
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end);
85 }
86
87 /*
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
90 */
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
92 {
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ);
95 }
96
97 static int waiting_for_cmd_completed(volatile u8 *offset,
98 int timeout_msec,
99 u32 sign)
100 {
101 int i;
102 u32 status;
103
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
105 msleep(1);
106
107 return (i < timeout_msec) ? 0 : -1;
108 }
109
110 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
111 {
112 u32 tmp;
113 int j = 0;
114 u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
115
116 /*
117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
120 */
121 while (j < WAIT_MS_LINKUP) {
122 tmp = readl(port_mmio + PORT_SCR_STAT);
123 tmp &= PORT_SCR_STAT_DET_MASK;
124 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
125 return 0;
126 udelay(1000);
127 j++;
128 }
129 return 1;
130 }
131
132 #ifdef CONFIG_SUNXI_AHCI
133 /* The sunxi AHCI controller requires this undocumented setup */
134 static void sunxi_dma_init(volatile u8 *port_mmio)
135 {
136 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
137 }
138 #endif
139
140 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
141 {
142 #ifndef CONFIG_SCSI_AHCI_PLAT
143 pci_dev_t pdev = probe_ent->dev;
144 u16 tmp16;
145 unsigned short vendor;
146 #endif
147 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
148 u32 tmp, cap_save, cmd;
149 int i, j, ret;
150 volatile u8 *port_mmio;
151 u32 port_map;
152
153 debug("ahci_host_init: start\n");
154
155 cap_save = readl(mmio + HOST_CAP);
156 cap_save &= ((1 << 28) | (1 << 17));
157 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
158
159 /* global controller reset */
160 tmp = readl(mmio + HOST_CTL);
161 if ((tmp & HOST_RESET) == 0)
162 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
163
164 /* reset must complete within 1 second, or
165 * the hardware should be considered fried.
166 */
167 i = 1000;
168 do {
169 udelay(1000);
170 tmp = readl(mmio + HOST_CTL);
171 if (!i--) {
172 debug("controller reset failed (0x%x)\n", tmp);
173 return -1;
174 }
175 } while (tmp & HOST_RESET);
176
177 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
178 writel(cap_save, mmio + HOST_CAP);
179 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
180
181 #ifndef CONFIG_SCSI_AHCI_PLAT
182 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
183
184 if (vendor == PCI_VENDOR_ID_INTEL) {
185 u16 tmp16;
186 pci_read_config_word(pdev, 0x92, &tmp16);
187 tmp16 |= 0xf;
188 pci_write_config_word(pdev, 0x92, tmp16);
189 }
190 #endif
191 probe_ent->cap = readl(mmio + HOST_CAP);
192 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
193 port_map = probe_ent->port_map;
194 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
195
196 debug("cap 0x%x port_map 0x%x n_ports %d\n",
197 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
198
199 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
200 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
201
202 for (i = 0; i < probe_ent->n_ports; i++) {
203 if (!(port_map & (1 << i)))
204 continue;
205 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
206 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
207 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
208
209 /* make sure port is not active */
210 tmp = readl(port_mmio + PORT_CMD);
211 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
212 PORT_CMD_FIS_RX | PORT_CMD_START)) {
213 debug("Port %d is active. Deactivating.\n", i);
214 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
215 PORT_CMD_FIS_RX | PORT_CMD_START);
216 writel_with_flush(tmp, port_mmio + PORT_CMD);
217
218 /* spec says 500 msecs for each bit, so
219 * this is slightly incorrect.
220 */
221 msleep(500);
222 }
223
224 #ifdef CONFIG_SUNXI_AHCI
225 sunxi_dma_init(port_mmio);
226 #endif
227
228 /* Add the spinup command to whatever mode bits may
229 * already be on in the command register.
230 */
231 cmd = readl(port_mmio + PORT_CMD);
232 cmd |= PORT_CMD_FIS_RX;
233 cmd |= PORT_CMD_SPIN_UP;
234 writel_with_flush(cmd, port_mmio + PORT_CMD);
235
236 /* Bring up SATA link. */
237 ret = ahci_link_up(probe_ent, i);
238 if (ret) {
239 printf("SATA link %d timeout.\n", i);
240 continue;
241 } else {
242 debug("SATA link ok.\n");
243 }
244
245 /* Clear error status */
246 tmp = readl(port_mmio + PORT_SCR_ERR);
247 if (tmp)
248 writel(tmp, port_mmio + PORT_SCR_ERR);
249
250 debug("Spinning up device on SATA port %d... ", i);
251
252 j = 0;
253 while (j < WAIT_MS_SPINUP) {
254 tmp = readl(port_mmio + PORT_TFDATA);
255 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
256 break;
257 udelay(1000);
258 tmp = readl(port_mmio + PORT_SCR_STAT);
259 tmp &= PORT_SCR_STAT_DET_MASK;
260 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
261 break;
262 j++;
263 }
264
265 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
266 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
267 debug("SATA link %d down (COMINIT received), retrying...\n", i);
268 i--;
269 continue;
270 }
271
272 printf("Target spinup took %d ms.\n", j);
273 if (j == WAIT_MS_SPINUP)
274 debug("timeout.\n");
275 else
276 debug("ok.\n");
277
278 tmp = readl(port_mmio + PORT_SCR_ERR);
279 debug("PORT_SCR_ERR 0x%x\n", tmp);
280 writel(tmp, port_mmio + PORT_SCR_ERR);
281
282 /* ack any pending irq events for this port */
283 tmp = readl(port_mmio + PORT_IRQ_STAT);
284 debug("PORT_IRQ_STAT 0x%x\n", tmp);
285 if (tmp)
286 writel(tmp, port_mmio + PORT_IRQ_STAT);
287
288 writel(1 << i, mmio + HOST_IRQ_STAT);
289
290 /* set irq mask (enables interrupts) */
291 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
292
293 /* register linkup ports */
294 tmp = readl(port_mmio + PORT_SCR_STAT);
295 debug("SATA port %d status: 0x%x\n", i, tmp);
296 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
297 probe_ent->link_port_map |= (0x01 << i);
298 }
299
300 tmp = readl(mmio + HOST_CTL);
301 debug("HOST_CTL 0x%x\n", tmp);
302 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
303 tmp = readl(mmio + HOST_CTL);
304 debug("HOST_CTL 0x%x\n", tmp);
305 #ifndef CONFIG_SCSI_AHCI_PLAT
306 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
307 tmp |= PCI_COMMAND_MASTER;
308 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
309 #endif
310 return 0;
311 }
312
313
314 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
315 {
316 #ifndef CONFIG_SCSI_AHCI_PLAT
317 pci_dev_t pdev = probe_ent->dev;
318 u16 cc;
319 #endif
320 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
321 u32 vers, cap, cap2, impl, speed;
322 const char *speed_s;
323 const char *scc_s;
324
325 vers = readl(mmio + HOST_VERSION);
326 cap = probe_ent->cap;
327 cap2 = readl(mmio + HOST_CAP2);
328 impl = probe_ent->port_map;
329
330 speed = (cap >> 20) & 0xf;
331 if (speed == 1)
332 speed_s = "1.5";
333 else if (speed == 2)
334 speed_s = "3";
335 else if (speed == 3)
336 speed_s = "6";
337 else
338 speed_s = "?";
339
340 #ifdef CONFIG_SCSI_AHCI_PLAT
341 scc_s = "SATA";
342 #else
343 pci_read_config_word(pdev, 0x0a, &cc);
344 if (cc == 0x0101)
345 scc_s = "IDE";
346 else if (cc == 0x0106)
347 scc_s = "SATA";
348 else if (cc == 0x0104)
349 scc_s = "RAID";
350 else
351 scc_s = "unknown";
352 #endif
353 printf("AHCI %02x%02x.%02x%02x "
354 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
355 (vers >> 24) & 0xff,
356 (vers >> 16) & 0xff,
357 (vers >> 8) & 0xff,
358 vers & 0xff,
359 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
360
361 printf("flags: "
362 "%s%s%s%s%s%s%s"
363 "%s%s%s%s%s%s%s"
364 "%s%s%s%s%s%s\n",
365 cap & (1 << 31) ? "64bit " : "",
366 cap & (1 << 30) ? "ncq " : "",
367 cap & (1 << 28) ? "ilck " : "",
368 cap & (1 << 27) ? "stag " : "",
369 cap & (1 << 26) ? "pm " : "",
370 cap & (1 << 25) ? "led " : "",
371 cap & (1 << 24) ? "clo " : "",
372 cap & (1 << 19) ? "nz " : "",
373 cap & (1 << 18) ? "only " : "",
374 cap & (1 << 17) ? "pmp " : "",
375 cap & (1 << 16) ? "fbss " : "",
376 cap & (1 << 15) ? "pio " : "",
377 cap & (1 << 14) ? "slum " : "",
378 cap & (1 << 13) ? "part " : "",
379 cap & (1 << 7) ? "ccc " : "",
380 cap & (1 << 6) ? "ems " : "",
381 cap & (1 << 5) ? "sxs " : "",
382 cap2 & (1 << 2) ? "apst " : "",
383 cap2 & (1 << 1) ? "nvmp " : "",
384 cap2 & (1 << 0) ? "boh " : "");
385 }
386
387 #ifndef CONFIG_SCSI_AHCI_PLAT
388 static int ahci_init_one(pci_dev_t pdev)
389 {
390 u16 vendor;
391 int rc;
392
393 probe_ent = malloc(sizeof(struct ahci_probe_ent));
394 if (!probe_ent) {
395 printf("%s: No memory for probe_ent\n", __func__);
396 return -ENOMEM;
397 }
398
399 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
400 probe_ent->dev = pdev;
401
402 probe_ent->host_flags = ATA_FLAG_SATA
403 | ATA_FLAG_NO_LEGACY
404 | ATA_FLAG_MMIO
405 | ATA_FLAG_PIO_DMA
406 | ATA_FLAG_NO_ATAPI;
407 probe_ent->pio_mask = 0x1f;
408 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
409
410 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
411 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
412
413 /* Take from kernel:
414 * JMicron-specific fixup:
415 * make sure we're in AHCI mode
416 */
417 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
418 if (vendor == 0x197b)
419 pci_write_config_byte(pdev, 0x41, 0xa1);
420
421 /* initialize adapter */
422 rc = ahci_host_init(probe_ent);
423 if (rc)
424 goto err_out;
425
426 ahci_print_info(probe_ent);
427
428 return 0;
429
430 err_out:
431 return rc;
432 }
433 #endif
434
435 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
436
437 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
438 {
439 struct ahci_ioports *pp = &(probe_ent->port[port]);
440 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
441 u32 sg_count;
442 int i;
443
444 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
445 if (sg_count > AHCI_MAX_SG) {
446 printf("Error:Too much sg!\n");
447 return -1;
448 }
449
450 for (i = 0; i < sg_count; i++) {
451 ahci_sg->addr =
452 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
453 ahci_sg->addr_hi = 0;
454 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
455 (buf_len < MAX_DATA_BYTE_COUNT
456 ? (buf_len - 1)
457 : (MAX_DATA_BYTE_COUNT - 1)));
458 ahci_sg++;
459 buf_len -= MAX_DATA_BYTE_COUNT;
460 }
461
462 return sg_count;
463 }
464
465
466 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
467 {
468 pp->cmd_slot->opts = cpu_to_le32(opts);
469 pp->cmd_slot->status = 0;
470 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
471 pp->cmd_slot->tbl_addr_hi = 0;
472 }
473
474
475 #ifdef CONFIG_AHCI_SETFEATURES_XFER
476 static void ahci_set_feature(u8 port)
477 {
478 struct ahci_ioports *pp = &(probe_ent->port[port]);
479 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
480 u32 cmd_fis_len = 5; /* five dwords */
481 u8 fis[20];
482
483 /* set feature */
484 memset(fis, 0, sizeof(fis));
485 fis[0] = 0x27;
486 fis[1] = 1 << 7;
487 fis[2] = ATA_CMD_SET_FEATURES;
488 fis[3] = SETFEATURES_XFER;
489 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
490
491 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
492 ahci_fill_cmd_slot(pp, cmd_fis_len);
493 ahci_dcache_flush_sata_cmd(pp);
494 writel(1, port_mmio + PORT_CMD_ISSUE);
495 readl(port_mmio + PORT_CMD_ISSUE);
496
497 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
498 WAIT_MS_DATAIO, 0x1)) {
499 printf("set feature error on port %d!\n", port);
500 }
501 }
502 #endif
503
504
505 static int ahci_port_start(u8 port)
506 {
507 struct ahci_ioports *pp = &(probe_ent->port[port]);
508 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
509 u32 port_status;
510 u32 mem;
511
512 debug("Enter start port: %d\n", port);
513 port_status = readl(port_mmio + PORT_SCR_STAT);
514 debug("Port %d status: %x\n", port, port_status);
515 if ((port_status & 0xf) != 0x03) {
516 printf("No Link on this port!\n");
517 return -1;
518 }
519
520 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
521 if (!mem) {
522 free(pp);
523 printf("%s: No mem for table!\n", __func__);
524 return -ENOMEM;
525 }
526
527 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
528 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
529
530 /*
531 * First item in chunk of DMA memory: 32-slot command table,
532 * 32 bytes each in size
533 */
534 pp->cmd_slot =
535 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
536 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
537 mem += (AHCI_CMD_SLOT_SZ + 224);
538
539 /*
540 * Second item: Received-FIS area
541 */
542 pp->rx_fis = virt_to_phys((void *)mem);
543 mem += AHCI_RX_FIS_SZ;
544
545 /*
546 * Third item: data area for storing a single command
547 * and its scatter-gather table
548 */
549 pp->cmd_tbl = virt_to_phys((void *)mem);
550 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
551
552 mem += AHCI_CMD_TBL_HDR;
553 pp->cmd_tbl_sg =
554 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
555
556 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
557
558 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
559
560 #ifdef CONFIG_SUNXI_AHCI
561 sunxi_dma_init(port_mmio);
562 #endif
563
564 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
565 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
566 PORT_CMD_START, port_mmio + PORT_CMD);
567
568 debug("Exit start port %d\n", port);
569
570 return 0;
571 }
572
573
574 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
575 int buf_len, u8 is_write)
576 {
577
578 struct ahci_ioports *pp = &(probe_ent->port[port]);
579 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
580 u32 opts;
581 u32 port_status;
582 int sg_count;
583
584 debug("Enter %s: for port %d\n", __func__, port);
585
586 if (port > probe_ent->n_ports) {
587 printf("Invalid port number %d\n", port);
588 return -1;
589 }
590
591 port_status = readl(port_mmio + PORT_SCR_STAT);
592 if ((port_status & 0xf) != 0x03) {
593 debug("No Link on port %d!\n", port);
594 return -1;
595 }
596
597 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
598
599 sg_count = ahci_fill_sg(port, buf, buf_len);
600 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
601 ahci_fill_cmd_slot(pp, opts);
602
603 ahci_dcache_flush_sata_cmd(pp);
604 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
605
606 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
607
608 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
609 WAIT_MS_DATAIO, 0x1)) {
610 printf("timeout exit!\n");
611 return -1;
612 }
613
614 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
615 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
616
617 return 0;
618 }
619
620
621 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
622 {
623 int i;
624 for (i = 0; i < len / 2; i++)
625 target[i] = swab16(src[i]);
626 return (char *)target;
627 }
628
629 /*
630 * SCSI INQUIRY command operation.
631 */
632 static int ata_scsiop_inquiry(ccb *pccb)
633 {
634 static const u8 hdr[] = {
635 0,
636 0,
637 0x5, /* claim SPC-3 version compatibility */
638 2,
639 95 - 4,
640 };
641 u8 fis[20];
642 u16 *idbuf;
643 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
644 u8 port;
645
646 /* Clean ccb data buffer */
647 memset(pccb->pdata, 0, pccb->datalen);
648
649 memcpy(pccb->pdata, hdr, sizeof(hdr));
650
651 if (pccb->datalen <= 35)
652 return 0;
653
654 memset(fis, 0, sizeof(fis));
655 /* Construct the FIS */
656 fis[0] = 0x27; /* Host to device FIS. */
657 fis[1] = 1 << 7; /* Command FIS. */
658 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
659
660 /* Read id from sata */
661 port = pccb->target;
662
663 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
664 ATA_ID_WORDS * 2, 0)) {
665 debug("scsi_ahci: SCSI inquiry command failure.\n");
666 return -EIO;
667 }
668
669 if (!ataid[port]) {
670 ataid[port] = malloc(ATA_ID_WORDS * 2);
671 if (!ataid[port]) {
672 printf("%s: No memory for ataid[port]\n", __func__);
673 return -ENOMEM;
674 }
675 }
676
677 idbuf = ataid[port];
678
679 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
680 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
681
682 memcpy(&pccb->pdata[8], "ATA ", 8);
683 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
684 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
685
686 #ifdef DEBUG
687 ata_dump_id(idbuf);
688 #endif
689 return 0;
690 }
691
692
693 /*
694 * SCSI READ10/WRITE10 command operation.
695 */
696 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
697 {
698 u32 lba = 0;
699 u16 blocks = 0;
700 u8 fis[20];
701 u8 *user_buffer = pccb->pdata;
702 u32 user_buffer_size = pccb->datalen;
703
704 /* Retrieve the base LBA number from the ccb structure. */
705 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
706 lba = be32_to_cpu(lba);
707
708 /*
709 * And the number of blocks.
710 *
711 * For 10-byte and 16-byte SCSI R/W commands, transfer
712 * length 0 means transfer 0 block of data.
713 * However, for ATA R/W commands, sector count 0 means
714 * 256 or 65536 sectors, not 0 sectors as in SCSI.
715 *
716 * WARNING: one or two older ATA drives treat 0 as 0...
717 */
718 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
719
720 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
721 is_write ? "write" : "read", (unsigned)lba, blocks);
722
723 /* Preset the FIS */
724 memset(fis, 0, sizeof(fis));
725 fis[0] = 0x27; /* Host to device FIS. */
726 fis[1] = 1 << 7; /* Command FIS. */
727 /* Command byte (read/write). */
728 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
729
730 while (blocks) {
731 u16 now_blocks; /* number of blocks per iteration */
732 u32 transfer_size; /* number of bytes per iteration */
733
734 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
735
736 transfer_size = ATA_SECT_SIZE * now_blocks;
737 if (transfer_size > user_buffer_size) {
738 printf("scsi_ahci: Error: buffer too small.\n");
739 return -EIO;
740 }
741
742 /* LBA48 SATA command but only use 32bit address range within
743 * that. The next smaller command range (28bit) is too small.
744 */
745 fis[4] = (lba >> 0) & 0xff;
746 fis[5] = (lba >> 8) & 0xff;
747 fis[6] = (lba >> 16) & 0xff;
748 fis[7] = 1 << 6; /* device reg: set LBA mode */
749 fis[8] = ((lba >> 24) & 0xff);
750 fis[3] = 0xe0; /* features */
751
752 /* Block (sector) count */
753 fis[12] = (now_blocks >> 0) & 0xff;
754 fis[13] = (now_blocks >> 8) & 0xff;
755
756 /* Read/Write from ahci */
757 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
758 user_buffer, user_buffer_size,
759 is_write)) {
760 debug("scsi_ahci: SCSI %s10 command failure.\n",
761 is_write ? "WRITE" : "READ");
762 return -EIO;
763 }
764
765 /* If this transaction is a write, do a following flush.
766 * Writes in u-boot are so rare, and the logic to know when is
767 * the last write and do a flush only there is sufficiently
768 * difficult. Just do a flush after every write. This incurs,
769 * usually, one extra flush when the rare writes do happen.
770 */
771 if (is_write) {
772 if (-EIO == ata_io_flush(pccb->target))
773 return -EIO;
774 }
775 user_buffer += transfer_size;
776 user_buffer_size -= transfer_size;
777 blocks -= now_blocks;
778 lba += now_blocks;
779 }
780
781 return 0;
782 }
783
784
785 /*
786 * SCSI READ CAPACITY10 command operation.
787 */
788 static int ata_scsiop_read_capacity10(ccb *pccb)
789 {
790 u32 cap;
791 u64 cap64;
792 u32 block_size;
793
794 if (!ataid[pccb->target]) {
795 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
796 "\tNo ATA info!\n"
797 "\tPlease run SCSI commmand INQUIRY firstly!\n");
798 return -EPERM;
799 }
800
801 cap64 = ata_id_n_sectors(ataid[pccb->target]);
802 if (cap64 > 0x100000000ULL)
803 cap64 = 0xffffffff;
804
805 cap = cpu_to_be32(cap64);
806 memcpy(pccb->pdata, &cap, sizeof(cap));
807
808 block_size = cpu_to_be32((u32)512);
809 memcpy(&pccb->pdata[4], &block_size, 4);
810
811 return 0;
812 }
813
814
815 /*
816 * SCSI READ CAPACITY16 command operation.
817 */
818 static int ata_scsiop_read_capacity16(ccb *pccb)
819 {
820 u64 cap;
821 u64 block_size;
822
823 if (!ataid[pccb->target]) {
824 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
825 "\tNo ATA info!\n"
826 "\tPlease run SCSI commmand INQUIRY firstly!\n");
827 return -EPERM;
828 }
829
830 cap = ata_id_n_sectors(ataid[pccb->target]);
831 cap = cpu_to_be64(cap);
832 memcpy(pccb->pdata, &cap, sizeof(cap));
833
834 block_size = cpu_to_be64((u64)512);
835 memcpy(&pccb->pdata[8], &block_size, 8);
836
837 return 0;
838 }
839
840
841 /*
842 * SCSI TEST UNIT READY command operation.
843 */
844 static int ata_scsiop_test_unit_ready(ccb *pccb)
845 {
846 return (ataid[pccb->target]) ? 0 : -EPERM;
847 }
848
849
850 int scsi_exec(ccb *pccb)
851 {
852 int ret;
853
854 switch (pccb->cmd[0]) {
855 case SCSI_READ10:
856 ret = ata_scsiop_read_write(pccb, 0);
857 break;
858 case SCSI_WRITE10:
859 ret = ata_scsiop_read_write(pccb, 1);
860 break;
861 case SCSI_RD_CAPAC10:
862 ret = ata_scsiop_read_capacity10(pccb);
863 break;
864 case SCSI_RD_CAPAC16:
865 ret = ata_scsiop_read_capacity16(pccb);
866 break;
867 case SCSI_TST_U_RDY:
868 ret = ata_scsiop_test_unit_ready(pccb);
869 break;
870 case SCSI_INQUIRY:
871 ret = ata_scsiop_inquiry(pccb);
872 break;
873 default:
874 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
875 return false;
876 }
877
878 if (ret) {
879 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
880 return false;
881 }
882 return true;
883
884 }
885
886
887 void scsi_low_level_init(int busdevfunc)
888 {
889 int i;
890 u32 linkmap;
891
892 #ifndef CONFIG_SCSI_AHCI_PLAT
893 ahci_init_one(busdevfunc);
894 #endif
895
896 linkmap = probe_ent->link_port_map;
897
898 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
899 if (((linkmap >> i) & 0x01)) {
900 if (ahci_port_start((u8) i)) {
901 printf("Can not start port %d\n", i);
902 continue;
903 }
904 #ifdef CONFIG_AHCI_SETFEATURES_XFER
905 ahci_set_feature((u8) i);
906 #endif
907 }
908 }
909 }
910
911 #ifdef CONFIG_SCSI_AHCI_PLAT
912 int ahci_init(u32 base)
913 {
914 int i, rc = 0;
915 u32 linkmap;
916
917 probe_ent = malloc(sizeof(struct ahci_probe_ent));
918 if (!probe_ent) {
919 printf("%s: No memory for probe_ent\n", __func__);
920 return -ENOMEM;
921 }
922
923 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
924
925 probe_ent->host_flags = ATA_FLAG_SATA
926 | ATA_FLAG_NO_LEGACY
927 | ATA_FLAG_MMIO
928 | ATA_FLAG_PIO_DMA
929 | ATA_FLAG_NO_ATAPI;
930 probe_ent->pio_mask = 0x1f;
931 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
932
933 probe_ent->mmio_base = base;
934
935 /* initialize adapter */
936 rc = ahci_host_init(probe_ent);
937 if (rc)
938 goto err_out;
939
940 ahci_print_info(probe_ent);
941
942 linkmap = probe_ent->link_port_map;
943
944 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
945 if (((linkmap >> i) & 0x01)) {
946 if (ahci_port_start((u8) i)) {
947 printf("Can not start port %d\n", i);
948 continue;
949 }
950 #ifdef CONFIG_AHCI_SETFEATURES_XFER
951 ahci_set_feature((u8) i);
952 #endif
953 }
954 }
955 err_out:
956 return rc;
957 }
958
959 void __weak scsi_init(void)
960 {
961 }
962
963 #endif
964
965 /*
966 * In the general case of generic rotating media it makes sense to have a
967 * flush capability. It probably even makes sense in the case of SSDs because
968 * one cannot always know for sure what kind of internal cache/flush mechanism
969 * is embodied therein. At first it was planned to invoke this after the last
970 * write to disk and before rebooting. In practice, knowing, a priori, which
971 * is the last write is difficult. Because writing to the disk in u-boot is
972 * very rare, this flush command will be invoked after every block write.
973 */
974 static int ata_io_flush(u8 port)
975 {
976 u8 fis[20];
977 struct ahci_ioports *pp = &(probe_ent->port[port]);
978 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
979 u32 cmd_fis_len = 5; /* five dwords */
980
981 /* Preset the FIS */
982 memset(fis, 0, 20);
983 fis[0] = 0x27; /* Host to device FIS. */
984 fis[1] = 1 << 7; /* Command FIS. */
985 fis[2] = ATA_CMD_FLUSH_EXT;
986
987 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
988 ahci_fill_cmd_slot(pp, cmd_fis_len);
989 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
990
991 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
992 WAIT_MS_FLUSH, 0x1)) {
993 debug("scsi_ahci: flush command timeout on port %d.\n", port);
994 return -EIO;
995 }
996
997 return 0;
998 }
999
1000
1001 void scsi_bus_reset(void)
1002 {
1003 /*Not implement*/
1004 }
1005
1006
1007 void scsi_print_error(ccb * pccb)
1008 {
1009 /*The ahci error info can be read in the ahci driver*/
1010 }
"Das U-Boot" Source Tree