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Merge branch 'master' of git://git.denx.de/u-boot-blackfin
[people/ms/u-boot.git] / drivers / block / ahci.c
1 /*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * with the reference on libata and ahci drvier in kernel
9 */
10 #include <common.h>
11
12 #include <command.h>
13 #include <pci.h>
14 #include <asm/processor.h>
15 #include <asm/errno.h>
16 #include <asm/io.h>
17 #include <malloc.h>
18 #include <scsi.h>
19 #include <libata.h>
20 #include <linux/ctype.h>
21 #include <ahci.h>
22
23 static int ata_io_flush(u8 port);
24
25 struct ahci_probe_ent *probe_ent = NULL;
26 u16 *ataid[AHCI_MAX_PORTS];
27
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
29
30 /*
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
34 * needed.
35 */
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
38 #endif
39
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 20000
42 #define WAIT_MS_DATAIO 5000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 200
45
46 static inline u32 ahci_port_base(u32 base, u32 port)
47 {
48 return base + 0x100 + (port * 0x80);
49 }
50
51
52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx)
54 {
55 base = ahci_port_base(base, port_idx);
56
57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
59 }
60
61
62 #define msleep(a) udelay(a * 1000)
63
64 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
65 {
66 const unsigned long start = begin;
67 const unsigned long end = start + len;
68
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end);
71 }
72
73 /*
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
76 * physical RAM.
77 */
78 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
79 {
80 const unsigned long start = begin;
81 const unsigned long end = start + len;
82
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end);
85 }
86
87 /*
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
90 */
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
92 {
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ);
95 }
96
97 static int waiting_for_cmd_completed(volatile u8 *offset,
98 int timeout_msec,
99 u32 sign)
100 {
101 int i;
102 u32 status;
103
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
105 msleep(1);
106
107 return (i < timeout_msec) ? 0 : -1;
108 }
109
110 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
111 {
112 u32 tmp;
113 int j = 0;
114 u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
115
116 /*
117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
120 */
121 while (j < WAIT_MS_LINKUP) {
122 tmp = readl(port_mmio + PORT_SCR_STAT);
123 tmp &= PORT_SCR_STAT_DET_MASK;
124 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
125 return 0;
126 udelay(1000);
127 j++;
128 }
129 return 1;
130 }
131
132 #ifdef CONFIG_SUNXI_AHCI
133 /* The sunxi AHCI controller requires this undocumented setup */
134 static void sunxi_dma_init(volatile u8 *port_mmio)
135 {
136 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
137 }
138 #endif
139
140 int ahci_reset(u32 base)
141 {
142 int i = 1000;
143 u32 host_ctl_reg = base + HOST_CTL;
144 u32 tmp = readl(host_ctl_reg); /* global controller reset */
145
146 if ((tmp & HOST_RESET) == 0)
147 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
148
149 /*
150 * reset must complete within 1 second, or
151 * the hardware should be considered fried.
152 */
153 do {
154 udelay(1000);
155 tmp = readl(host_ctl_reg);
156 i--;
157 } while ((i > 0) && (tmp & HOST_RESET));
158
159 if (i == 0) {
160 printf("controller reset failed (0x%x)\n", tmp);
161 return -1;
162 }
163
164 return 0;
165 }
166
167 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
168 {
169 #ifndef CONFIG_SCSI_AHCI_PLAT
170 pci_dev_t pdev = probe_ent->dev;
171 u16 tmp16;
172 unsigned short vendor;
173 #endif
174 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
175 u32 tmp, cap_save, cmd;
176 int i, j, ret;
177 volatile u8 *port_mmio;
178 u32 port_map;
179
180 debug("ahci_host_init: start\n");
181
182 cap_save = readl(mmio + HOST_CAP);
183 cap_save &= ((1 << 28) | (1 << 17));
184 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
185
186 ret = ahci_reset(probe_ent->mmio_base);
187 if (ret)
188 return ret;
189
190 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
191 writel(cap_save, mmio + HOST_CAP);
192 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
193
194 #ifndef CONFIG_SCSI_AHCI_PLAT
195 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
196
197 if (vendor == PCI_VENDOR_ID_INTEL) {
198 u16 tmp16;
199 pci_read_config_word(pdev, 0x92, &tmp16);
200 tmp16 |= 0xf;
201 pci_write_config_word(pdev, 0x92, tmp16);
202 }
203 #endif
204 probe_ent->cap = readl(mmio + HOST_CAP);
205 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
206 port_map = probe_ent->port_map;
207 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
208
209 debug("cap 0x%x port_map 0x%x n_ports %d\n",
210 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
211
212 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
213 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
214
215 for (i = 0; i < probe_ent->n_ports; i++) {
216 if (!(port_map & (1 << i)))
217 continue;
218 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
219 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
220 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
221
222 /* make sure port is not active */
223 tmp = readl(port_mmio + PORT_CMD);
224 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
225 PORT_CMD_FIS_RX | PORT_CMD_START)) {
226 debug("Port %d is active. Deactivating.\n", i);
227 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
228 PORT_CMD_FIS_RX | PORT_CMD_START);
229 writel_with_flush(tmp, port_mmio + PORT_CMD);
230
231 /* spec says 500 msecs for each bit, so
232 * this is slightly incorrect.
233 */
234 msleep(500);
235 }
236
237 #ifdef CONFIG_SUNXI_AHCI
238 sunxi_dma_init(port_mmio);
239 #endif
240
241 /* Add the spinup command to whatever mode bits may
242 * already be on in the command register.
243 */
244 cmd = readl(port_mmio + PORT_CMD);
245 cmd |= PORT_CMD_SPIN_UP;
246 writel_with_flush(cmd, port_mmio + PORT_CMD);
247
248 /* Bring up SATA link. */
249 ret = ahci_link_up(probe_ent, i);
250 if (ret) {
251 printf("SATA link %d timeout.\n", i);
252 continue;
253 } else {
254 debug("SATA link ok.\n");
255 }
256
257 /* Clear error status */
258 tmp = readl(port_mmio + PORT_SCR_ERR);
259 if (tmp)
260 writel(tmp, port_mmio + PORT_SCR_ERR);
261
262 debug("Spinning up device on SATA port %d... ", i);
263
264 j = 0;
265 while (j < WAIT_MS_SPINUP) {
266 tmp = readl(port_mmio + PORT_TFDATA);
267 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
268 break;
269 udelay(1000);
270 tmp = readl(port_mmio + PORT_SCR_STAT);
271 tmp &= PORT_SCR_STAT_DET_MASK;
272 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
273 break;
274 j++;
275 }
276
277 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
278 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
279 debug("SATA link %d down (COMINIT received), retrying...\n", i);
280 i--;
281 continue;
282 }
283
284 printf("Target spinup took %d ms.\n", j);
285 if (j == WAIT_MS_SPINUP)
286 debug("timeout.\n");
287 else
288 debug("ok.\n");
289
290 tmp = readl(port_mmio + PORT_SCR_ERR);
291 debug("PORT_SCR_ERR 0x%x\n", tmp);
292 writel(tmp, port_mmio + PORT_SCR_ERR);
293
294 /* ack any pending irq events for this port */
295 tmp = readl(port_mmio + PORT_IRQ_STAT);
296 debug("PORT_IRQ_STAT 0x%x\n", tmp);
297 if (tmp)
298 writel(tmp, port_mmio + PORT_IRQ_STAT);
299
300 writel(1 << i, mmio + HOST_IRQ_STAT);
301
302 /* set irq mask (enables interrupts) */
303 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
304
305 /* register linkup ports */
306 tmp = readl(port_mmio + PORT_SCR_STAT);
307 debug("SATA port %d status: 0x%x\n", i, tmp);
308 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
309 probe_ent->link_port_map |= (0x01 << i);
310 }
311
312 tmp = readl(mmio + HOST_CTL);
313 debug("HOST_CTL 0x%x\n", tmp);
314 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
315 tmp = readl(mmio + HOST_CTL);
316 debug("HOST_CTL 0x%x\n", tmp);
317 #ifndef CONFIG_SCSI_AHCI_PLAT
318 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
319 tmp |= PCI_COMMAND_MASTER;
320 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
321 #endif
322 return 0;
323 }
324
325
326 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
327 {
328 #ifndef CONFIG_SCSI_AHCI_PLAT
329 pci_dev_t pdev = probe_ent->dev;
330 u16 cc;
331 #endif
332 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
333 u32 vers, cap, cap2, impl, speed;
334 const char *speed_s;
335 const char *scc_s;
336
337 vers = readl(mmio + HOST_VERSION);
338 cap = probe_ent->cap;
339 cap2 = readl(mmio + HOST_CAP2);
340 impl = probe_ent->port_map;
341
342 speed = (cap >> 20) & 0xf;
343 if (speed == 1)
344 speed_s = "1.5";
345 else if (speed == 2)
346 speed_s = "3";
347 else if (speed == 3)
348 speed_s = "6";
349 else
350 speed_s = "?";
351
352 #ifdef CONFIG_SCSI_AHCI_PLAT
353 scc_s = "SATA";
354 #else
355 pci_read_config_word(pdev, 0x0a, &cc);
356 if (cc == 0x0101)
357 scc_s = "IDE";
358 else if (cc == 0x0106)
359 scc_s = "SATA";
360 else if (cc == 0x0104)
361 scc_s = "RAID";
362 else
363 scc_s = "unknown";
364 #endif
365 printf("AHCI %02x%02x.%02x%02x "
366 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
367 (vers >> 24) & 0xff,
368 (vers >> 16) & 0xff,
369 (vers >> 8) & 0xff,
370 vers & 0xff,
371 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
372
373 printf("flags: "
374 "%s%s%s%s%s%s%s"
375 "%s%s%s%s%s%s%s"
376 "%s%s%s%s%s%s\n",
377 cap & (1 << 31) ? "64bit " : "",
378 cap & (1 << 30) ? "ncq " : "",
379 cap & (1 << 28) ? "ilck " : "",
380 cap & (1 << 27) ? "stag " : "",
381 cap & (1 << 26) ? "pm " : "",
382 cap & (1 << 25) ? "led " : "",
383 cap & (1 << 24) ? "clo " : "",
384 cap & (1 << 19) ? "nz " : "",
385 cap & (1 << 18) ? "only " : "",
386 cap & (1 << 17) ? "pmp " : "",
387 cap & (1 << 16) ? "fbss " : "",
388 cap & (1 << 15) ? "pio " : "",
389 cap & (1 << 14) ? "slum " : "",
390 cap & (1 << 13) ? "part " : "",
391 cap & (1 << 7) ? "ccc " : "",
392 cap & (1 << 6) ? "ems " : "",
393 cap & (1 << 5) ? "sxs " : "",
394 cap2 & (1 << 2) ? "apst " : "",
395 cap2 & (1 << 1) ? "nvmp " : "",
396 cap2 & (1 << 0) ? "boh " : "");
397 }
398
399 #ifndef CONFIG_SCSI_AHCI_PLAT
400 static int ahci_init_one(pci_dev_t pdev)
401 {
402 u16 vendor;
403 int rc;
404
405 probe_ent = malloc(sizeof(struct ahci_probe_ent));
406 if (!probe_ent) {
407 printf("%s: No memory for probe_ent\n", __func__);
408 return -ENOMEM;
409 }
410
411 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
412 probe_ent->dev = pdev;
413
414 probe_ent->host_flags = ATA_FLAG_SATA
415 | ATA_FLAG_NO_LEGACY
416 | ATA_FLAG_MMIO
417 | ATA_FLAG_PIO_DMA
418 | ATA_FLAG_NO_ATAPI;
419 probe_ent->pio_mask = 0x1f;
420 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
421
422 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
423 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
424
425 /* Take from kernel:
426 * JMicron-specific fixup:
427 * make sure we're in AHCI mode
428 */
429 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
430 if (vendor == 0x197b)
431 pci_write_config_byte(pdev, 0x41, 0xa1);
432
433 /* initialize adapter */
434 rc = ahci_host_init(probe_ent);
435 if (rc)
436 goto err_out;
437
438 ahci_print_info(probe_ent);
439
440 return 0;
441
442 err_out:
443 return rc;
444 }
445 #endif
446
447 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
448
449 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
450 {
451 struct ahci_ioports *pp = &(probe_ent->port[port]);
452 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
453 u32 sg_count;
454 int i;
455
456 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
457 if (sg_count > AHCI_MAX_SG) {
458 printf("Error:Too much sg!\n");
459 return -1;
460 }
461
462 for (i = 0; i < sg_count; i++) {
463 ahci_sg->addr =
464 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
465 ahci_sg->addr_hi = 0;
466 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
467 (buf_len < MAX_DATA_BYTE_COUNT
468 ? (buf_len - 1)
469 : (MAX_DATA_BYTE_COUNT - 1)));
470 ahci_sg++;
471 buf_len -= MAX_DATA_BYTE_COUNT;
472 }
473
474 return sg_count;
475 }
476
477
478 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
479 {
480 pp->cmd_slot->opts = cpu_to_le32(opts);
481 pp->cmd_slot->status = 0;
482 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
483 pp->cmd_slot->tbl_addr_hi = 0;
484 }
485
486
487 #ifdef CONFIG_AHCI_SETFEATURES_XFER
488 static void ahci_set_feature(u8 port)
489 {
490 struct ahci_ioports *pp = &(probe_ent->port[port]);
491 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
492 u32 cmd_fis_len = 5; /* five dwords */
493 u8 fis[20];
494
495 /* set feature */
496 memset(fis, 0, sizeof(fis));
497 fis[0] = 0x27;
498 fis[1] = 1 << 7;
499 fis[2] = ATA_CMD_SET_FEATURES;
500 fis[3] = SETFEATURES_XFER;
501 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
502
503 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
504 ahci_fill_cmd_slot(pp, cmd_fis_len);
505 ahci_dcache_flush_sata_cmd(pp);
506 writel(1, port_mmio + PORT_CMD_ISSUE);
507 readl(port_mmio + PORT_CMD_ISSUE);
508
509 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
510 WAIT_MS_DATAIO, 0x1)) {
511 printf("set feature error on port %d!\n", port);
512 }
513 }
514 #endif
515
516 static int wait_spinup(volatile u8 *port_mmio)
517 {
518 ulong start;
519 u32 tf_data;
520
521 start = get_timer(0);
522 do {
523 tf_data = readl(port_mmio + PORT_TFDATA);
524 if (!(tf_data & ATA_BUSY))
525 return 0;
526 } while (get_timer(start) < WAIT_MS_SPINUP);
527
528 return -ETIMEDOUT;
529 }
530
531 static int ahci_port_start(u8 port)
532 {
533 struct ahci_ioports *pp = &(probe_ent->port[port]);
534 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
535 u32 port_status;
536 u32 mem;
537
538 debug("Enter start port: %d\n", port);
539 port_status = readl(port_mmio + PORT_SCR_STAT);
540 debug("Port %d status: %x\n", port, port_status);
541 if ((port_status & 0xf) != 0x03) {
542 printf("No Link on this port!\n");
543 return -1;
544 }
545
546 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
547 if (!mem) {
548 free(pp);
549 printf("%s: No mem for table!\n", __func__);
550 return -ENOMEM;
551 }
552
553 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
554 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
555
556 /*
557 * First item in chunk of DMA memory: 32-slot command table,
558 * 32 bytes each in size
559 */
560 pp->cmd_slot =
561 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
562 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
563 mem += (AHCI_CMD_SLOT_SZ + 224);
564
565 /*
566 * Second item: Received-FIS area
567 */
568 pp->rx_fis = virt_to_phys((void *)mem);
569 mem += AHCI_RX_FIS_SZ;
570
571 /*
572 * Third item: data area for storing a single command
573 * and its scatter-gather table
574 */
575 pp->cmd_tbl = virt_to_phys((void *)mem);
576 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
577
578 mem += AHCI_CMD_TBL_HDR;
579 pp->cmd_tbl_sg =
580 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
581
582 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
583
584 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
585
586 #ifdef CONFIG_SUNXI_AHCI
587 sunxi_dma_init(port_mmio);
588 #endif
589
590 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
591 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
592 PORT_CMD_START, port_mmio + PORT_CMD);
593
594 debug("Exit start port %d\n", port);
595
596 /*
597 * Make sure interface is not busy based on error and status
598 * information from task file data register before proceeding
599 */
600 return wait_spinup(port_mmio);
601 }
602
603
604 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
605 int buf_len, u8 is_write)
606 {
607
608 struct ahci_ioports *pp = &(probe_ent->port[port]);
609 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
610 u32 opts;
611 u32 port_status;
612 int sg_count;
613
614 debug("Enter %s: for port %d\n", __func__, port);
615
616 if (port > probe_ent->n_ports) {
617 printf("Invalid port number %d\n", port);
618 return -1;
619 }
620
621 port_status = readl(port_mmio + PORT_SCR_STAT);
622 if ((port_status & 0xf) != 0x03) {
623 debug("No Link on port %d!\n", port);
624 return -1;
625 }
626
627 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
628
629 sg_count = ahci_fill_sg(port, buf, buf_len);
630 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
631 ahci_fill_cmd_slot(pp, opts);
632
633 ahci_dcache_flush_sata_cmd(pp);
634 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
635
636 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
637
638 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
639 WAIT_MS_DATAIO, 0x1)) {
640 printf("timeout exit!\n");
641 return -1;
642 }
643
644 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
645 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
646
647 return 0;
648 }
649
650
651 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
652 {
653 int i;
654 for (i = 0; i < len / 2; i++)
655 target[i] = swab16(src[i]);
656 return (char *)target;
657 }
658
659 /*
660 * SCSI INQUIRY command operation.
661 */
662 static int ata_scsiop_inquiry(ccb *pccb)
663 {
664 static const u8 hdr[] = {
665 0,
666 0,
667 0x5, /* claim SPC-3 version compatibility */
668 2,
669 95 - 4,
670 };
671 u8 fis[20];
672 u16 *idbuf;
673 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
674 u8 port;
675
676 /* Clean ccb data buffer */
677 memset(pccb->pdata, 0, pccb->datalen);
678
679 memcpy(pccb->pdata, hdr, sizeof(hdr));
680
681 if (pccb->datalen <= 35)
682 return 0;
683
684 memset(fis, 0, sizeof(fis));
685 /* Construct the FIS */
686 fis[0] = 0x27; /* Host to device FIS. */
687 fis[1] = 1 << 7; /* Command FIS. */
688 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
689
690 /* Read id from sata */
691 port = pccb->target;
692
693 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
694 ATA_ID_WORDS * 2, 0)) {
695 debug("scsi_ahci: SCSI inquiry command failure.\n");
696 return -EIO;
697 }
698
699 if (!ataid[port]) {
700 ataid[port] = malloc(ATA_ID_WORDS * 2);
701 if (!ataid[port]) {
702 printf("%s: No memory for ataid[port]\n", __func__);
703 return -ENOMEM;
704 }
705 }
706
707 idbuf = ataid[port];
708
709 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
710 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
711
712 memcpy(&pccb->pdata[8], "ATA ", 8);
713 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
714 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
715
716 #ifdef DEBUG
717 ata_dump_id(idbuf);
718 #endif
719 return 0;
720 }
721
722
723 /*
724 * SCSI READ10/WRITE10 command operation.
725 */
726 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
727 {
728 u32 lba = 0;
729 u16 blocks = 0;
730 u8 fis[20];
731 u8 *user_buffer = pccb->pdata;
732 u32 user_buffer_size = pccb->datalen;
733
734 /* Retrieve the base LBA number from the ccb structure. */
735 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
736 lba = be32_to_cpu(lba);
737
738 /*
739 * And the number of blocks.
740 *
741 * For 10-byte and 16-byte SCSI R/W commands, transfer
742 * length 0 means transfer 0 block of data.
743 * However, for ATA R/W commands, sector count 0 means
744 * 256 or 65536 sectors, not 0 sectors as in SCSI.
745 *
746 * WARNING: one or two older ATA drives treat 0 as 0...
747 */
748 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
749
750 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
751 is_write ? "write" : "read", (unsigned)lba, blocks);
752
753 /* Preset the FIS */
754 memset(fis, 0, sizeof(fis));
755 fis[0] = 0x27; /* Host to device FIS. */
756 fis[1] = 1 << 7; /* Command FIS. */
757 /* Command byte (read/write). */
758 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
759
760 while (blocks) {
761 u16 now_blocks; /* number of blocks per iteration */
762 u32 transfer_size; /* number of bytes per iteration */
763
764 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
765
766 transfer_size = ATA_SECT_SIZE * now_blocks;
767 if (transfer_size > user_buffer_size) {
768 printf("scsi_ahci: Error: buffer too small.\n");
769 return -EIO;
770 }
771
772 /* LBA48 SATA command but only use 32bit address range within
773 * that. The next smaller command range (28bit) is too small.
774 */
775 fis[4] = (lba >> 0) & 0xff;
776 fis[5] = (lba >> 8) & 0xff;
777 fis[6] = (lba >> 16) & 0xff;
778 fis[7] = 1 << 6; /* device reg: set LBA mode */
779 fis[8] = ((lba >> 24) & 0xff);
780 fis[3] = 0xe0; /* features */
781
782 /* Block (sector) count */
783 fis[12] = (now_blocks >> 0) & 0xff;
784 fis[13] = (now_blocks >> 8) & 0xff;
785
786 /* Read/Write from ahci */
787 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
788 user_buffer, user_buffer_size,
789 is_write)) {
790 debug("scsi_ahci: SCSI %s10 command failure.\n",
791 is_write ? "WRITE" : "READ");
792 return -EIO;
793 }
794
795 /* If this transaction is a write, do a following flush.
796 * Writes in u-boot are so rare, and the logic to know when is
797 * the last write and do a flush only there is sufficiently
798 * difficult. Just do a flush after every write. This incurs,
799 * usually, one extra flush when the rare writes do happen.
800 */
801 if (is_write) {
802 if (-EIO == ata_io_flush(pccb->target))
803 return -EIO;
804 }
805 user_buffer += transfer_size;
806 user_buffer_size -= transfer_size;
807 blocks -= now_blocks;
808 lba += now_blocks;
809 }
810
811 return 0;
812 }
813
814
815 /*
816 * SCSI READ CAPACITY10 command operation.
817 */
818 static int ata_scsiop_read_capacity10(ccb *pccb)
819 {
820 u32 cap;
821 u64 cap64;
822 u32 block_size;
823
824 if (!ataid[pccb->target]) {
825 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
826 "\tNo ATA info!\n"
827 "\tPlease run SCSI commmand INQUIRY firstly!\n");
828 return -EPERM;
829 }
830
831 cap64 = ata_id_n_sectors(ataid[pccb->target]);
832 if (cap64 > 0x100000000ULL)
833 cap64 = 0xffffffff;
834
835 cap = cpu_to_be32(cap64);
836 memcpy(pccb->pdata, &cap, sizeof(cap));
837
838 block_size = cpu_to_be32((u32)512);
839 memcpy(&pccb->pdata[4], &block_size, 4);
840
841 return 0;
842 }
843
844
845 /*
846 * SCSI READ CAPACITY16 command operation.
847 */
848 static int ata_scsiop_read_capacity16(ccb *pccb)
849 {
850 u64 cap;
851 u64 block_size;
852
853 if (!ataid[pccb->target]) {
854 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
855 "\tNo ATA info!\n"
856 "\tPlease run SCSI commmand INQUIRY firstly!\n");
857 return -EPERM;
858 }
859
860 cap = ata_id_n_sectors(ataid[pccb->target]);
861 cap = cpu_to_be64(cap);
862 memcpy(pccb->pdata, &cap, sizeof(cap));
863
864 block_size = cpu_to_be64((u64)512);
865 memcpy(&pccb->pdata[8], &block_size, 8);
866
867 return 0;
868 }
869
870
871 /*
872 * SCSI TEST UNIT READY command operation.
873 */
874 static int ata_scsiop_test_unit_ready(ccb *pccb)
875 {
876 return (ataid[pccb->target]) ? 0 : -EPERM;
877 }
878
879
880 int scsi_exec(ccb *pccb)
881 {
882 int ret;
883
884 switch (pccb->cmd[0]) {
885 case SCSI_READ10:
886 ret = ata_scsiop_read_write(pccb, 0);
887 break;
888 case SCSI_WRITE10:
889 ret = ata_scsiop_read_write(pccb, 1);
890 break;
891 case SCSI_RD_CAPAC10:
892 ret = ata_scsiop_read_capacity10(pccb);
893 break;
894 case SCSI_RD_CAPAC16:
895 ret = ata_scsiop_read_capacity16(pccb);
896 break;
897 case SCSI_TST_U_RDY:
898 ret = ata_scsiop_test_unit_ready(pccb);
899 break;
900 case SCSI_INQUIRY:
901 ret = ata_scsiop_inquiry(pccb);
902 break;
903 default:
904 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
905 return false;
906 }
907
908 if (ret) {
909 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
910 return false;
911 }
912 return true;
913
914 }
915
916
917 void scsi_low_level_init(int busdevfunc)
918 {
919 int i;
920 u32 linkmap;
921
922 #ifndef CONFIG_SCSI_AHCI_PLAT
923 ahci_init_one(busdevfunc);
924 #endif
925
926 linkmap = probe_ent->link_port_map;
927
928 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
929 if (((linkmap >> i) & 0x01)) {
930 if (ahci_port_start((u8) i)) {
931 printf("Can not start port %d\n", i);
932 continue;
933 }
934 #ifdef CONFIG_AHCI_SETFEATURES_XFER
935 ahci_set_feature((u8) i);
936 #endif
937 }
938 }
939 }
940
941 #ifdef CONFIG_SCSI_AHCI_PLAT
942 int ahci_init(u32 base)
943 {
944 int i, rc = 0;
945 u32 linkmap;
946
947 probe_ent = malloc(sizeof(struct ahci_probe_ent));
948 if (!probe_ent) {
949 printf("%s: No memory for probe_ent\n", __func__);
950 return -ENOMEM;
951 }
952
953 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
954
955 probe_ent->host_flags = ATA_FLAG_SATA
956 | ATA_FLAG_NO_LEGACY
957 | ATA_FLAG_MMIO
958 | ATA_FLAG_PIO_DMA
959 | ATA_FLAG_NO_ATAPI;
960 probe_ent->pio_mask = 0x1f;
961 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
962
963 probe_ent->mmio_base = base;
964
965 /* initialize adapter */
966 rc = ahci_host_init(probe_ent);
967 if (rc)
968 goto err_out;
969
970 ahci_print_info(probe_ent);
971
972 linkmap = probe_ent->link_port_map;
973
974 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
975 if (((linkmap >> i) & 0x01)) {
976 if (ahci_port_start((u8) i)) {
977 printf("Can not start port %d\n", i);
978 continue;
979 }
980 #ifdef CONFIG_AHCI_SETFEATURES_XFER
981 ahci_set_feature((u8) i);
982 #endif
983 }
984 }
985 err_out:
986 return rc;
987 }
988
989 void __weak scsi_init(void)
990 {
991 }
992
993 #endif
994
995 /*
996 * In the general case of generic rotating media it makes sense to have a
997 * flush capability. It probably even makes sense in the case of SSDs because
998 * one cannot always know for sure what kind of internal cache/flush mechanism
999 * is embodied therein. At first it was planned to invoke this after the last
1000 * write to disk and before rebooting. In practice, knowing, a priori, which
1001 * is the last write is difficult. Because writing to the disk in u-boot is
1002 * very rare, this flush command will be invoked after every block write.
1003 */
1004 static int ata_io_flush(u8 port)
1005 {
1006 u8 fis[20];
1007 struct ahci_ioports *pp = &(probe_ent->port[port]);
1008 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
1009 u32 cmd_fis_len = 5; /* five dwords */
1010
1011 /* Preset the FIS */
1012 memset(fis, 0, 20);
1013 fis[0] = 0x27; /* Host to device FIS. */
1014 fis[1] = 1 << 7; /* Command FIS. */
1015 fis[2] = ATA_CMD_FLUSH_EXT;
1016
1017 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1018 ahci_fill_cmd_slot(pp, cmd_fis_len);
1019 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1020
1021 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1022 WAIT_MS_FLUSH, 0x1)) {
1023 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1024 return -EIO;
1025 }
1026
1027 return 0;
1028 }
1029
1030
1031 __weak void scsi_bus_reset(void)
1032 {
1033 /*Not implement*/
1034 }
1035
1036 void scsi_print_error(ccb * pccb)
1037 {
1038 /*The ahci error info can be read in the ahci driver*/
1039 }
"Das U-Boot" Source Tree