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Merge branch 'master' of git://git.denx.de/u-boot-arm
[people/ms/u-boot.git] / drivers / block / ahci.c
1 /*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * with the reference on libata and ahci drvier in kernel
9 */
10 #include <common.h>
11
12 #include <command.h>
13 #include <pci.h>
14 #include <asm/processor.h>
15 #include <asm/errno.h>
16 #include <asm/io.h>
17 #include <malloc.h>
18 #include <scsi.h>
19 #include <libata.h>
20 #include <linux/ctype.h>
21 #include <ahci.h>
22
23 static int ata_io_flush(u8 port);
24
25 struct ahci_probe_ent *probe_ent = NULL;
26 u16 *ataid[AHCI_MAX_PORTS];
27
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
29
30 /*
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
34 * needed.
35 */
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
38 #endif
39
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 20000
42 #define WAIT_MS_DATAIO 5000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 4
45
46 static inline u32 ahci_port_base(u32 base, u32 port)
47 {
48 return base + 0x100 + (port * 0x80);
49 }
50
51
52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx)
54 {
55 base = ahci_port_base(base, port_idx);
56
57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
59 }
60
61
62 #define msleep(a) udelay(a * 1000)
63
64 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
65 {
66 const unsigned long start = begin;
67 const unsigned long end = start + len;
68
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end);
71 }
72
73 /*
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
76 * physical RAM.
77 */
78 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
79 {
80 const unsigned long start = begin;
81 const unsigned long end = start + len;
82
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end);
85 }
86
87 /*
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
90 */
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
92 {
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ);
95 }
96
97 static int waiting_for_cmd_completed(volatile u8 *offset,
98 int timeout_msec,
99 u32 sign)
100 {
101 int i;
102 u32 status;
103
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
105 msleep(1);
106
107 return (i < timeout_msec) ? 0 : -1;
108 }
109
110 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
111 {
112 u32 tmp;
113 int j = 0;
114 u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
115
116 /*
117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
120 */
121 while (j < WAIT_MS_LINKUP) {
122 tmp = readl(port_mmio + PORT_SCR_STAT);
123 tmp &= PORT_SCR_STAT_DET_MASK;
124 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
125 return 0;
126 udelay(1000);
127 j++;
128 }
129 return 1;
130 }
131
132 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
133 {
134 #ifndef CONFIG_SCSI_AHCI_PLAT
135 pci_dev_t pdev = probe_ent->dev;
136 u16 tmp16;
137 unsigned short vendor;
138 #endif
139 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
140 u32 tmp, cap_save, cmd;
141 int i, j, ret;
142 volatile u8 *port_mmio;
143 u32 port_map;
144
145 debug("ahci_host_init: start\n");
146
147 cap_save = readl(mmio + HOST_CAP);
148 cap_save &= ((1 << 28) | (1 << 17));
149 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
150
151 /* global controller reset */
152 tmp = readl(mmio + HOST_CTL);
153 if ((tmp & HOST_RESET) == 0)
154 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
155
156 /* reset must complete within 1 second, or
157 * the hardware should be considered fried.
158 */
159 i = 1000;
160 do {
161 udelay(1000);
162 tmp = readl(mmio + HOST_CTL);
163 if (!i--) {
164 debug("controller reset failed (0x%x)\n", tmp);
165 return -1;
166 }
167 } while (tmp & HOST_RESET);
168
169 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
170 writel(cap_save, mmio + HOST_CAP);
171 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
172
173 #ifndef CONFIG_SCSI_AHCI_PLAT
174 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
175
176 if (vendor == PCI_VENDOR_ID_INTEL) {
177 u16 tmp16;
178 pci_read_config_word(pdev, 0x92, &tmp16);
179 tmp16 |= 0xf;
180 pci_write_config_word(pdev, 0x92, tmp16);
181 }
182 #endif
183 probe_ent->cap = readl(mmio + HOST_CAP);
184 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
185 port_map = probe_ent->port_map;
186 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
187
188 debug("cap 0x%x port_map 0x%x n_ports %d\n",
189 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
190
191 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
192 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
193
194 for (i = 0; i < probe_ent->n_ports; i++) {
195 if (!(port_map & (1 << i)))
196 continue;
197 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
198 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
199 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
200
201 /* make sure port is not active */
202 tmp = readl(port_mmio + PORT_CMD);
203 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
204 PORT_CMD_FIS_RX | PORT_CMD_START)) {
205 debug("Port %d is active. Deactivating.\n", i);
206 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
207 PORT_CMD_FIS_RX | PORT_CMD_START);
208 writel_with_flush(tmp, port_mmio + PORT_CMD);
209
210 /* spec says 500 msecs for each bit, so
211 * this is slightly incorrect.
212 */
213 msleep(500);
214 }
215
216 /* Add the spinup command to whatever mode bits may
217 * already be on in the command register.
218 */
219 cmd = readl(port_mmio + PORT_CMD);
220 cmd |= PORT_CMD_FIS_RX;
221 cmd |= PORT_CMD_SPIN_UP;
222 writel_with_flush(cmd, port_mmio + PORT_CMD);
223
224 /* Bring up SATA link. */
225 ret = ahci_link_up(probe_ent, i);
226 if (ret) {
227 printf("SATA link %d timeout.\n", i);
228 continue;
229 } else {
230 debug("SATA link ok.\n");
231 }
232
233 /* Clear error status */
234 tmp = readl(port_mmio + PORT_SCR_ERR);
235 if (tmp)
236 writel(tmp, port_mmio + PORT_SCR_ERR);
237
238 debug("Spinning up device on SATA port %d... ", i);
239
240 j = 0;
241 while (j < WAIT_MS_SPINUP) {
242 tmp = readl(port_mmio + PORT_TFDATA);
243 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
244 break;
245 udelay(1000);
246 tmp = readl(port_mmio + PORT_SCR_STAT);
247 tmp &= PORT_SCR_STAT_DET_MASK;
248 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
249 break;
250 j++;
251 }
252
253 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
254 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
255 debug("SATA link %d down (COMINIT received), retrying...\n", i);
256 i--;
257 continue;
258 }
259
260 printf("Target spinup took %d ms.\n", j);
261 if (j == WAIT_MS_SPINUP)
262 debug("timeout.\n");
263 else
264 debug("ok.\n");
265
266 tmp = readl(port_mmio + PORT_SCR_ERR);
267 debug("PORT_SCR_ERR 0x%x\n", tmp);
268 writel(tmp, port_mmio + PORT_SCR_ERR);
269
270 /* ack any pending irq events for this port */
271 tmp = readl(port_mmio + PORT_IRQ_STAT);
272 debug("PORT_IRQ_STAT 0x%x\n", tmp);
273 if (tmp)
274 writel(tmp, port_mmio + PORT_IRQ_STAT);
275
276 writel(1 << i, mmio + HOST_IRQ_STAT);
277
278 /* set irq mask (enables interrupts) */
279 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
280
281 /* register linkup ports */
282 tmp = readl(port_mmio + PORT_SCR_STAT);
283 debug("SATA port %d status: 0x%x\n", i, tmp);
284 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
285 probe_ent->link_port_map |= (0x01 << i);
286 }
287
288 tmp = readl(mmio + HOST_CTL);
289 debug("HOST_CTL 0x%x\n", tmp);
290 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
291 tmp = readl(mmio + HOST_CTL);
292 debug("HOST_CTL 0x%x\n", tmp);
293 #ifndef CONFIG_SCSI_AHCI_PLAT
294 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
295 tmp |= PCI_COMMAND_MASTER;
296 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
297 #endif
298 return 0;
299 }
300
301
302 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
303 {
304 #ifndef CONFIG_SCSI_AHCI_PLAT
305 pci_dev_t pdev = probe_ent->dev;
306 u16 cc;
307 #endif
308 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
309 u32 vers, cap, cap2, impl, speed;
310 const char *speed_s;
311 const char *scc_s;
312
313 vers = readl(mmio + HOST_VERSION);
314 cap = probe_ent->cap;
315 cap2 = readl(mmio + HOST_CAP2);
316 impl = probe_ent->port_map;
317
318 speed = (cap >> 20) & 0xf;
319 if (speed == 1)
320 speed_s = "1.5";
321 else if (speed == 2)
322 speed_s = "3";
323 else if (speed == 3)
324 speed_s = "6";
325 else
326 speed_s = "?";
327
328 #ifdef CONFIG_SCSI_AHCI_PLAT
329 scc_s = "SATA";
330 #else
331 pci_read_config_word(pdev, 0x0a, &cc);
332 if (cc == 0x0101)
333 scc_s = "IDE";
334 else if (cc == 0x0106)
335 scc_s = "SATA";
336 else if (cc == 0x0104)
337 scc_s = "RAID";
338 else
339 scc_s = "unknown";
340 #endif
341 printf("AHCI %02x%02x.%02x%02x "
342 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
343 (vers >> 24) & 0xff,
344 (vers >> 16) & 0xff,
345 (vers >> 8) & 0xff,
346 vers & 0xff,
347 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
348
349 printf("flags: "
350 "%s%s%s%s%s%s%s"
351 "%s%s%s%s%s%s%s"
352 "%s%s%s%s%s%s\n",
353 cap & (1 << 31) ? "64bit " : "",
354 cap & (1 << 30) ? "ncq " : "",
355 cap & (1 << 28) ? "ilck " : "",
356 cap & (1 << 27) ? "stag " : "",
357 cap & (1 << 26) ? "pm " : "",
358 cap & (1 << 25) ? "led " : "",
359 cap & (1 << 24) ? "clo " : "",
360 cap & (1 << 19) ? "nz " : "",
361 cap & (1 << 18) ? "only " : "",
362 cap & (1 << 17) ? "pmp " : "",
363 cap & (1 << 16) ? "fbss " : "",
364 cap & (1 << 15) ? "pio " : "",
365 cap & (1 << 14) ? "slum " : "",
366 cap & (1 << 13) ? "part " : "",
367 cap & (1 << 7) ? "ccc " : "",
368 cap & (1 << 6) ? "ems " : "",
369 cap & (1 << 5) ? "sxs " : "",
370 cap2 & (1 << 2) ? "apst " : "",
371 cap2 & (1 << 1) ? "nvmp " : "",
372 cap2 & (1 << 0) ? "boh " : "");
373 }
374
375 #ifndef CONFIG_SCSI_AHCI_PLAT
376 static int ahci_init_one(pci_dev_t pdev)
377 {
378 u16 vendor;
379 int rc;
380
381 probe_ent = malloc(sizeof(struct ahci_probe_ent));
382 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
383 probe_ent->dev = pdev;
384
385 probe_ent->host_flags = ATA_FLAG_SATA
386 | ATA_FLAG_NO_LEGACY
387 | ATA_FLAG_MMIO
388 | ATA_FLAG_PIO_DMA
389 | ATA_FLAG_NO_ATAPI;
390 probe_ent->pio_mask = 0x1f;
391 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
392
393 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
394 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
395
396 /* Take from kernel:
397 * JMicron-specific fixup:
398 * make sure we're in AHCI mode
399 */
400 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
401 if (vendor == 0x197b)
402 pci_write_config_byte(pdev, 0x41, 0xa1);
403
404 /* initialize adapter */
405 rc = ahci_host_init(probe_ent);
406 if (rc)
407 goto err_out;
408
409 ahci_print_info(probe_ent);
410
411 return 0;
412
413 err_out:
414 return rc;
415 }
416 #endif
417
418 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
419
420 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
421 {
422 struct ahci_ioports *pp = &(probe_ent->port[port]);
423 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
424 u32 sg_count;
425 int i;
426
427 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
428 if (sg_count > AHCI_MAX_SG) {
429 printf("Error:Too much sg!\n");
430 return -1;
431 }
432
433 for (i = 0; i < sg_count; i++) {
434 ahci_sg->addr =
435 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
436 ahci_sg->addr_hi = 0;
437 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
438 (buf_len < MAX_DATA_BYTE_COUNT
439 ? (buf_len - 1)
440 : (MAX_DATA_BYTE_COUNT - 1)));
441 ahci_sg++;
442 buf_len -= MAX_DATA_BYTE_COUNT;
443 }
444
445 return sg_count;
446 }
447
448
449 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
450 {
451 pp->cmd_slot->opts = cpu_to_le32(opts);
452 pp->cmd_slot->status = 0;
453 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
454 pp->cmd_slot->tbl_addr_hi = 0;
455 }
456
457
458 #ifdef CONFIG_AHCI_SETFEATURES_XFER
459 static void ahci_set_feature(u8 port)
460 {
461 struct ahci_ioports *pp = &(probe_ent->port[port]);
462 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
463 u32 cmd_fis_len = 5; /* five dwords */
464 u8 fis[20];
465
466 /* set feature */
467 memset(fis, 0, sizeof(fis));
468 fis[0] = 0x27;
469 fis[1] = 1 << 7;
470 fis[2] = ATA_CMD_SET_FEATURES;
471 fis[3] = SETFEATURES_XFER;
472 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
473
474 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
475 ahci_fill_cmd_slot(pp, cmd_fis_len);
476 ahci_dcache_flush_sata_cmd(pp);
477 writel(1, port_mmio + PORT_CMD_ISSUE);
478 readl(port_mmio + PORT_CMD_ISSUE);
479
480 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
481 WAIT_MS_DATAIO, 0x1)) {
482 printf("set feature error on port %d!\n", port);
483 }
484 }
485 #endif
486
487
488 static int ahci_port_start(u8 port)
489 {
490 struct ahci_ioports *pp = &(probe_ent->port[port]);
491 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
492 u32 port_status;
493 u32 mem;
494
495 debug("Enter start port: %d\n", port);
496 port_status = readl(port_mmio + PORT_SCR_STAT);
497 debug("Port %d status: %x\n", port, port_status);
498 if ((port_status & 0xf) != 0x03) {
499 printf("No Link on this port!\n");
500 return -1;
501 }
502
503 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
504 if (!mem) {
505 free(pp);
506 printf("No mem for table!\n");
507 return -ENOMEM;
508 }
509
510 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
511 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
512
513 /*
514 * First item in chunk of DMA memory: 32-slot command table,
515 * 32 bytes each in size
516 */
517 pp->cmd_slot =
518 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
519 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
520 mem += (AHCI_CMD_SLOT_SZ + 224);
521
522 /*
523 * Second item: Received-FIS area
524 */
525 pp->rx_fis = virt_to_phys((void *)mem);
526 mem += AHCI_RX_FIS_SZ;
527
528 /*
529 * Third item: data area for storing a single command
530 * and its scatter-gather table
531 */
532 pp->cmd_tbl = virt_to_phys((void *)mem);
533 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
534
535 mem += AHCI_CMD_TBL_HDR;
536 pp->cmd_tbl_sg =
537 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
538
539 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
540
541 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
542
543 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
544 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
545 PORT_CMD_START, port_mmio + PORT_CMD);
546
547 debug("Exit start port %d\n", port);
548
549 return 0;
550 }
551
552
553 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
554 int buf_len, u8 is_write)
555 {
556
557 struct ahci_ioports *pp = &(probe_ent->port[port]);
558 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
559 u32 opts;
560 u32 port_status;
561 int sg_count;
562
563 debug("Enter %s: for port %d\n", __func__, port);
564
565 if (port > probe_ent->n_ports) {
566 printf("Invalid port number %d\n", port);
567 return -1;
568 }
569
570 port_status = readl(port_mmio + PORT_SCR_STAT);
571 if ((port_status & 0xf) != 0x03) {
572 debug("No Link on port %d!\n", port);
573 return -1;
574 }
575
576 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
577
578 sg_count = ahci_fill_sg(port, buf, buf_len);
579 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
580 ahci_fill_cmd_slot(pp, opts);
581
582 ahci_dcache_flush_sata_cmd(pp);
583 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
584
585 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
586
587 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
588 WAIT_MS_DATAIO, 0x1)) {
589 printf("timeout exit!\n");
590 return -1;
591 }
592
593 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
594 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
595
596 return 0;
597 }
598
599
600 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
601 {
602 int i;
603 for (i = 0; i < len / 2; i++)
604 target[i] = swab16(src[i]);
605 return (char *)target;
606 }
607
608 /*
609 * SCSI INQUIRY command operation.
610 */
611 static int ata_scsiop_inquiry(ccb *pccb)
612 {
613 static const u8 hdr[] = {
614 0,
615 0,
616 0x5, /* claim SPC-3 version compatibility */
617 2,
618 95 - 4,
619 };
620 u8 fis[20];
621 u16 *tmpid;
622 u8 port;
623
624 /* Clean ccb data buffer */
625 memset(pccb->pdata, 0, pccb->datalen);
626
627 memcpy(pccb->pdata, hdr, sizeof(hdr));
628
629 if (pccb->datalen <= 35)
630 return 0;
631
632 memset(fis, 0, sizeof(fis));
633 /* Construct the FIS */
634 fis[0] = 0x27; /* Host to device FIS. */
635 fis[1] = 1 << 7; /* Command FIS. */
636 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
637
638 /* Read id from sata */
639 port = pccb->target;
640 tmpid = malloc(ATA_ID_WORDS * 2);
641 if (!tmpid)
642 return -ENOMEM;
643
644 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
645 ATA_ID_WORDS * 2, 0)) {
646 debug("scsi_ahci: SCSI inquiry command failure.\n");
647 free(tmpid);
648 return -EIO;
649 }
650
651 if (ataid[port])
652 free(ataid[port]);
653 ataid[port] = tmpid;
654 ata_swap_buf_le16(tmpid, ATA_ID_WORDS);
655
656 memcpy(&pccb->pdata[8], "ATA ", 8);
657 ata_id_strcpy((u16 *) &pccb->pdata[16], &tmpid[ATA_ID_PROD], 16);
658 ata_id_strcpy((u16 *) &pccb->pdata[32], &tmpid[ATA_ID_FW_REV], 4);
659
660 #ifdef DEBUG
661 ata_dump_id(tmpid);
662 #endif
663 return 0;
664 }
665
666
667 /*
668 * SCSI READ10/WRITE10 command operation.
669 */
670 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
671 {
672 u32 lba = 0;
673 u16 blocks = 0;
674 u8 fis[20];
675 u8 *user_buffer = pccb->pdata;
676 u32 user_buffer_size = pccb->datalen;
677
678 /* Retrieve the base LBA number from the ccb structure. */
679 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
680 lba = be32_to_cpu(lba);
681
682 /*
683 * And the number of blocks.
684 *
685 * For 10-byte and 16-byte SCSI R/W commands, transfer
686 * length 0 means transfer 0 block of data.
687 * However, for ATA R/W commands, sector count 0 means
688 * 256 or 65536 sectors, not 0 sectors as in SCSI.
689 *
690 * WARNING: one or two older ATA drives treat 0 as 0...
691 */
692 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
693
694 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
695 is_write ? "write" : "read", (unsigned)lba, blocks);
696
697 /* Preset the FIS */
698 memset(fis, 0, sizeof(fis));
699 fis[0] = 0x27; /* Host to device FIS. */
700 fis[1] = 1 << 7; /* Command FIS. */
701 /* Command byte (read/write). */
702 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
703
704 while (blocks) {
705 u16 now_blocks; /* number of blocks per iteration */
706 u32 transfer_size; /* number of bytes per iteration */
707
708 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
709
710 transfer_size = ATA_SECT_SIZE * now_blocks;
711 if (transfer_size > user_buffer_size) {
712 printf("scsi_ahci: Error: buffer too small.\n");
713 return -EIO;
714 }
715
716 /* LBA48 SATA command but only use 32bit address range within
717 * that. The next smaller command range (28bit) is too small.
718 */
719 fis[4] = (lba >> 0) & 0xff;
720 fis[5] = (lba >> 8) & 0xff;
721 fis[6] = (lba >> 16) & 0xff;
722 fis[7] = 1 << 6; /* device reg: set LBA mode */
723 fis[8] = ((lba >> 24) & 0xff);
724 fis[3] = 0xe0; /* features */
725
726 /* Block (sector) count */
727 fis[12] = (now_blocks >> 0) & 0xff;
728 fis[13] = (now_blocks >> 8) & 0xff;
729
730 /* Read/Write from ahci */
731 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
732 user_buffer, user_buffer_size,
733 is_write)) {
734 debug("scsi_ahci: SCSI %s10 command failure.\n",
735 is_write ? "WRITE" : "READ");
736 return -EIO;
737 }
738
739 /* If this transaction is a write, do a following flush.
740 * Writes in u-boot are so rare, and the logic to know when is
741 * the last write and do a flush only there is sufficiently
742 * difficult. Just do a flush after every write. This incurs,
743 * usually, one extra flush when the rare writes do happen.
744 */
745 if (is_write) {
746 if (-EIO == ata_io_flush(pccb->target))
747 return -EIO;
748 }
749 user_buffer += transfer_size;
750 user_buffer_size -= transfer_size;
751 blocks -= now_blocks;
752 lba += now_blocks;
753 }
754
755 return 0;
756 }
757
758
759 /*
760 * SCSI READ CAPACITY10 command operation.
761 */
762 static int ata_scsiop_read_capacity10(ccb *pccb)
763 {
764 u32 cap;
765 u64 cap64;
766 u32 block_size;
767
768 if (!ataid[pccb->target]) {
769 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
770 "\tNo ATA info!\n"
771 "\tPlease run SCSI commmand INQUIRY firstly!\n");
772 return -EPERM;
773 }
774
775 cap64 = ata_id_n_sectors(ataid[pccb->target]);
776 if (cap64 > 0x100000000ULL)
777 cap64 = 0xffffffff;
778
779 cap = cpu_to_be32(cap64);
780 memcpy(pccb->pdata, &cap, sizeof(cap));
781
782 block_size = cpu_to_be32((u32)512);
783 memcpy(&pccb->pdata[4], &block_size, 4);
784
785 return 0;
786 }
787
788
789 /*
790 * SCSI READ CAPACITY16 command operation.
791 */
792 static int ata_scsiop_read_capacity16(ccb *pccb)
793 {
794 u64 cap;
795 u64 block_size;
796
797 if (!ataid[pccb->target]) {
798 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
799 "\tNo ATA info!\n"
800 "\tPlease run SCSI commmand INQUIRY firstly!\n");
801 return -EPERM;
802 }
803
804 cap = ata_id_n_sectors(ataid[pccb->target]);
805 cap = cpu_to_be64(cap);
806 memcpy(pccb->pdata, &cap, sizeof(cap));
807
808 block_size = cpu_to_be64((u64)512);
809 memcpy(&pccb->pdata[8], &block_size, 8);
810
811 return 0;
812 }
813
814
815 /*
816 * SCSI TEST UNIT READY command operation.
817 */
818 static int ata_scsiop_test_unit_ready(ccb *pccb)
819 {
820 return (ataid[pccb->target]) ? 0 : -EPERM;
821 }
822
823
824 int scsi_exec(ccb *pccb)
825 {
826 int ret;
827
828 switch (pccb->cmd[0]) {
829 case SCSI_READ10:
830 ret = ata_scsiop_read_write(pccb, 0);
831 break;
832 case SCSI_WRITE10:
833 ret = ata_scsiop_read_write(pccb, 1);
834 break;
835 case SCSI_RD_CAPAC10:
836 ret = ata_scsiop_read_capacity10(pccb);
837 break;
838 case SCSI_RD_CAPAC16:
839 ret = ata_scsiop_read_capacity16(pccb);
840 break;
841 case SCSI_TST_U_RDY:
842 ret = ata_scsiop_test_unit_ready(pccb);
843 break;
844 case SCSI_INQUIRY:
845 ret = ata_scsiop_inquiry(pccb);
846 break;
847 default:
848 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
849 return false;
850 }
851
852 if (ret) {
853 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
854 return false;
855 }
856 return true;
857
858 }
859
860
861 void scsi_low_level_init(int busdevfunc)
862 {
863 int i;
864 u32 linkmap;
865
866 #ifndef CONFIG_SCSI_AHCI_PLAT
867 ahci_init_one(busdevfunc);
868 #endif
869
870 linkmap = probe_ent->link_port_map;
871
872 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
873 if (((linkmap >> i) & 0x01)) {
874 if (ahci_port_start((u8) i)) {
875 printf("Can not start port %d\n", i);
876 continue;
877 }
878 #ifdef CONFIG_AHCI_SETFEATURES_XFER
879 ahci_set_feature((u8) i);
880 #endif
881 }
882 }
883 }
884
885 #ifdef CONFIG_SCSI_AHCI_PLAT
886 int ahci_init(u32 base)
887 {
888 int i, rc = 0;
889 u32 linkmap;
890
891 probe_ent = malloc(sizeof(struct ahci_probe_ent));
892 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
893
894 probe_ent->host_flags = ATA_FLAG_SATA
895 | ATA_FLAG_NO_LEGACY
896 | ATA_FLAG_MMIO
897 | ATA_FLAG_PIO_DMA
898 | ATA_FLAG_NO_ATAPI;
899 probe_ent->pio_mask = 0x1f;
900 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
901
902 probe_ent->mmio_base = base;
903
904 /* initialize adapter */
905 rc = ahci_host_init(probe_ent);
906 if (rc)
907 goto err_out;
908
909 ahci_print_info(probe_ent);
910
911 linkmap = probe_ent->link_port_map;
912
913 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
914 if (((linkmap >> i) & 0x01)) {
915 if (ahci_port_start((u8) i)) {
916 printf("Can not start port %d\n", i);
917 continue;
918 }
919 #ifdef CONFIG_AHCI_SETFEATURES_XFER
920 ahci_set_feature((u8) i);
921 #endif
922 }
923 }
924 err_out:
925 return rc;
926 }
927 #endif
928
929 /*
930 * In the general case of generic rotating media it makes sense to have a
931 * flush capability. It probably even makes sense in the case of SSDs because
932 * one cannot always know for sure what kind of internal cache/flush mechanism
933 * is embodied therein. At first it was planned to invoke this after the last
934 * write to disk and before rebooting. In practice, knowing, a priori, which
935 * is the last write is difficult. Because writing to the disk in u-boot is
936 * very rare, this flush command will be invoked after every block write.
937 */
938 static int ata_io_flush(u8 port)
939 {
940 u8 fis[20];
941 struct ahci_ioports *pp = &(probe_ent->port[port]);
942 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
943 u32 cmd_fis_len = 5; /* five dwords */
944
945 /* Preset the FIS */
946 memset(fis, 0, 20);
947 fis[0] = 0x27; /* Host to device FIS. */
948 fis[1] = 1 << 7; /* Command FIS. */
949 fis[2] = ATA_CMD_FLUSH_EXT;
950
951 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
952 ahci_fill_cmd_slot(pp, cmd_fis_len);
953 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
954
955 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
956 WAIT_MS_FLUSH, 0x1)) {
957 debug("scsi_ahci: flush command timeout on port %d.\n", port);
958 return -EIO;
959 }
960
961 return 0;
962 }
963
964
965 void scsi_bus_reset(void)
966 {
967 /*Not implement*/
968 }
969
970
971 void scsi_print_error(ccb * pccb)
972 {
973 /*The ahci error info can be read in the ahci driver*/
974 }
"Das U-Boot" Source Tree