2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference on libata and ahci drvier in kernel
14 #include <asm/processor.h>
15 #include <asm/errno.h>
20 #include <linux/ctype.h>
23 static int ata_io_flush(u8 port
);
25 struct ahci_probe_ent
*probe_ent
= NULL
;
26 u16
*ataid
[AHCI_MAX_PORTS
];
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 20000
42 #define WAIT_MS_DATAIO 5000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 200
46 static inline u32
ahci_port_base(u32 base
, u32 port
)
48 return base
+ 0x100 + (port
* 0x80);
52 static void ahci_setup_port(struct ahci_ioports
*port
, unsigned long base
,
53 unsigned int port_idx
)
55 base
= ahci_port_base(base
, port_idx
);
57 port
->cmd_addr
= base
;
58 port
->scr_addr
= base
+ PORT_SCR
;
62 #define msleep(a) udelay(a * 1000)
64 static void ahci_dcache_flush_range(unsigned begin
, unsigned len
)
66 const unsigned long start
= begin
;
67 const unsigned long end
= start
+ len
;
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
70 flush_dcache_range(start
, end
);
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
78 static void ahci_dcache_invalidate_range(unsigned begin
, unsigned len
)
80 const unsigned long start
= begin
;
81 const unsigned long end
= start
+ len
;
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
84 invalidate_dcache_range(start
, end
);
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports
*pp
)
93 ahci_dcache_flush_range((unsigned long)pp
->cmd_slot
,
94 AHCI_PORT_PRIV_DMA_SZ
);
97 static int waiting_for_cmd_completed(volatile u8
*offset
,
104 for (i
= 0; ((status
= readl(offset
)) & sign
) && i
< timeout_msec
; i
++)
107 return (i
< timeout_msec
) ? 0 : -1;
110 int __weak
ahci_link_up(struct ahci_probe_ent
*probe_ent
, u8 port
)
114 u8
*port_mmio
= (u8
*)probe_ent
->port
[port
].port_mmio
;
117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
121 while (j
< WAIT_MS_LINKUP
) {
122 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
123 tmp
&= PORT_SCR_STAT_DET_MASK
;
124 if (tmp
== PORT_SCR_STAT_DET_PHYRDY
)
132 #ifdef CONFIG_SUNXI_AHCI
133 /* The sunxi AHCI controller requires this undocumented setup */
134 static void sunxi_dma_init(volatile u8
*port_mmio
)
136 clrsetbits_le32(port_mmio
+ PORT_P0DMACR
, 0x0000ff00, 0x00004400);
140 int ahci_reset(u32 base
)
143 u32 host_ctl_reg
= base
+ HOST_CTL
;
144 u32 tmp
= readl(host_ctl_reg
); /* global controller reset */
146 if ((tmp
& HOST_RESET
) == 0)
147 writel_with_flush(tmp
| HOST_RESET
, host_ctl_reg
);
150 * reset must complete within 1 second, or
151 * the hardware should be considered fried.
155 tmp
= readl(host_ctl_reg
);
157 } while ((i
> 0) && (tmp
& HOST_RESET
));
160 printf("controller reset failed (0x%x)\n", tmp
);
167 static int ahci_host_init(struct ahci_probe_ent
*probe_ent
)
169 #ifndef CONFIG_SCSI_AHCI_PLAT
170 pci_dev_t pdev
= probe_ent
->dev
;
172 unsigned short vendor
;
174 volatile u8
*mmio
= (volatile u8
*)probe_ent
->mmio_base
;
175 u32 tmp
, cap_save
, cmd
;
177 volatile u8
*port_mmio
;
180 debug("ahci_host_init: start\n");
182 cap_save
= readl(mmio
+ HOST_CAP
);
183 cap_save
&= ((1 << 28) | (1 << 17));
184 cap_save
|= (1 << 27); /* Staggered Spin-up. Not needed. */
186 ret
= ahci_reset(probe_ent
->mmio_base
);
190 writel_with_flush(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
191 writel(cap_save
, mmio
+ HOST_CAP
);
192 writel_with_flush(0xf, mmio
+ HOST_PORTS_IMPL
);
194 #ifndef CONFIG_SCSI_AHCI_PLAT
195 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
197 if (vendor
== PCI_VENDOR_ID_INTEL
) {
199 pci_read_config_word(pdev
, 0x92, &tmp16
);
201 pci_write_config_word(pdev
, 0x92, tmp16
);
204 probe_ent
->cap
= readl(mmio
+ HOST_CAP
);
205 probe_ent
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
206 port_map
= probe_ent
->port_map
;
207 probe_ent
->n_ports
= (probe_ent
->cap
& 0x1f) + 1;
209 debug("cap 0x%x port_map 0x%x n_ports %d\n",
210 probe_ent
->cap
, probe_ent
->port_map
, probe_ent
->n_ports
);
212 if (probe_ent
->n_ports
> CONFIG_SYS_SCSI_MAX_SCSI_ID
)
213 probe_ent
->n_ports
= CONFIG_SYS_SCSI_MAX_SCSI_ID
;
215 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
216 if (!(port_map
& (1 << i
)))
218 probe_ent
->port
[i
].port_mmio
= ahci_port_base((u32
) mmio
, i
);
219 port_mmio
= (u8
*) probe_ent
->port
[i
].port_mmio
;
220 ahci_setup_port(&probe_ent
->port
[i
], (unsigned long)mmio
, i
);
222 /* make sure port is not active */
223 tmp
= readl(port_mmio
+ PORT_CMD
);
224 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
225 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
226 debug("Port %d is active. Deactivating.\n", i
);
227 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
228 PORT_CMD_FIS_RX
| PORT_CMD_START
);
229 writel_with_flush(tmp
, port_mmio
+ PORT_CMD
);
231 /* spec says 500 msecs for each bit, so
232 * this is slightly incorrect.
237 #ifdef CONFIG_SUNXI_AHCI
238 sunxi_dma_init(port_mmio
);
241 /* Add the spinup command to whatever mode bits may
242 * already be on in the command register.
244 cmd
= readl(port_mmio
+ PORT_CMD
);
245 cmd
|= PORT_CMD_SPIN_UP
;
246 writel_with_flush(cmd
, port_mmio
+ PORT_CMD
);
248 /* Bring up SATA link. */
249 ret
= ahci_link_up(probe_ent
, i
);
251 printf("SATA link %d timeout.\n", i
);
254 debug("SATA link ok.\n");
257 /* Clear error status */
258 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
260 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
262 debug("Spinning up device on SATA port %d... ", i
);
265 while (j
< WAIT_MS_SPINUP
) {
266 tmp
= readl(port_mmio
+ PORT_TFDATA
);
267 if (!(tmp
& (ATA_BUSY
| ATA_DRQ
)))
270 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
271 tmp
&= PORT_SCR_STAT_DET_MASK
;
272 if (tmp
== PORT_SCR_STAT_DET_PHYRDY
)
277 tmp
= readl(port_mmio
+ PORT_SCR_STAT
) & PORT_SCR_STAT_DET_MASK
;
278 if (tmp
== PORT_SCR_STAT_DET_COMINIT
) {
279 debug("SATA link %d down (COMINIT received), retrying...\n", i
);
284 printf("Target spinup took %d ms.\n", j
);
285 if (j
== WAIT_MS_SPINUP
)
290 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
291 debug("PORT_SCR_ERR 0x%x\n", tmp
);
292 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
294 /* ack any pending irq events for this port */
295 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
296 debug("PORT_IRQ_STAT 0x%x\n", tmp
);
298 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
300 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
302 /* set irq mask (enables interrupts) */
303 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
305 /* register linkup ports */
306 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
307 debug("SATA port %d status: 0x%x\n", i
, tmp
);
308 if ((tmp
& PORT_SCR_STAT_DET_MASK
) == PORT_SCR_STAT_DET_PHYRDY
)
309 probe_ent
->link_port_map
|= (0x01 << i
);
312 tmp
= readl(mmio
+ HOST_CTL
);
313 debug("HOST_CTL 0x%x\n", tmp
);
314 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
315 tmp
= readl(mmio
+ HOST_CTL
);
316 debug("HOST_CTL 0x%x\n", tmp
);
317 #ifndef CONFIG_SCSI_AHCI_PLAT
318 pci_read_config_word(pdev
, PCI_COMMAND
, &tmp16
);
319 tmp
|= PCI_COMMAND_MASTER
;
320 pci_write_config_word(pdev
, PCI_COMMAND
, tmp16
);
326 static void ahci_print_info(struct ahci_probe_ent
*probe_ent
)
328 #ifndef CONFIG_SCSI_AHCI_PLAT
329 pci_dev_t pdev
= probe_ent
->dev
;
332 volatile u8
*mmio
= (volatile u8
*)probe_ent
->mmio_base
;
333 u32 vers
, cap
, cap2
, impl
, speed
;
337 vers
= readl(mmio
+ HOST_VERSION
);
338 cap
= probe_ent
->cap
;
339 cap2
= readl(mmio
+ HOST_CAP2
);
340 impl
= probe_ent
->port_map
;
342 speed
= (cap
>> 20) & 0xf;
352 #ifdef CONFIG_SCSI_AHCI_PLAT
355 pci_read_config_word(pdev
, 0x0a, &cc
);
358 else if (cc
== 0x0106)
360 else if (cc
== 0x0104)
365 printf("AHCI %02x%02x.%02x%02x "
366 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
371 ((cap
>> 8) & 0x1f) + 1, (cap
& 0x1f) + 1, speed_s
, impl
, scc_s
);
377 cap
& (1 << 31) ? "64bit " : "",
378 cap
& (1 << 30) ? "ncq " : "",
379 cap
& (1 << 28) ? "ilck " : "",
380 cap
& (1 << 27) ? "stag " : "",
381 cap
& (1 << 26) ? "pm " : "",
382 cap
& (1 << 25) ? "led " : "",
383 cap
& (1 << 24) ? "clo " : "",
384 cap
& (1 << 19) ? "nz " : "",
385 cap
& (1 << 18) ? "only " : "",
386 cap
& (1 << 17) ? "pmp " : "",
387 cap
& (1 << 16) ? "fbss " : "",
388 cap
& (1 << 15) ? "pio " : "",
389 cap
& (1 << 14) ? "slum " : "",
390 cap
& (1 << 13) ? "part " : "",
391 cap
& (1 << 7) ? "ccc " : "",
392 cap
& (1 << 6) ? "ems " : "",
393 cap
& (1 << 5) ? "sxs " : "",
394 cap2
& (1 << 2) ? "apst " : "",
395 cap2
& (1 << 1) ? "nvmp " : "",
396 cap2
& (1 << 0) ? "boh " : "");
399 #ifndef CONFIG_SCSI_AHCI_PLAT
400 static int ahci_init_one(pci_dev_t pdev
)
405 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
407 printf("%s: No memory for probe_ent\n", __func__
);
411 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
412 probe_ent
->dev
= pdev
;
414 probe_ent
->host_flags
= ATA_FLAG_SATA
419 probe_ent
->pio_mask
= 0x1f;
420 probe_ent
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
422 pci_read_config_dword(pdev
, PCI_BASE_ADDRESS_5
, &probe_ent
->mmio_base
);
423 debug("ahci mmio_base=0x%08x\n", probe_ent
->mmio_base
);
426 * JMicron-specific fixup:
427 * make sure we're in AHCI mode
429 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
430 if (vendor
== 0x197b)
431 pci_write_config_byte(pdev
, 0x41, 0xa1);
433 /* initialize adapter */
434 rc
= ahci_host_init(probe_ent
);
438 ahci_print_info(probe_ent
);
447 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
449 static int ahci_fill_sg(u8 port
, unsigned char *buf
, int buf_len
)
451 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
452 struct ahci_sg
*ahci_sg
= pp
->cmd_tbl_sg
;
456 sg_count
= ((buf_len
- 1) / MAX_DATA_BYTE_COUNT
) + 1;
457 if (sg_count
> AHCI_MAX_SG
) {
458 printf("Error:Too much sg!\n");
462 for (i
= 0; i
< sg_count
; i
++) {
464 cpu_to_le32((u32
) buf
+ i
* MAX_DATA_BYTE_COUNT
);
465 ahci_sg
->addr_hi
= 0;
466 ahci_sg
->flags_size
= cpu_to_le32(0x3fffff &
467 (buf_len
< MAX_DATA_BYTE_COUNT
469 : (MAX_DATA_BYTE_COUNT
- 1)));
471 buf_len
-= MAX_DATA_BYTE_COUNT
;
478 static void ahci_fill_cmd_slot(struct ahci_ioports
*pp
, u32 opts
)
480 pp
->cmd_slot
->opts
= cpu_to_le32(opts
);
481 pp
->cmd_slot
->status
= 0;
482 pp
->cmd_slot
->tbl_addr
= cpu_to_le32(pp
->cmd_tbl
& 0xffffffff);
483 pp
->cmd_slot
->tbl_addr_hi
= 0;
487 #ifdef CONFIG_AHCI_SETFEATURES_XFER
488 static void ahci_set_feature(u8 port
)
490 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
491 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
492 u32 cmd_fis_len
= 5; /* five dwords */
496 memset(fis
, 0, sizeof(fis
));
499 fis
[2] = ATA_CMD_SET_FEATURES
;
500 fis
[3] = SETFEATURES_XFER
;
501 fis
[12] = __ilog2(probe_ent
->udma_mask
+ 1) + 0x40 - 0x01;
503 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, sizeof(fis
));
504 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
505 ahci_dcache_flush_sata_cmd(pp
);
506 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
507 readl(port_mmio
+ PORT_CMD_ISSUE
);
509 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
510 WAIT_MS_DATAIO
, 0x1)) {
511 printf("set feature error on port %d!\n", port
);
517 static int ahci_port_start(u8 port
)
519 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
520 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
524 debug("Enter start port: %d\n", port
);
525 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
526 debug("Port %d status: %x\n", port
, port_status
);
527 if ((port_status
& 0xf) != 0x03) {
528 printf("No Link on this port!\n");
532 mem
= (u32
) malloc(AHCI_PORT_PRIV_DMA_SZ
+ 2048);
535 printf("%s: No mem for table!\n", __func__
);
539 mem
= (mem
+ 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
540 memset((u8
*) mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
543 * First item in chunk of DMA memory: 32-slot command table,
544 * 32 bytes each in size
547 (struct ahci_cmd_hdr
*)(uintptr_t)virt_to_phys((void *)mem
);
548 debug("cmd_slot = 0x%x\n", (unsigned)pp
->cmd_slot
);
549 mem
+= (AHCI_CMD_SLOT_SZ
+ 224);
552 * Second item: Received-FIS area
554 pp
->rx_fis
= virt_to_phys((void *)mem
);
555 mem
+= AHCI_RX_FIS_SZ
;
558 * Third item: data area for storing a single command
559 * and its scatter-gather table
561 pp
->cmd_tbl
= virt_to_phys((void *)mem
);
562 debug("cmd_tbl_dma = 0x%x\n", pp
->cmd_tbl
);
564 mem
+= AHCI_CMD_TBL_HDR
;
566 (struct ahci_sg
*)(uintptr_t)virt_to_phys((void *)mem
);
568 writel_with_flush((u32
) pp
->cmd_slot
, port_mmio
+ PORT_LST_ADDR
);
570 writel_with_flush(pp
->rx_fis
, port_mmio
+ PORT_FIS_ADDR
);
572 #ifdef CONFIG_SUNXI_AHCI
573 sunxi_dma_init(port_mmio
);
576 writel_with_flush(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
577 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
578 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
580 debug("Exit start port %d\n", port
);
586 static int ahci_device_data_io(u8 port
, u8
*fis
, int fis_len
, u8
*buf
,
587 int buf_len
, u8 is_write
)
590 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
591 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
596 debug("Enter %s: for port %d\n", __func__
, port
);
598 if (port
> probe_ent
->n_ports
) {
599 printf("Invalid port number %d\n", port
);
603 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
604 if ((port_status
& 0xf) != 0x03) {
605 debug("No Link on port %d!\n", port
);
609 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, fis_len
);
611 sg_count
= ahci_fill_sg(port
, buf
, buf_len
);
612 opts
= (fis_len
>> 2) | (sg_count
<< 16) | (is_write
<< 6);
613 ahci_fill_cmd_slot(pp
, opts
);
615 ahci_dcache_flush_sata_cmd(pp
);
616 ahci_dcache_flush_range((unsigned)buf
, (unsigned)buf_len
);
618 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
620 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
621 WAIT_MS_DATAIO
, 0x1)) {
622 printf("timeout exit!\n");
626 ahci_dcache_invalidate_range((unsigned)buf
, (unsigned)buf_len
);
627 debug("%s: %d byte transferred.\n", __func__
, pp
->cmd_slot
->status
);
633 static char *ata_id_strcpy(u16
*target
, u16
*src
, int len
)
636 for (i
= 0; i
< len
/ 2; i
++)
637 target
[i
] = swab16(src
[i
]);
638 return (char *)target
;
642 * SCSI INQUIRY command operation.
644 static int ata_scsiop_inquiry(ccb
*pccb
)
646 static const u8 hdr
[] = {
649 0x5, /* claim SPC-3 version compatibility */
655 ALLOC_CACHE_ALIGN_BUFFER(u16
, tmpid
, ATA_ID_WORDS
);
658 /* Clean ccb data buffer */
659 memset(pccb
->pdata
, 0, pccb
->datalen
);
661 memcpy(pccb
->pdata
, hdr
, sizeof(hdr
));
663 if (pccb
->datalen
<= 35)
666 memset(fis
, 0, sizeof(fis
));
667 /* Construct the FIS */
668 fis
[0] = 0x27; /* Host to device FIS. */
669 fis
[1] = 1 << 7; /* Command FIS. */
670 fis
[2] = ATA_CMD_ID_ATA
; /* Command byte. */
672 /* Read id from sata */
675 if (ahci_device_data_io(port
, (u8
*) &fis
, sizeof(fis
), (u8
*)tmpid
,
676 ATA_ID_WORDS
* 2, 0)) {
677 debug("scsi_ahci: SCSI inquiry command failure.\n");
682 ataid
[port
] = malloc(ATA_ID_WORDS
* 2);
684 printf("%s: No memory for ataid[port]\n", __func__
);
691 memcpy(idbuf
, tmpid
, ATA_ID_WORDS
* 2);
692 ata_swap_buf_le16(idbuf
, ATA_ID_WORDS
);
694 memcpy(&pccb
->pdata
[8], "ATA ", 8);
695 ata_id_strcpy((u16
*)&pccb
->pdata
[16], &idbuf
[ATA_ID_PROD
], 16);
696 ata_id_strcpy((u16
*)&pccb
->pdata
[32], &idbuf
[ATA_ID_FW_REV
], 4);
706 * SCSI READ10/WRITE10 command operation.
708 static int ata_scsiop_read_write(ccb
*pccb
, u8 is_write
)
713 u8
*user_buffer
= pccb
->pdata
;
714 u32 user_buffer_size
= pccb
->datalen
;
716 /* Retrieve the base LBA number from the ccb structure. */
717 memcpy(&lba
, pccb
->cmd
+ 2, sizeof(lba
));
718 lba
= be32_to_cpu(lba
);
721 * And the number of blocks.
723 * For 10-byte and 16-byte SCSI R/W commands, transfer
724 * length 0 means transfer 0 block of data.
725 * However, for ATA R/W commands, sector count 0 means
726 * 256 or 65536 sectors, not 0 sectors as in SCSI.
728 * WARNING: one or two older ATA drives treat 0 as 0...
730 blocks
= (((u16
)pccb
->cmd
[7]) << 8) | ((u16
) pccb
->cmd
[8]);
732 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
733 is_write
? "write" : "read", (unsigned)lba
, blocks
);
736 memset(fis
, 0, sizeof(fis
));
737 fis
[0] = 0x27; /* Host to device FIS. */
738 fis
[1] = 1 << 7; /* Command FIS. */
739 /* Command byte (read/write). */
740 fis
[2] = is_write
? ATA_CMD_WRITE_EXT
: ATA_CMD_READ_EXT
;
743 u16 now_blocks
; /* number of blocks per iteration */
744 u32 transfer_size
; /* number of bytes per iteration */
746 now_blocks
= min((u16
)MAX_SATA_BLOCKS_READ_WRITE
, blocks
);
748 transfer_size
= ATA_SECT_SIZE
* now_blocks
;
749 if (transfer_size
> user_buffer_size
) {
750 printf("scsi_ahci: Error: buffer too small.\n");
754 /* LBA48 SATA command but only use 32bit address range within
755 * that. The next smaller command range (28bit) is too small.
757 fis
[4] = (lba
>> 0) & 0xff;
758 fis
[5] = (lba
>> 8) & 0xff;
759 fis
[6] = (lba
>> 16) & 0xff;
760 fis
[7] = 1 << 6; /* device reg: set LBA mode */
761 fis
[8] = ((lba
>> 24) & 0xff);
762 fis
[3] = 0xe0; /* features */
764 /* Block (sector) count */
765 fis
[12] = (now_blocks
>> 0) & 0xff;
766 fis
[13] = (now_blocks
>> 8) & 0xff;
768 /* Read/Write from ahci */
769 if (ahci_device_data_io(pccb
->target
, (u8
*) &fis
, sizeof(fis
),
770 user_buffer
, user_buffer_size
,
772 debug("scsi_ahci: SCSI %s10 command failure.\n",
773 is_write
? "WRITE" : "READ");
777 /* If this transaction is a write, do a following flush.
778 * Writes in u-boot are so rare, and the logic to know when is
779 * the last write and do a flush only there is sufficiently
780 * difficult. Just do a flush after every write. This incurs,
781 * usually, one extra flush when the rare writes do happen.
784 if (-EIO
== ata_io_flush(pccb
->target
))
787 user_buffer
+= transfer_size
;
788 user_buffer_size
-= transfer_size
;
789 blocks
-= now_blocks
;
798 * SCSI READ CAPACITY10 command operation.
800 static int ata_scsiop_read_capacity10(ccb
*pccb
)
806 if (!ataid
[pccb
->target
]) {
807 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
809 "\tPlease run SCSI commmand INQUIRY firstly!\n");
813 cap64
= ata_id_n_sectors(ataid
[pccb
->target
]);
814 if (cap64
> 0x100000000ULL
)
817 cap
= cpu_to_be32(cap64
);
818 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
820 block_size
= cpu_to_be32((u32
)512);
821 memcpy(&pccb
->pdata
[4], &block_size
, 4);
828 * SCSI READ CAPACITY16 command operation.
830 static int ata_scsiop_read_capacity16(ccb
*pccb
)
835 if (!ataid
[pccb
->target
]) {
836 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
838 "\tPlease run SCSI commmand INQUIRY firstly!\n");
842 cap
= ata_id_n_sectors(ataid
[pccb
->target
]);
843 cap
= cpu_to_be64(cap
);
844 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
846 block_size
= cpu_to_be64((u64
)512);
847 memcpy(&pccb
->pdata
[8], &block_size
, 8);
854 * SCSI TEST UNIT READY command operation.
856 static int ata_scsiop_test_unit_ready(ccb
*pccb
)
858 return (ataid
[pccb
->target
]) ? 0 : -EPERM
;
862 int scsi_exec(ccb
*pccb
)
866 switch (pccb
->cmd
[0]) {
868 ret
= ata_scsiop_read_write(pccb
, 0);
871 ret
= ata_scsiop_read_write(pccb
, 1);
873 case SCSI_RD_CAPAC10
:
874 ret
= ata_scsiop_read_capacity10(pccb
);
876 case SCSI_RD_CAPAC16
:
877 ret
= ata_scsiop_read_capacity16(pccb
);
880 ret
= ata_scsiop_test_unit_ready(pccb
);
883 ret
= ata_scsiop_inquiry(pccb
);
886 printf("Unsupport SCSI command 0x%02x\n", pccb
->cmd
[0]);
891 debug("SCSI command 0x%02x ret errno %d\n", pccb
->cmd
[0], ret
);
899 void scsi_low_level_init(int busdevfunc
)
904 #ifndef CONFIG_SCSI_AHCI_PLAT
905 ahci_init_one(busdevfunc
);
908 linkmap
= probe_ent
->link_port_map
;
910 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
911 if (((linkmap
>> i
) & 0x01)) {
912 if (ahci_port_start((u8
) i
)) {
913 printf("Can not start port %d\n", i
);
916 #ifdef CONFIG_AHCI_SETFEATURES_XFER
917 ahci_set_feature((u8
) i
);
923 #ifdef CONFIG_SCSI_AHCI_PLAT
924 int ahci_init(u32 base
)
929 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
931 printf("%s: No memory for probe_ent\n", __func__
);
935 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
937 probe_ent
->host_flags
= ATA_FLAG_SATA
942 probe_ent
->pio_mask
= 0x1f;
943 probe_ent
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
945 probe_ent
->mmio_base
= base
;
947 /* initialize adapter */
948 rc
= ahci_host_init(probe_ent
);
952 ahci_print_info(probe_ent
);
954 linkmap
= probe_ent
->link_port_map
;
956 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
957 if (((linkmap
>> i
) & 0x01)) {
958 if (ahci_port_start((u8
) i
)) {
959 printf("Can not start port %d\n", i
);
962 #ifdef CONFIG_AHCI_SETFEATURES_XFER
963 ahci_set_feature((u8
) i
);
971 void __weak
scsi_init(void)
978 * In the general case of generic rotating media it makes sense to have a
979 * flush capability. It probably even makes sense in the case of SSDs because
980 * one cannot always know for sure what kind of internal cache/flush mechanism
981 * is embodied therein. At first it was planned to invoke this after the last
982 * write to disk and before rebooting. In practice, knowing, a priori, which
983 * is the last write is difficult. Because writing to the disk in u-boot is
984 * very rare, this flush command will be invoked after every block write.
986 static int ata_io_flush(u8 port
)
989 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
990 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
991 u32 cmd_fis_len
= 5; /* five dwords */
995 fis
[0] = 0x27; /* Host to device FIS. */
996 fis
[1] = 1 << 7; /* Command FIS. */
997 fis
[2] = ATA_CMD_FLUSH_EXT
;
999 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, 20);
1000 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
1001 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
1003 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
1004 WAIT_MS_FLUSH
, 0x1)) {
1005 debug("scsi_ahci: flush command timeout on port %d.\n", port
);
1013 __weak
void scsi_bus_reset(void)
1018 void scsi_print_error(ccb
* pccb
)
1020 /*The ahci error info can be read in the ahci driver*/