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Merge branch 'master' of git://git.denx.de/u-boot
[people/ms/u-boot.git] / drivers / block / ahci.c
1 /*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * with the reference on libata and ahci drvier in kernel
9 */
10 #include <common.h>
11
12 #include <command.h>
13 #include <pci.h>
14 #include <asm/processor.h>
15 #include <asm/errno.h>
16 #include <asm/io.h>
17 #include <malloc.h>
18 #include <scsi.h>
19 #include <libata.h>
20 #include <linux/ctype.h>
21 #include <ahci.h>
22
23 static int ata_io_flush(u8 port);
24
25 struct ahci_probe_ent *probe_ent = NULL;
26 u16 *ataid[AHCI_MAX_PORTS];
27
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
29
30 /*
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
34 * needed.
35 */
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
38 #endif
39
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 20000
42 #define WAIT_MS_DATAIO 10000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 200
45
46 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
47 {
48 return base + 0x100 + (port * 0x80);
49 }
50
51
52 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
53 unsigned int port_idx)
54 {
55 base = ahci_port_base(base, port_idx);
56
57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
59 }
60
61
62 #define msleep(a) udelay(a * 1000)
63
64 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
65 {
66 const unsigned long start = begin;
67 const unsigned long end = start + len;
68
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end);
71 }
72
73 /*
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
76 * physical RAM.
77 */
78 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
79 {
80 const unsigned long start = begin;
81 const unsigned long end = start + len;
82
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end);
85 }
86
87 /*
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
90 */
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
92 {
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ);
95 }
96
97 static int waiting_for_cmd_completed(void __iomem *offset,
98 int timeout_msec,
99 u32 sign)
100 {
101 int i;
102 u32 status;
103
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
105 msleep(1);
106
107 return (i < timeout_msec) ? 0 : -1;
108 }
109
110 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
111 {
112 u32 tmp;
113 int j = 0;
114 void __iomem *port_mmio = probe_ent->port[port].port_mmio;
115
116 /*
117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
120 */
121 while (j < WAIT_MS_LINKUP) {
122 tmp = readl(port_mmio + PORT_SCR_STAT);
123 tmp &= PORT_SCR_STAT_DET_MASK;
124 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
125 return 0;
126 udelay(1000);
127 j++;
128 }
129 return 1;
130 }
131
132 #ifdef CONFIG_SUNXI_AHCI
133 /* The sunxi AHCI controller requires this undocumented setup */
134 static void sunxi_dma_init(void __iomem *port_mmio)
135 {
136 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
137 }
138 #endif
139
140 int ahci_reset(void __iomem *base)
141 {
142 int i = 1000;
143 u32 __iomem *host_ctl_reg = base + HOST_CTL;
144 u32 tmp = readl(host_ctl_reg); /* global controller reset */
145
146 if ((tmp & HOST_RESET) == 0)
147 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
148
149 /*
150 * reset must complete within 1 second, or
151 * the hardware should be considered fried.
152 */
153 do {
154 udelay(1000);
155 tmp = readl(host_ctl_reg);
156 i--;
157 } while ((i > 0) && (tmp & HOST_RESET));
158
159 if (i == 0) {
160 printf("controller reset failed (0x%x)\n", tmp);
161 return -1;
162 }
163
164 return 0;
165 }
166
167 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
168 {
169 #ifndef CONFIG_SCSI_AHCI_PLAT
170 pci_dev_t pdev = probe_ent->dev;
171 u16 tmp16;
172 unsigned short vendor;
173 #endif
174 void __iomem *mmio = probe_ent->mmio_base;
175 u32 tmp, cap_save, cmd;
176 int i, j, ret;
177 void __iomem *port_mmio;
178 u32 port_map;
179
180 debug("ahci_host_init: start\n");
181
182 cap_save = readl(mmio + HOST_CAP);
183 cap_save &= ((1 << 28) | (1 << 17));
184 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
185
186 ret = ahci_reset(probe_ent->mmio_base);
187 if (ret)
188 return ret;
189
190 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
191 writel(cap_save, mmio + HOST_CAP);
192 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
193
194 #ifndef CONFIG_SCSI_AHCI_PLAT
195 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
196
197 if (vendor == PCI_VENDOR_ID_INTEL) {
198 u16 tmp16;
199 pci_read_config_word(pdev, 0x92, &tmp16);
200 tmp16 |= 0xf;
201 pci_write_config_word(pdev, 0x92, tmp16);
202 }
203 #endif
204 probe_ent->cap = readl(mmio + HOST_CAP);
205 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
206 port_map = probe_ent->port_map;
207 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
208
209 debug("cap 0x%x port_map 0x%x n_ports %d\n",
210 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
211
212 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
213 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
214
215 for (i = 0; i < probe_ent->n_ports; i++) {
216 if (!(port_map & (1 << i)))
217 continue;
218 probe_ent->port[i].port_mmio = ahci_port_base(mmio, i);
219 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
220 ahci_setup_port(&probe_ent->port[i], mmio, i);
221
222 /* make sure port is not active */
223 tmp = readl(port_mmio + PORT_CMD);
224 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
225 PORT_CMD_FIS_RX | PORT_CMD_START)) {
226 debug("Port %d is active. Deactivating.\n", i);
227 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
228 PORT_CMD_FIS_RX | PORT_CMD_START);
229 writel_with_flush(tmp, port_mmio + PORT_CMD);
230
231 /* spec says 500 msecs for each bit, so
232 * this is slightly incorrect.
233 */
234 msleep(500);
235 }
236
237 #ifdef CONFIG_SUNXI_AHCI
238 sunxi_dma_init(port_mmio);
239 #endif
240
241 /* Add the spinup command to whatever mode bits may
242 * already be on in the command register.
243 */
244 cmd = readl(port_mmio + PORT_CMD);
245 cmd |= PORT_CMD_SPIN_UP;
246 writel_with_flush(cmd, port_mmio + PORT_CMD);
247
248 /* Bring up SATA link. */
249 ret = ahci_link_up(probe_ent, i);
250 if (ret) {
251 printf("SATA link %d timeout.\n", i);
252 continue;
253 } else {
254 debug("SATA link ok.\n");
255 }
256
257 /* Clear error status */
258 tmp = readl(port_mmio + PORT_SCR_ERR);
259 if (tmp)
260 writel(tmp, port_mmio + PORT_SCR_ERR);
261
262 debug("Spinning up device on SATA port %d... ", i);
263
264 j = 0;
265 while (j < WAIT_MS_SPINUP) {
266 tmp = readl(port_mmio + PORT_TFDATA);
267 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
268 break;
269 udelay(1000);
270 tmp = readl(port_mmio + PORT_SCR_STAT);
271 tmp &= PORT_SCR_STAT_DET_MASK;
272 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
273 break;
274 j++;
275 }
276
277 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
278 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
279 debug("SATA link %d down (COMINIT received), retrying...\n", i);
280 i--;
281 continue;
282 }
283
284 printf("Target spinup took %d ms.\n", j);
285 if (j == WAIT_MS_SPINUP)
286 debug("timeout.\n");
287 else
288 debug("ok.\n");
289
290 tmp = readl(port_mmio + PORT_SCR_ERR);
291 debug("PORT_SCR_ERR 0x%x\n", tmp);
292 writel(tmp, port_mmio + PORT_SCR_ERR);
293
294 /* ack any pending irq events for this port */
295 tmp = readl(port_mmio + PORT_IRQ_STAT);
296 debug("PORT_IRQ_STAT 0x%x\n", tmp);
297 if (tmp)
298 writel(tmp, port_mmio + PORT_IRQ_STAT);
299
300 writel(1 << i, mmio + HOST_IRQ_STAT);
301
302 /* register linkup ports */
303 tmp = readl(port_mmio + PORT_SCR_STAT);
304 debug("SATA port %d status: 0x%x\n", i, tmp);
305 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
306 probe_ent->link_port_map |= (0x01 << i);
307 }
308
309 tmp = readl(mmio + HOST_CTL);
310 debug("HOST_CTL 0x%x\n", tmp);
311 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
312 tmp = readl(mmio + HOST_CTL);
313 debug("HOST_CTL 0x%x\n", tmp);
314 #ifndef CONFIG_SCSI_AHCI_PLAT
315 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
316 tmp |= PCI_COMMAND_MASTER;
317 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
318 #endif
319 return 0;
320 }
321
322
323 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
324 {
325 #ifndef CONFIG_SCSI_AHCI_PLAT
326 pci_dev_t pdev = probe_ent->dev;
327 u16 cc;
328 #endif
329 void __iomem *mmio = probe_ent->mmio_base;
330 u32 vers, cap, cap2, impl, speed;
331 const char *speed_s;
332 const char *scc_s;
333
334 vers = readl(mmio + HOST_VERSION);
335 cap = probe_ent->cap;
336 cap2 = readl(mmio + HOST_CAP2);
337 impl = probe_ent->port_map;
338
339 speed = (cap >> 20) & 0xf;
340 if (speed == 1)
341 speed_s = "1.5";
342 else if (speed == 2)
343 speed_s = "3";
344 else if (speed == 3)
345 speed_s = "6";
346 else
347 speed_s = "?";
348
349 #ifdef CONFIG_SCSI_AHCI_PLAT
350 scc_s = "SATA";
351 #else
352 pci_read_config_word(pdev, 0x0a, &cc);
353 if (cc == 0x0101)
354 scc_s = "IDE";
355 else if (cc == 0x0106)
356 scc_s = "SATA";
357 else if (cc == 0x0104)
358 scc_s = "RAID";
359 else
360 scc_s = "unknown";
361 #endif
362 printf("AHCI %02x%02x.%02x%02x "
363 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
364 (vers >> 24) & 0xff,
365 (vers >> 16) & 0xff,
366 (vers >> 8) & 0xff,
367 vers & 0xff,
368 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
369
370 printf("flags: "
371 "%s%s%s%s%s%s%s"
372 "%s%s%s%s%s%s%s"
373 "%s%s%s%s%s%s\n",
374 cap & (1 << 31) ? "64bit " : "",
375 cap & (1 << 30) ? "ncq " : "",
376 cap & (1 << 28) ? "ilck " : "",
377 cap & (1 << 27) ? "stag " : "",
378 cap & (1 << 26) ? "pm " : "",
379 cap & (1 << 25) ? "led " : "",
380 cap & (1 << 24) ? "clo " : "",
381 cap & (1 << 19) ? "nz " : "",
382 cap & (1 << 18) ? "only " : "",
383 cap & (1 << 17) ? "pmp " : "",
384 cap & (1 << 16) ? "fbss " : "",
385 cap & (1 << 15) ? "pio " : "",
386 cap & (1 << 14) ? "slum " : "",
387 cap & (1 << 13) ? "part " : "",
388 cap & (1 << 7) ? "ccc " : "",
389 cap & (1 << 6) ? "ems " : "",
390 cap & (1 << 5) ? "sxs " : "",
391 cap2 & (1 << 2) ? "apst " : "",
392 cap2 & (1 << 1) ? "nvmp " : "",
393 cap2 & (1 << 0) ? "boh " : "");
394 }
395
396 #ifndef CONFIG_SCSI_AHCI_PLAT
397 static int ahci_init_one(pci_dev_t pdev)
398 {
399 u16 vendor;
400 int rc;
401
402 probe_ent = malloc(sizeof(struct ahci_probe_ent));
403 if (!probe_ent) {
404 printf("%s: No memory for probe_ent\n", __func__);
405 return -ENOMEM;
406 }
407
408 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
409 probe_ent->dev = pdev;
410
411 probe_ent->host_flags = ATA_FLAG_SATA
412 | ATA_FLAG_NO_LEGACY
413 | ATA_FLAG_MMIO
414 | ATA_FLAG_PIO_DMA
415 | ATA_FLAG_NO_ATAPI;
416 probe_ent->pio_mask = 0x1f;
417 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
418
419 probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5,
420 PCI_REGION_MEM);
421 debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
422
423 /* Take from kernel:
424 * JMicron-specific fixup:
425 * make sure we're in AHCI mode
426 */
427 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
428 if (vendor == 0x197b)
429 pci_write_config_byte(pdev, 0x41, 0xa1);
430
431 /* initialize adapter */
432 rc = ahci_host_init(probe_ent);
433 if (rc)
434 goto err_out;
435
436 ahci_print_info(probe_ent);
437
438 return 0;
439
440 err_out:
441 return rc;
442 }
443 #endif
444
445 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
446
447 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
448 {
449 struct ahci_ioports *pp = &(probe_ent->port[port]);
450 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
451 u32 sg_count;
452 int i;
453
454 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
455 if (sg_count > AHCI_MAX_SG) {
456 printf("Error:Too much sg!\n");
457 return -1;
458 }
459
460 for (i = 0; i < sg_count; i++) {
461 ahci_sg->addr =
462 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
463 ahci_sg->addr_hi = 0;
464 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
465 (buf_len < MAX_DATA_BYTE_COUNT
466 ? (buf_len - 1)
467 : (MAX_DATA_BYTE_COUNT - 1)));
468 ahci_sg++;
469 buf_len -= MAX_DATA_BYTE_COUNT;
470 }
471
472 return sg_count;
473 }
474
475
476 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
477 {
478 pp->cmd_slot->opts = cpu_to_le32(opts);
479 pp->cmd_slot->status = 0;
480 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
481 #ifdef CONFIG_PHYS_64BIT
482 pp->cmd_slot->tbl_addr_hi =
483 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
484 #endif
485 }
486
487
488 #ifdef CONFIG_AHCI_SETFEATURES_XFER
489 static void ahci_set_feature(u8 port)
490 {
491 struct ahci_ioports *pp = &(probe_ent->port[port]);
492 void __iomem *port_mmio = pp->port_mmio;
493 u32 cmd_fis_len = 5; /* five dwords */
494 u8 fis[20];
495
496 /* set feature */
497 memset(fis, 0, sizeof(fis));
498 fis[0] = 0x27;
499 fis[1] = 1 << 7;
500 fis[2] = ATA_CMD_SET_FEATURES;
501 fis[3] = SETFEATURES_XFER;
502 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
503
504 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
505 ahci_fill_cmd_slot(pp, cmd_fis_len);
506 ahci_dcache_flush_sata_cmd(pp);
507 writel(1, port_mmio + PORT_CMD_ISSUE);
508 readl(port_mmio + PORT_CMD_ISSUE);
509
510 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
511 WAIT_MS_DATAIO, 0x1)) {
512 printf("set feature error on port %d!\n", port);
513 }
514 }
515 #endif
516
517 static int wait_spinup(void __iomem *port_mmio)
518 {
519 ulong start;
520 u32 tf_data;
521
522 start = get_timer(0);
523 do {
524 tf_data = readl(port_mmio + PORT_TFDATA);
525 if (!(tf_data & ATA_BUSY))
526 return 0;
527 } while (get_timer(start) < WAIT_MS_SPINUP);
528
529 return -ETIMEDOUT;
530 }
531
532 static int ahci_port_start(u8 port)
533 {
534 struct ahci_ioports *pp = &(probe_ent->port[port]);
535 void __iomem *port_mmio = pp->port_mmio;
536 u32 port_status;
537 void __iomem *mem;
538
539 debug("Enter start port: %d\n", port);
540 port_status = readl(port_mmio + PORT_SCR_STAT);
541 debug("Port %d status: %x\n", port, port_status);
542 if ((port_status & 0xf) != 0x03) {
543 printf("No Link on this port!\n");
544 return -1;
545 }
546
547 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
548 if (!mem) {
549 free(pp);
550 printf("%s: No mem for table!\n", __func__);
551 return -ENOMEM;
552 }
553
554 /* Aligned to 2048-bytes */
555 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
556 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
557
558 /*
559 * First item in chunk of DMA memory: 32-slot command table,
560 * 32 bytes each in size
561 */
562 pp->cmd_slot =
563 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
564 debug("cmd_slot = %p\n", pp->cmd_slot);
565 mem += (AHCI_CMD_SLOT_SZ + 224);
566
567 /*
568 * Second item: Received-FIS area
569 */
570 pp->rx_fis = virt_to_phys((void *)mem);
571 mem += AHCI_RX_FIS_SZ;
572
573 /*
574 * Third item: data area for storing a single command
575 * and its scatter-gather table
576 */
577 pp->cmd_tbl = virt_to_phys((void *)mem);
578 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
579
580 mem += AHCI_CMD_TBL_HDR;
581 pp->cmd_tbl_sg =
582 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
583
584 writel_with_flush((unsigned long)pp->cmd_slot,
585 port_mmio + PORT_LST_ADDR);
586
587 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
588
589 #ifdef CONFIG_SUNXI_AHCI
590 sunxi_dma_init(port_mmio);
591 #endif
592
593 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
594 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
595 PORT_CMD_START, port_mmio + PORT_CMD);
596
597 debug("Exit start port %d\n", port);
598
599 /*
600 * Make sure interface is not busy based on error and status
601 * information from task file data register before proceeding
602 */
603 return wait_spinup(port_mmio);
604 }
605
606
607 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
608 int buf_len, u8 is_write)
609 {
610
611 struct ahci_ioports *pp = &(probe_ent->port[port]);
612 void __iomem *port_mmio = pp->port_mmio;
613 u32 opts;
614 u32 port_status;
615 int sg_count;
616
617 debug("Enter %s: for port %d\n", __func__, port);
618
619 if (port > probe_ent->n_ports) {
620 printf("Invalid port number %d\n", port);
621 return -1;
622 }
623
624 port_status = readl(port_mmio + PORT_SCR_STAT);
625 if ((port_status & 0xf) != 0x03) {
626 debug("No Link on port %d!\n", port);
627 return -1;
628 }
629
630 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
631
632 sg_count = ahci_fill_sg(port, buf, buf_len);
633 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
634 ahci_fill_cmd_slot(pp, opts);
635
636 ahci_dcache_flush_sata_cmd(pp);
637 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
638
639 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
640
641 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
642 WAIT_MS_DATAIO, 0x1)) {
643 printf("timeout exit!\n");
644 return -1;
645 }
646
647 ahci_dcache_invalidate_range((unsigned long)buf,
648 (unsigned long)buf_len);
649 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
650
651 return 0;
652 }
653
654
655 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
656 {
657 int i;
658 for (i = 0; i < len / 2; i++)
659 target[i] = swab16(src[i]);
660 return (char *)target;
661 }
662
663 /*
664 * SCSI INQUIRY command operation.
665 */
666 static int ata_scsiop_inquiry(ccb *pccb)
667 {
668 static const u8 hdr[] = {
669 0,
670 0,
671 0x5, /* claim SPC-3 version compatibility */
672 2,
673 95 - 4,
674 };
675 u8 fis[20];
676 u16 *idbuf;
677 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
678 u8 port;
679
680 /* Clean ccb data buffer */
681 memset(pccb->pdata, 0, pccb->datalen);
682
683 memcpy(pccb->pdata, hdr, sizeof(hdr));
684
685 if (pccb->datalen <= 35)
686 return 0;
687
688 memset(fis, 0, sizeof(fis));
689 /* Construct the FIS */
690 fis[0] = 0x27; /* Host to device FIS. */
691 fis[1] = 1 << 7; /* Command FIS. */
692 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
693
694 /* Read id from sata */
695 port = pccb->target;
696
697 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
698 ATA_ID_WORDS * 2, 0)) {
699 debug("scsi_ahci: SCSI inquiry command failure.\n");
700 return -EIO;
701 }
702
703 if (!ataid[port]) {
704 ataid[port] = malloc(ATA_ID_WORDS * 2);
705 if (!ataid[port]) {
706 printf("%s: No memory for ataid[port]\n", __func__);
707 return -ENOMEM;
708 }
709 }
710
711 idbuf = ataid[port];
712
713 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
714 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
715
716 memcpy(&pccb->pdata[8], "ATA ", 8);
717 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
718 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
719
720 #ifdef DEBUG
721 ata_dump_id(idbuf);
722 #endif
723 return 0;
724 }
725
726
727 /*
728 * SCSI READ10/WRITE10 command operation.
729 */
730 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
731 {
732 lbaint_t lba = 0;
733 u16 blocks = 0;
734 u8 fis[20];
735 u8 *user_buffer = pccb->pdata;
736 u32 user_buffer_size = pccb->datalen;
737
738 /* Retrieve the base LBA number from the ccb structure. */
739 if (pccb->cmd[0] == SCSI_READ16) {
740 memcpy(&lba, pccb->cmd + 2, 8);
741 lba = be64_to_cpu(lba);
742 } else {
743 u32 temp;
744 memcpy(&temp, pccb->cmd + 2, 4);
745 lba = be32_to_cpu(temp);
746 }
747
748 /*
749 * Retrieve the base LBA number and the block count from
750 * the ccb structure.
751 *
752 * For 10-byte and 16-byte SCSI R/W commands, transfer
753 * length 0 means transfer 0 block of data.
754 * However, for ATA R/W commands, sector count 0 means
755 * 256 or 65536 sectors, not 0 sectors as in SCSI.
756 *
757 * WARNING: one or two older ATA drives treat 0 as 0...
758 */
759 if (pccb->cmd[0] == SCSI_READ16)
760 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
761 else
762 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
763
764 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
765 is_write ? "write" : "read", blocks, lba);
766
767 /* Preset the FIS */
768 memset(fis, 0, sizeof(fis));
769 fis[0] = 0x27; /* Host to device FIS. */
770 fis[1] = 1 << 7; /* Command FIS. */
771 /* Command byte (read/write). */
772 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
773
774 while (blocks) {
775 u16 now_blocks; /* number of blocks per iteration */
776 u32 transfer_size; /* number of bytes per iteration */
777
778 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
779
780 transfer_size = ATA_SECT_SIZE * now_blocks;
781 if (transfer_size > user_buffer_size) {
782 printf("scsi_ahci: Error: buffer too small.\n");
783 return -EIO;
784 }
785
786 /*
787 * LBA48 SATA command but only use 32bit address range within
788 * that (unless we've enabled 64bit LBA support). The next
789 * smaller command range (28bit) is too small.
790 */
791 fis[4] = (lba >> 0) & 0xff;
792 fis[5] = (lba >> 8) & 0xff;
793 fis[6] = (lba >> 16) & 0xff;
794 fis[7] = 1 << 6; /* device reg: set LBA mode */
795 fis[8] = ((lba >> 24) & 0xff);
796 #ifdef CONFIG_SYS_64BIT_LBA
797 if (pccb->cmd[0] == SCSI_READ16) {
798 fis[9] = ((lba >> 32) & 0xff);
799 fis[10] = ((lba >> 40) & 0xff);
800 }
801 #endif
802
803 fis[3] = 0xe0; /* features */
804
805 /* Block (sector) count */
806 fis[12] = (now_blocks >> 0) & 0xff;
807 fis[13] = (now_blocks >> 8) & 0xff;
808
809 /* Read/Write from ahci */
810 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
811 user_buffer, transfer_size,
812 is_write)) {
813 debug("scsi_ahci: SCSI %s10 command failure.\n",
814 is_write ? "WRITE" : "READ");
815 return -EIO;
816 }
817
818 /* If this transaction is a write, do a following flush.
819 * Writes in u-boot are so rare, and the logic to know when is
820 * the last write and do a flush only there is sufficiently
821 * difficult. Just do a flush after every write. This incurs,
822 * usually, one extra flush when the rare writes do happen.
823 */
824 if (is_write) {
825 if (-EIO == ata_io_flush(pccb->target))
826 return -EIO;
827 }
828 user_buffer += transfer_size;
829 user_buffer_size -= transfer_size;
830 blocks -= now_blocks;
831 lba += now_blocks;
832 }
833
834 return 0;
835 }
836
837
838 /*
839 * SCSI READ CAPACITY10 command operation.
840 */
841 static int ata_scsiop_read_capacity10(ccb *pccb)
842 {
843 u32 cap;
844 u64 cap64;
845 u32 block_size;
846
847 if (!ataid[pccb->target]) {
848 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
849 "\tNo ATA info!\n"
850 "\tPlease run SCSI commmand INQUIRY firstly!\n");
851 return -EPERM;
852 }
853
854 cap64 = ata_id_n_sectors(ataid[pccb->target]);
855 if (cap64 > 0x100000000ULL)
856 cap64 = 0xffffffff;
857
858 cap = cpu_to_be32(cap64);
859 memcpy(pccb->pdata, &cap, sizeof(cap));
860
861 block_size = cpu_to_be32((u32)512);
862 memcpy(&pccb->pdata[4], &block_size, 4);
863
864 return 0;
865 }
866
867
868 /*
869 * SCSI READ CAPACITY16 command operation.
870 */
871 static int ata_scsiop_read_capacity16(ccb *pccb)
872 {
873 u64 cap;
874 u64 block_size;
875
876 if (!ataid[pccb->target]) {
877 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
878 "\tNo ATA info!\n"
879 "\tPlease run SCSI commmand INQUIRY firstly!\n");
880 return -EPERM;
881 }
882
883 cap = ata_id_n_sectors(ataid[pccb->target]);
884 cap = cpu_to_be64(cap);
885 memcpy(pccb->pdata, &cap, sizeof(cap));
886
887 block_size = cpu_to_be64((u64)512);
888 memcpy(&pccb->pdata[8], &block_size, 8);
889
890 return 0;
891 }
892
893
894 /*
895 * SCSI TEST UNIT READY command operation.
896 */
897 static int ata_scsiop_test_unit_ready(ccb *pccb)
898 {
899 return (ataid[pccb->target]) ? 0 : -EPERM;
900 }
901
902
903 int scsi_exec(ccb *pccb)
904 {
905 int ret;
906
907 switch (pccb->cmd[0]) {
908 case SCSI_READ16:
909 case SCSI_READ10:
910 ret = ata_scsiop_read_write(pccb, 0);
911 break;
912 case SCSI_WRITE10:
913 ret = ata_scsiop_read_write(pccb, 1);
914 break;
915 case SCSI_RD_CAPAC10:
916 ret = ata_scsiop_read_capacity10(pccb);
917 break;
918 case SCSI_RD_CAPAC16:
919 ret = ata_scsiop_read_capacity16(pccb);
920 break;
921 case SCSI_TST_U_RDY:
922 ret = ata_scsiop_test_unit_ready(pccb);
923 break;
924 case SCSI_INQUIRY:
925 ret = ata_scsiop_inquiry(pccb);
926 break;
927 default:
928 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
929 return false;
930 }
931
932 if (ret) {
933 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
934 return false;
935 }
936 return true;
937
938 }
939
940
941 void scsi_low_level_init(int busdevfunc)
942 {
943 int i;
944 u32 linkmap;
945
946 #ifndef CONFIG_SCSI_AHCI_PLAT
947 ahci_init_one(busdevfunc);
948 #endif
949
950 linkmap = probe_ent->link_port_map;
951
952 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
953 if (((linkmap >> i) & 0x01)) {
954 if (ahci_port_start((u8) i)) {
955 printf("Can not start port %d\n", i);
956 continue;
957 }
958 #ifdef CONFIG_AHCI_SETFEATURES_XFER
959 ahci_set_feature((u8) i);
960 #endif
961 }
962 }
963 }
964
965 #ifdef CONFIG_SCSI_AHCI_PLAT
966 int ahci_init(void __iomem *base)
967 {
968 int i, rc = 0;
969 u32 linkmap;
970
971 probe_ent = malloc(sizeof(struct ahci_probe_ent));
972 if (!probe_ent) {
973 printf("%s: No memory for probe_ent\n", __func__);
974 return -ENOMEM;
975 }
976
977 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
978
979 probe_ent->host_flags = ATA_FLAG_SATA
980 | ATA_FLAG_NO_LEGACY
981 | ATA_FLAG_MMIO
982 | ATA_FLAG_PIO_DMA
983 | ATA_FLAG_NO_ATAPI;
984 probe_ent->pio_mask = 0x1f;
985 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
986
987 probe_ent->mmio_base = base;
988
989 /* initialize adapter */
990 rc = ahci_host_init(probe_ent);
991 if (rc)
992 goto err_out;
993
994 ahci_print_info(probe_ent);
995
996 linkmap = probe_ent->link_port_map;
997
998 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
999 if (((linkmap >> i) & 0x01)) {
1000 if (ahci_port_start((u8) i)) {
1001 printf("Can not start port %d\n", i);
1002 continue;
1003 }
1004 #ifdef CONFIG_AHCI_SETFEATURES_XFER
1005 ahci_set_feature((u8) i);
1006 #endif
1007 }
1008 }
1009 err_out:
1010 return rc;
1011 }
1012
1013 void __weak scsi_init(void)
1014 {
1015 }
1016
1017 #endif
1018
1019 /*
1020 * In the general case of generic rotating media it makes sense to have a
1021 * flush capability. It probably even makes sense in the case of SSDs because
1022 * one cannot always know for sure what kind of internal cache/flush mechanism
1023 * is embodied therein. At first it was planned to invoke this after the last
1024 * write to disk and before rebooting. In practice, knowing, a priori, which
1025 * is the last write is difficult. Because writing to the disk in u-boot is
1026 * very rare, this flush command will be invoked after every block write.
1027 */
1028 static int ata_io_flush(u8 port)
1029 {
1030 u8 fis[20];
1031 struct ahci_ioports *pp = &(probe_ent->port[port]);
1032 void __iomem *port_mmio = pp->port_mmio;
1033 u32 cmd_fis_len = 5; /* five dwords */
1034
1035 /* Preset the FIS */
1036 memset(fis, 0, 20);
1037 fis[0] = 0x27; /* Host to device FIS. */
1038 fis[1] = 1 << 7; /* Command FIS. */
1039 fis[2] = ATA_CMD_FLUSH_EXT;
1040
1041 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1042 ahci_fill_cmd_slot(pp, cmd_fis_len);
1043 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1044
1045 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1046 WAIT_MS_FLUSH, 0x1)) {
1047 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1048 return -EIO;
1049 }
1050
1051 return 0;
1052 }
1053
1054
1055 __weak void scsi_bus_reset(void)
1056 {
1057 /*Not implement*/
1058 }
1059
1060 void scsi_print_error(ccb * pccb)
1061 {
1062 /*The ahci error info can be read in the ahci driver*/
1063 }
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