2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference on libata and ahci drvier in kernel
14 #include <asm/processor.h>
15 #include <asm/errno.h>
20 #include <linux/ctype.h>
23 static int ata_io_flush(u8 port
);
25 struct ahci_probe_ent
*probe_ent
= NULL
;
26 u16
*ataid
[AHCI_MAX_PORTS
];
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 20000
42 #define WAIT_MS_DATAIO 10000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 200
46 static inline void __iomem
*ahci_port_base(void __iomem
*base
, u32 port
)
48 return base
+ 0x100 + (port
* 0x80);
52 static void ahci_setup_port(struct ahci_ioports
*port
, void __iomem
*base
,
53 unsigned int port_idx
)
55 base
= ahci_port_base(base
, port_idx
);
57 port
->cmd_addr
= base
;
58 port
->scr_addr
= base
+ PORT_SCR
;
62 #define msleep(a) udelay(a * 1000)
64 static void ahci_dcache_flush_range(unsigned long begin
, unsigned long len
)
66 const unsigned long start
= begin
;
67 const unsigned long end
= start
+ len
;
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
70 flush_dcache_range(start
, end
);
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
78 static void ahci_dcache_invalidate_range(unsigned long begin
, unsigned long len
)
80 const unsigned long start
= begin
;
81 const unsigned long end
= start
+ len
;
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
84 invalidate_dcache_range(start
, end
);
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports
*pp
)
93 ahci_dcache_flush_range((unsigned long)pp
->cmd_slot
,
94 AHCI_PORT_PRIV_DMA_SZ
);
97 static int waiting_for_cmd_completed(void __iomem
*offset
,
104 for (i
= 0; ((status
= readl(offset
)) & sign
) && i
< timeout_msec
; i
++)
107 return (i
< timeout_msec
) ? 0 : -1;
110 int __weak
ahci_link_up(struct ahci_probe_ent
*probe_ent
, u8 port
)
114 void __iomem
*port_mmio
= probe_ent
->port
[port
].port_mmio
;
117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
121 while (j
< WAIT_MS_LINKUP
) {
122 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
123 tmp
&= PORT_SCR_STAT_DET_MASK
;
124 if (tmp
== PORT_SCR_STAT_DET_PHYRDY
)
132 #ifdef CONFIG_SUNXI_AHCI
133 /* The sunxi AHCI controller requires this undocumented setup */
134 static void sunxi_dma_init(void __iomem
*port_mmio
)
136 clrsetbits_le32(port_mmio
+ PORT_P0DMACR
, 0x0000ff00, 0x00004400);
140 int ahci_reset(void __iomem
*base
)
143 u32 __iomem
*host_ctl_reg
= base
+ HOST_CTL
;
144 u32 tmp
= readl(host_ctl_reg
); /* global controller reset */
146 if ((tmp
& HOST_RESET
) == 0)
147 writel_with_flush(tmp
| HOST_RESET
, host_ctl_reg
);
150 * reset must complete within 1 second, or
151 * the hardware should be considered fried.
155 tmp
= readl(host_ctl_reg
);
157 } while ((i
> 0) && (tmp
& HOST_RESET
));
160 printf("controller reset failed (0x%x)\n", tmp
);
167 static int ahci_host_init(struct ahci_probe_ent
*probe_ent
)
169 #ifndef CONFIG_SCSI_AHCI_PLAT
170 pci_dev_t pdev
= probe_ent
->dev
;
172 unsigned short vendor
;
174 void __iomem
*mmio
= probe_ent
->mmio_base
;
175 u32 tmp
, cap_save
, cmd
;
177 void __iomem
*port_mmio
;
180 debug("ahci_host_init: start\n");
182 cap_save
= readl(mmio
+ HOST_CAP
);
183 cap_save
&= ((1 << 28) | (1 << 17));
184 cap_save
|= (1 << 27); /* Staggered Spin-up. Not needed. */
186 ret
= ahci_reset(probe_ent
->mmio_base
);
190 writel_with_flush(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
191 writel(cap_save
, mmio
+ HOST_CAP
);
192 writel_with_flush(0xf, mmio
+ HOST_PORTS_IMPL
);
194 #ifndef CONFIG_SCSI_AHCI_PLAT
195 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
197 if (vendor
== PCI_VENDOR_ID_INTEL
) {
199 pci_read_config_word(pdev
, 0x92, &tmp16
);
201 pci_write_config_word(pdev
, 0x92, tmp16
);
204 probe_ent
->cap
= readl(mmio
+ HOST_CAP
);
205 probe_ent
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
206 port_map
= probe_ent
->port_map
;
207 probe_ent
->n_ports
= (probe_ent
->cap
& 0x1f) + 1;
209 debug("cap 0x%x port_map 0x%x n_ports %d\n",
210 probe_ent
->cap
, probe_ent
->port_map
, probe_ent
->n_ports
);
212 if (probe_ent
->n_ports
> CONFIG_SYS_SCSI_MAX_SCSI_ID
)
213 probe_ent
->n_ports
= CONFIG_SYS_SCSI_MAX_SCSI_ID
;
215 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
216 if (!(port_map
& (1 << i
)))
218 probe_ent
->port
[i
].port_mmio
= ahci_port_base(mmio
, i
);
219 port_mmio
= (u8
*) probe_ent
->port
[i
].port_mmio
;
220 ahci_setup_port(&probe_ent
->port
[i
], mmio
, i
);
222 /* make sure port is not active */
223 tmp
= readl(port_mmio
+ PORT_CMD
);
224 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
225 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
226 debug("Port %d is active. Deactivating.\n", i
);
227 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
228 PORT_CMD_FIS_RX
| PORT_CMD_START
);
229 writel_with_flush(tmp
, port_mmio
+ PORT_CMD
);
231 /* spec says 500 msecs for each bit, so
232 * this is slightly incorrect.
237 #ifdef CONFIG_SUNXI_AHCI
238 sunxi_dma_init(port_mmio
);
241 /* Add the spinup command to whatever mode bits may
242 * already be on in the command register.
244 cmd
= readl(port_mmio
+ PORT_CMD
);
245 cmd
|= PORT_CMD_SPIN_UP
;
246 writel_with_flush(cmd
, port_mmio
+ PORT_CMD
);
248 /* Bring up SATA link. */
249 ret
= ahci_link_up(probe_ent
, i
);
251 printf("SATA link %d timeout.\n", i
);
254 debug("SATA link ok.\n");
257 /* Clear error status */
258 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
260 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
262 debug("Spinning up device on SATA port %d... ", i
);
265 while (j
< WAIT_MS_SPINUP
) {
266 tmp
= readl(port_mmio
+ PORT_TFDATA
);
267 if (!(tmp
& (ATA_BUSY
| ATA_DRQ
)))
270 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
271 tmp
&= PORT_SCR_STAT_DET_MASK
;
272 if (tmp
== PORT_SCR_STAT_DET_PHYRDY
)
277 tmp
= readl(port_mmio
+ PORT_SCR_STAT
) & PORT_SCR_STAT_DET_MASK
;
278 if (tmp
== PORT_SCR_STAT_DET_COMINIT
) {
279 debug("SATA link %d down (COMINIT received), retrying...\n", i
);
284 printf("Target spinup took %d ms.\n", j
);
285 if (j
== WAIT_MS_SPINUP
)
290 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
291 debug("PORT_SCR_ERR 0x%x\n", tmp
);
292 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
294 /* ack any pending irq events for this port */
295 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
296 debug("PORT_IRQ_STAT 0x%x\n", tmp
);
298 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
300 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
302 /* set irq mask (enables interrupts) */
303 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
305 /* register linkup ports */
306 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
307 debug("SATA port %d status: 0x%x\n", i
, tmp
);
308 if ((tmp
& PORT_SCR_STAT_DET_MASK
) == PORT_SCR_STAT_DET_PHYRDY
)
309 probe_ent
->link_port_map
|= (0x01 << i
);
312 tmp
= readl(mmio
+ HOST_CTL
);
313 debug("HOST_CTL 0x%x\n", tmp
);
314 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
315 tmp
= readl(mmio
+ HOST_CTL
);
316 debug("HOST_CTL 0x%x\n", tmp
);
317 #ifndef CONFIG_SCSI_AHCI_PLAT
318 pci_read_config_word(pdev
, PCI_COMMAND
, &tmp16
);
319 tmp
|= PCI_COMMAND_MASTER
;
320 pci_write_config_word(pdev
, PCI_COMMAND
, tmp16
);
326 static void ahci_print_info(struct ahci_probe_ent
*probe_ent
)
328 #ifndef CONFIG_SCSI_AHCI_PLAT
329 pci_dev_t pdev
= probe_ent
->dev
;
332 void __iomem
*mmio
= probe_ent
->mmio_base
;
333 u32 vers
, cap
, cap2
, impl
, speed
;
337 vers
= readl(mmio
+ HOST_VERSION
);
338 cap
= probe_ent
->cap
;
339 cap2
= readl(mmio
+ HOST_CAP2
);
340 impl
= probe_ent
->port_map
;
342 speed
= (cap
>> 20) & 0xf;
352 #ifdef CONFIG_SCSI_AHCI_PLAT
355 pci_read_config_word(pdev
, 0x0a, &cc
);
358 else if (cc
== 0x0106)
360 else if (cc
== 0x0104)
365 printf("AHCI %02x%02x.%02x%02x "
366 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
371 ((cap
>> 8) & 0x1f) + 1, (cap
& 0x1f) + 1, speed_s
, impl
, scc_s
);
377 cap
& (1 << 31) ? "64bit " : "",
378 cap
& (1 << 30) ? "ncq " : "",
379 cap
& (1 << 28) ? "ilck " : "",
380 cap
& (1 << 27) ? "stag " : "",
381 cap
& (1 << 26) ? "pm " : "",
382 cap
& (1 << 25) ? "led " : "",
383 cap
& (1 << 24) ? "clo " : "",
384 cap
& (1 << 19) ? "nz " : "",
385 cap
& (1 << 18) ? "only " : "",
386 cap
& (1 << 17) ? "pmp " : "",
387 cap
& (1 << 16) ? "fbss " : "",
388 cap
& (1 << 15) ? "pio " : "",
389 cap
& (1 << 14) ? "slum " : "",
390 cap
& (1 << 13) ? "part " : "",
391 cap
& (1 << 7) ? "ccc " : "",
392 cap
& (1 << 6) ? "ems " : "",
393 cap
& (1 << 5) ? "sxs " : "",
394 cap2
& (1 << 2) ? "apst " : "",
395 cap2
& (1 << 1) ? "nvmp " : "",
396 cap2
& (1 << 0) ? "boh " : "");
399 #ifndef CONFIG_SCSI_AHCI_PLAT
400 static int ahci_init_one(pci_dev_t pdev
)
405 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
407 printf("%s: No memory for probe_ent\n", __func__
);
411 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
412 probe_ent
->dev
= pdev
;
414 probe_ent
->host_flags
= ATA_FLAG_SATA
419 probe_ent
->pio_mask
= 0x1f;
420 probe_ent
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
422 probe_ent
->mmio_base
= pci_map_bar(pdev
, PCI_BASE_ADDRESS_5
,
424 debug("ahci mmio_base=0x%p\n", probe_ent
->mmio_base
);
427 * JMicron-specific fixup:
428 * make sure we're in AHCI mode
430 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
431 if (vendor
== 0x197b)
432 pci_write_config_byte(pdev
, 0x41, 0xa1);
434 /* initialize adapter */
435 rc
= ahci_host_init(probe_ent
);
439 ahci_print_info(probe_ent
);
448 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
450 static int ahci_fill_sg(u8 port
, unsigned char *buf
, int buf_len
)
452 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
453 struct ahci_sg
*ahci_sg
= pp
->cmd_tbl_sg
;
457 sg_count
= ((buf_len
- 1) / MAX_DATA_BYTE_COUNT
) + 1;
458 if (sg_count
> AHCI_MAX_SG
) {
459 printf("Error:Too much sg!\n");
463 for (i
= 0; i
< sg_count
; i
++) {
465 cpu_to_le32((unsigned long) buf
+ i
* MAX_DATA_BYTE_COUNT
);
466 ahci_sg
->addr_hi
= 0;
467 ahci_sg
->flags_size
= cpu_to_le32(0x3fffff &
468 (buf_len
< MAX_DATA_BYTE_COUNT
470 : (MAX_DATA_BYTE_COUNT
- 1)));
472 buf_len
-= MAX_DATA_BYTE_COUNT
;
479 static void ahci_fill_cmd_slot(struct ahci_ioports
*pp
, u32 opts
)
481 pp
->cmd_slot
->opts
= cpu_to_le32(opts
);
482 pp
->cmd_slot
->status
= 0;
483 pp
->cmd_slot
->tbl_addr
= cpu_to_le32((u32
)pp
->cmd_tbl
& 0xffffffff);
484 #ifdef CONFIG_PHYS_64BIT
485 pp
->cmd_slot
->tbl_addr_hi
=
486 cpu_to_le32((u32
)(((pp
->cmd_tbl
) >> 16) >> 16));
491 #ifdef CONFIG_AHCI_SETFEATURES_XFER
492 static void ahci_set_feature(u8 port
)
494 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
495 void __iomem
*port_mmio
= pp
->port_mmio
;
496 u32 cmd_fis_len
= 5; /* five dwords */
500 memset(fis
, 0, sizeof(fis
));
503 fis
[2] = ATA_CMD_SET_FEATURES
;
504 fis
[3] = SETFEATURES_XFER
;
505 fis
[12] = __ilog2(probe_ent
->udma_mask
+ 1) + 0x40 - 0x01;
507 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, sizeof(fis
));
508 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
509 ahci_dcache_flush_sata_cmd(pp
);
510 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
511 readl(port_mmio
+ PORT_CMD_ISSUE
);
513 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
514 WAIT_MS_DATAIO
, 0x1)) {
515 printf("set feature error on port %d!\n", port
);
520 static int wait_spinup(void __iomem
*port_mmio
)
525 start
= get_timer(0);
527 tf_data
= readl(port_mmio
+ PORT_TFDATA
);
528 if (!(tf_data
& ATA_BUSY
))
530 } while (get_timer(start
) < WAIT_MS_SPINUP
);
535 static int ahci_port_start(u8 port
)
537 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
538 void __iomem
*port_mmio
= pp
->port_mmio
;
542 debug("Enter start port: %d\n", port
);
543 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
544 debug("Port %d status: %x\n", port
, port_status
);
545 if ((port_status
& 0xf) != 0x03) {
546 printf("No Link on this port!\n");
550 mem
= malloc(AHCI_PORT_PRIV_DMA_SZ
+ 2048);
553 printf("%s: No mem for table!\n", __func__
);
557 /* Aligned to 2048-bytes */
558 mem
= memalign(2048, AHCI_PORT_PRIV_DMA_SZ
);
559 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
562 * First item in chunk of DMA memory: 32-slot command table,
563 * 32 bytes each in size
566 (struct ahci_cmd_hdr
*)(uintptr_t)virt_to_phys((void *)mem
);
567 debug("cmd_slot = %p\n", pp
->cmd_slot
);
568 mem
+= (AHCI_CMD_SLOT_SZ
+ 224);
571 * Second item: Received-FIS area
573 pp
->rx_fis
= virt_to_phys((void *)mem
);
574 mem
+= AHCI_RX_FIS_SZ
;
577 * Third item: data area for storing a single command
578 * and its scatter-gather table
580 pp
->cmd_tbl
= virt_to_phys((void *)mem
);
581 debug("cmd_tbl_dma = %lx\n", pp
->cmd_tbl
);
583 mem
+= AHCI_CMD_TBL_HDR
;
585 (struct ahci_sg
*)(uintptr_t)virt_to_phys((void *)mem
);
587 writel_with_flush((unsigned long)pp
->cmd_slot
,
588 port_mmio
+ PORT_LST_ADDR
);
590 writel_with_flush(pp
->rx_fis
, port_mmio
+ PORT_FIS_ADDR
);
592 #ifdef CONFIG_SUNXI_AHCI
593 sunxi_dma_init(port_mmio
);
596 writel_with_flush(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
597 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
598 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
600 debug("Exit start port %d\n", port
);
603 * Make sure interface is not busy based on error and status
604 * information from task file data register before proceeding
606 return wait_spinup(port_mmio
);
610 static int ahci_device_data_io(u8 port
, u8
*fis
, int fis_len
, u8
*buf
,
611 int buf_len
, u8 is_write
)
614 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
615 void __iomem
*port_mmio
= pp
->port_mmio
;
620 debug("Enter %s: for port %d\n", __func__
, port
);
622 if (port
> probe_ent
->n_ports
) {
623 printf("Invalid port number %d\n", port
);
627 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
628 if ((port_status
& 0xf) != 0x03) {
629 debug("No Link on port %d!\n", port
);
633 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, fis_len
);
635 sg_count
= ahci_fill_sg(port
, buf
, buf_len
);
636 opts
= (fis_len
>> 2) | (sg_count
<< 16) | (is_write
<< 6);
637 ahci_fill_cmd_slot(pp
, opts
);
639 ahci_dcache_flush_sata_cmd(pp
);
640 ahci_dcache_flush_range((unsigned long)buf
, (unsigned long)buf_len
);
642 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
644 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
645 WAIT_MS_DATAIO
, 0x1)) {
646 printf("timeout exit!\n");
650 ahci_dcache_invalidate_range((unsigned long)buf
,
651 (unsigned long)buf_len
);
652 debug("%s: %d byte transferred.\n", __func__
, pp
->cmd_slot
->status
);
658 static char *ata_id_strcpy(u16
*target
, u16
*src
, int len
)
661 for (i
= 0; i
< len
/ 2; i
++)
662 target
[i
] = swab16(src
[i
]);
663 return (char *)target
;
667 * SCSI INQUIRY command operation.
669 static int ata_scsiop_inquiry(ccb
*pccb
)
671 static const u8 hdr
[] = {
674 0x5, /* claim SPC-3 version compatibility */
680 ALLOC_CACHE_ALIGN_BUFFER(u16
, tmpid
, ATA_ID_WORDS
);
683 /* Clean ccb data buffer */
684 memset(pccb
->pdata
, 0, pccb
->datalen
);
686 memcpy(pccb
->pdata
, hdr
, sizeof(hdr
));
688 if (pccb
->datalen
<= 35)
691 memset(fis
, 0, sizeof(fis
));
692 /* Construct the FIS */
693 fis
[0] = 0x27; /* Host to device FIS. */
694 fis
[1] = 1 << 7; /* Command FIS. */
695 fis
[2] = ATA_CMD_ID_ATA
; /* Command byte. */
697 /* Read id from sata */
700 if (ahci_device_data_io(port
, (u8
*) &fis
, sizeof(fis
), (u8
*)tmpid
,
701 ATA_ID_WORDS
* 2, 0)) {
702 debug("scsi_ahci: SCSI inquiry command failure.\n");
707 ataid
[port
] = malloc(ATA_ID_WORDS
* 2);
709 printf("%s: No memory for ataid[port]\n", __func__
);
716 memcpy(idbuf
, tmpid
, ATA_ID_WORDS
* 2);
717 ata_swap_buf_le16(idbuf
, ATA_ID_WORDS
);
719 memcpy(&pccb
->pdata
[8], "ATA ", 8);
720 ata_id_strcpy((u16
*)&pccb
->pdata
[16], &idbuf
[ATA_ID_PROD
], 16);
721 ata_id_strcpy((u16
*)&pccb
->pdata
[32], &idbuf
[ATA_ID_FW_REV
], 4);
731 * SCSI READ10/WRITE10 command operation.
733 static int ata_scsiop_read_write(ccb
*pccb
, u8 is_write
)
738 u8
*user_buffer
= pccb
->pdata
;
739 u32 user_buffer_size
= pccb
->datalen
;
741 /* Retrieve the base LBA number from the ccb structure. */
742 if (pccb
->cmd
[0] == SCSI_READ16
) {
743 memcpy(&lba
, pccb
->cmd
+ 2, 8);
744 lba
= be64_to_cpu(lba
);
747 memcpy(&temp
, pccb
->cmd
+ 2, 4);
748 lba
= be32_to_cpu(temp
);
752 * Retrieve the base LBA number and the block count from
755 * For 10-byte and 16-byte SCSI R/W commands, transfer
756 * length 0 means transfer 0 block of data.
757 * However, for ATA R/W commands, sector count 0 means
758 * 256 or 65536 sectors, not 0 sectors as in SCSI.
760 * WARNING: one or two older ATA drives treat 0 as 0...
762 if (pccb
->cmd
[0] == SCSI_READ16
)
763 blocks
= (((u16
)pccb
->cmd
[13]) << 8) | ((u16
) pccb
->cmd
[14]);
765 blocks
= (((u16
)pccb
->cmd
[7]) << 8) | ((u16
) pccb
->cmd
[8]);
767 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU
"\n",
768 is_write
? "write" : "read", blocks
, lba
);
771 memset(fis
, 0, sizeof(fis
));
772 fis
[0] = 0x27; /* Host to device FIS. */
773 fis
[1] = 1 << 7; /* Command FIS. */
774 /* Command byte (read/write). */
775 fis
[2] = is_write
? ATA_CMD_WRITE_EXT
: ATA_CMD_READ_EXT
;
778 u16 now_blocks
; /* number of blocks per iteration */
779 u32 transfer_size
; /* number of bytes per iteration */
781 now_blocks
= min((u16
)MAX_SATA_BLOCKS_READ_WRITE
, blocks
);
783 transfer_size
= ATA_SECT_SIZE
* now_blocks
;
784 if (transfer_size
> user_buffer_size
) {
785 printf("scsi_ahci: Error: buffer too small.\n");
790 * LBA48 SATA command but only use 32bit address range within
791 * that (unless we've enabled 64bit LBA support). The next
792 * smaller command range (28bit) is too small.
794 fis
[4] = (lba
>> 0) & 0xff;
795 fis
[5] = (lba
>> 8) & 0xff;
796 fis
[6] = (lba
>> 16) & 0xff;
797 fis
[7] = 1 << 6; /* device reg: set LBA mode */
798 fis
[8] = ((lba
>> 24) & 0xff);
799 #ifdef CONFIG_SYS_64BIT_LBA
800 if (pccb
->cmd
[0] == SCSI_READ16
) {
801 fis
[9] = ((lba
>> 32) & 0xff);
802 fis
[10] = ((lba
>> 40) & 0xff);
806 fis
[3] = 0xe0; /* features */
808 /* Block (sector) count */
809 fis
[12] = (now_blocks
>> 0) & 0xff;
810 fis
[13] = (now_blocks
>> 8) & 0xff;
812 /* Read/Write from ahci */
813 if (ahci_device_data_io(pccb
->target
, (u8
*) &fis
, sizeof(fis
),
814 user_buffer
, transfer_size
,
816 debug("scsi_ahci: SCSI %s10 command failure.\n",
817 is_write
? "WRITE" : "READ");
821 /* If this transaction is a write, do a following flush.
822 * Writes in u-boot are so rare, and the logic to know when is
823 * the last write and do a flush only there is sufficiently
824 * difficult. Just do a flush after every write. This incurs,
825 * usually, one extra flush when the rare writes do happen.
828 if (-EIO
== ata_io_flush(pccb
->target
))
831 user_buffer
+= transfer_size
;
832 user_buffer_size
-= transfer_size
;
833 blocks
-= now_blocks
;
842 * SCSI READ CAPACITY10 command operation.
844 static int ata_scsiop_read_capacity10(ccb
*pccb
)
850 if (!ataid
[pccb
->target
]) {
851 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
853 "\tPlease run SCSI commmand INQUIRY firstly!\n");
857 cap64
= ata_id_n_sectors(ataid
[pccb
->target
]);
858 if (cap64
> 0x100000000ULL
)
861 cap
= cpu_to_be32(cap64
);
862 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
864 block_size
= cpu_to_be32((u32
)512);
865 memcpy(&pccb
->pdata
[4], &block_size
, 4);
872 * SCSI READ CAPACITY16 command operation.
874 static int ata_scsiop_read_capacity16(ccb
*pccb
)
879 if (!ataid
[pccb
->target
]) {
880 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
882 "\tPlease run SCSI commmand INQUIRY firstly!\n");
886 cap
= ata_id_n_sectors(ataid
[pccb
->target
]);
887 cap
= cpu_to_be64(cap
);
888 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
890 block_size
= cpu_to_be64((u64
)512);
891 memcpy(&pccb
->pdata
[8], &block_size
, 8);
898 * SCSI TEST UNIT READY command operation.
900 static int ata_scsiop_test_unit_ready(ccb
*pccb
)
902 return (ataid
[pccb
->target
]) ? 0 : -EPERM
;
906 int scsi_exec(ccb
*pccb
)
910 switch (pccb
->cmd
[0]) {
913 ret
= ata_scsiop_read_write(pccb
, 0);
916 ret
= ata_scsiop_read_write(pccb
, 1);
918 case SCSI_RD_CAPAC10
:
919 ret
= ata_scsiop_read_capacity10(pccb
);
921 case SCSI_RD_CAPAC16
:
922 ret
= ata_scsiop_read_capacity16(pccb
);
925 ret
= ata_scsiop_test_unit_ready(pccb
);
928 ret
= ata_scsiop_inquiry(pccb
);
931 printf("Unsupport SCSI command 0x%02x\n", pccb
->cmd
[0]);
936 debug("SCSI command 0x%02x ret errno %d\n", pccb
->cmd
[0], ret
);
944 void scsi_low_level_init(int busdevfunc
)
949 #ifndef CONFIG_SCSI_AHCI_PLAT
950 ahci_init_one(busdevfunc
);
953 linkmap
= probe_ent
->link_port_map
;
955 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
956 if (((linkmap
>> i
) & 0x01)) {
957 if (ahci_port_start((u8
) i
)) {
958 printf("Can not start port %d\n", i
);
961 #ifdef CONFIG_AHCI_SETFEATURES_XFER
962 ahci_set_feature((u8
) i
);
968 #ifdef CONFIG_SCSI_AHCI_PLAT
969 int ahci_init(void __iomem
*base
)
974 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
976 printf("%s: No memory for probe_ent\n", __func__
);
980 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
982 probe_ent
->host_flags
= ATA_FLAG_SATA
987 probe_ent
->pio_mask
= 0x1f;
988 probe_ent
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
990 probe_ent
->mmio_base
= base
;
992 /* initialize adapter */
993 rc
= ahci_host_init(probe_ent
);
997 ahci_print_info(probe_ent
);
999 linkmap
= probe_ent
->link_port_map
;
1001 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
1002 if (((linkmap
>> i
) & 0x01)) {
1003 if (ahci_port_start((u8
) i
)) {
1004 printf("Can not start port %d\n", i
);
1007 #ifdef CONFIG_AHCI_SETFEATURES_XFER
1008 ahci_set_feature((u8
) i
);
1016 void __weak
scsi_init(void)
1023 * In the general case of generic rotating media it makes sense to have a
1024 * flush capability. It probably even makes sense in the case of SSDs because
1025 * one cannot always know for sure what kind of internal cache/flush mechanism
1026 * is embodied therein. At first it was planned to invoke this after the last
1027 * write to disk and before rebooting. In practice, knowing, a priori, which
1028 * is the last write is difficult. Because writing to the disk in u-boot is
1029 * very rare, this flush command will be invoked after every block write.
1031 static int ata_io_flush(u8 port
)
1034 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
1035 void __iomem
*port_mmio
= pp
->port_mmio
;
1036 u32 cmd_fis_len
= 5; /* five dwords */
1038 /* Preset the FIS */
1040 fis
[0] = 0x27; /* Host to device FIS. */
1041 fis
[1] = 1 << 7; /* Command FIS. */
1042 fis
[2] = ATA_CMD_FLUSH_EXT
;
1044 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, 20);
1045 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
1046 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
1048 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
1049 WAIT_MS_FLUSH
, 0x1)) {
1050 debug("scsi_ahci: flush command timeout on port %d.\n", port
);
1058 __weak
void scsi_bus_reset(void)
1063 void scsi_print_error(ccb
* pccb
)
1065 /*The ahci error info can be read in the ahci driver*/