2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * with the reference on libata and ahci drvier in kernel
31 #include <asm/processor.h>
32 #include <asm/errno.h>
37 #include <linux/ctype.h>
40 static int ata_io_flush(u8 port
);
42 struct ahci_probe_ent
*probe_ent
= NULL
;
43 hd_driveid_t
*ataid
[AHCI_MAX_PORTS
];
45 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
48 * Some controllers limit number of blocks they can read/write at once.
49 * Contemporary SSD devices work much faster if the read/write size is aligned
50 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
53 #ifndef MAX_SATA_BLOCKS_READ_WRITE
54 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
57 /* Maximum timeouts for each event */
58 #define WAIT_MS_SPINUP 10000
59 #define WAIT_MS_DATAIO 5000
60 #define WAIT_MS_FLUSH 5000
61 #define WAIT_MS_LINKUP 4
63 static inline u32
ahci_port_base(u32 base
, u32 port
)
65 return base
+ 0x100 + (port
* 0x80);
69 static void ahci_setup_port(struct ahci_ioports
*port
, unsigned long base
,
70 unsigned int port_idx
)
72 base
= ahci_port_base(base
, port_idx
);
74 port
->cmd_addr
= base
;
75 port
->scr_addr
= base
+ PORT_SCR
;
79 #define msleep(a) udelay(a * 1000)
81 static void ahci_dcache_flush_range(unsigned begin
, unsigned len
)
83 const unsigned long start
= begin
;
84 const unsigned long end
= start
+ len
;
86 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
87 flush_dcache_range(start
, end
);
91 * SATA controller DMAs to physical RAM. Ensure data from the
92 * controller is invalidated from dcache; next access comes from
95 static void ahci_dcache_invalidate_range(unsigned begin
, unsigned len
)
97 const unsigned long start
= begin
;
98 const unsigned long end
= start
+ len
;
100 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
101 invalidate_dcache_range(start
, end
);
105 * Ensure data for SATA controller is flushed out of dcache and
106 * written to physical memory.
108 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports
*pp
)
110 ahci_dcache_flush_range((unsigned long)pp
->cmd_slot
,
111 AHCI_PORT_PRIV_DMA_SZ
);
114 static int waiting_for_cmd_completed(volatile u8
*offset
,
121 for (i
= 0; ((status
= readl(offset
)) & sign
) && i
< timeout_msec
; i
++)
124 return (i
< timeout_msec
) ? 0 : -1;
128 static int ahci_host_init(struct ahci_probe_ent
*probe_ent
)
130 #ifndef CONFIG_SCSI_AHCI_PLAT
131 pci_dev_t pdev
= probe_ent
->dev
;
133 unsigned short vendor
;
135 volatile u8
*mmio
= (volatile u8
*)probe_ent
->mmio_base
;
136 u32 tmp
, cap_save
, cmd
;
138 volatile u8
*port_mmio
;
140 debug("ahci_host_init: start\n");
142 cap_save
= readl(mmio
+ HOST_CAP
);
143 cap_save
&= ((1 << 28) | (1 << 17));
144 cap_save
|= (1 << 27); /* Staggered Spin-up. Not needed. */
146 /* global controller reset */
147 tmp
= readl(mmio
+ HOST_CTL
);
148 if ((tmp
& HOST_RESET
) == 0)
149 writel_with_flush(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
151 /* reset must complete within 1 second, or
152 * the hardware should be considered fried.
157 tmp
= readl(mmio
+ HOST_CTL
);
159 debug("controller reset failed (0x%x)\n", tmp
);
162 } while (tmp
& HOST_RESET
);
164 writel_with_flush(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
165 writel(cap_save
, mmio
+ HOST_CAP
);
166 writel_with_flush(0xf, mmio
+ HOST_PORTS_IMPL
);
168 #ifndef CONFIG_SCSI_AHCI_PLAT
169 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
171 if (vendor
== PCI_VENDOR_ID_INTEL
) {
173 pci_read_config_word(pdev
, 0x92, &tmp16
);
175 pci_write_config_word(pdev
, 0x92, tmp16
);
178 probe_ent
->cap
= readl(mmio
+ HOST_CAP
);
179 probe_ent
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
180 probe_ent
->n_ports
= (probe_ent
->cap
& 0x1f) + 1;
182 debug("cap 0x%x port_map 0x%x n_ports %d\n",
183 probe_ent
->cap
, probe_ent
->port_map
, probe_ent
->n_ports
);
185 if (probe_ent
->n_ports
> CONFIG_SYS_SCSI_MAX_SCSI_ID
)
186 probe_ent
->n_ports
= CONFIG_SYS_SCSI_MAX_SCSI_ID
;
188 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
189 probe_ent
->port
[i
].port_mmio
= ahci_port_base((u32
) mmio
, i
);
190 port_mmio
= (u8
*) probe_ent
->port
[i
].port_mmio
;
191 ahci_setup_port(&probe_ent
->port
[i
], (unsigned long)mmio
, i
);
193 /* make sure port is not active */
194 tmp
= readl(port_mmio
+ PORT_CMD
);
195 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
196 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
197 debug("Port %d is active. Deactivating.\n", i
);
198 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
199 PORT_CMD_FIS_RX
| PORT_CMD_START
);
200 writel_with_flush(tmp
, port_mmio
+ PORT_CMD
);
202 /* spec says 500 msecs for each bit, so
203 * this is slightly incorrect.
208 /* Add the spinup command to whatever mode bits may
209 * already be on in the command register.
211 cmd
= readl(port_mmio
+ PORT_CMD
);
212 cmd
|= PORT_CMD_FIS_RX
;
213 cmd
|= PORT_CMD_SPIN_UP
;
214 writel_with_flush(cmd
, port_mmio
+ PORT_CMD
);
216 /* Bring up SATA link.
217 * SATA link bringup time is usually less than 1 ms; only very
218 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
221 while (j
< WAIT_MS_LINKUP
) {
222 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
223 if ((tmp
& 0xf) == 0x3)
228 if (j
== WAIT_MS_LINKUP
) {
229 printf("SATA link %d timeout.\n", i
);
232 debug("SATA link ok.\n");
235 /* Clear error status */
236 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
238 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
240 debug("Spinning up device on SATA port %d... ", i
);
243 while (j
< WAIT_MS_SPINUP
) {
244 tmp
= readl(port_mmio
+ PORT_TFDATA
);
245 if (!(tmp
& (ATA_STAT_BUSY
| ATA_STAT_DRQ
)))
250 printf("Target spinup took %d ms.\n", j
);
251 if (j
== WAIT_MS_SPINUP
)
256 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
257 debug("PORT_SCR_ERR 0x%x\n", tmp
);
258 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
260 /* ack any pending irq events for this port */
261 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
262 debug("PORT_IRQ_STAT 0x%x\n", tmp
);
264 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
266 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
268 /* set irq mask (enables interrupts) */
269 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
271 /* register linkup ports */
272 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
273 debug("SATA port %d status: 0x%x\n", i
, tmp
);
274 if ((tmp
& 0xf) == 0x03)
275 probe_ent
->link_port_map
|= (0x01 << i
);
278 tmp
= readl(mmio
+ HOST_CTL
);
279 debug("HOST_CTL 0x%x\n", tmp
);
280 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
281 tmp
= readl(mmio
+ HOST_CTL
);
282 debug("HOST_CTL 0x%x\n", tmp
);
283 #ifndef CONFIG_SCSI_AHCI_PLAT
284 pci_read_config_word(pdev
, PCI_COMMAND
, &tmp16
);
285 tmp
|= PCI_COMMAND_MASTER
;
286 pci_write_config_word(pdev
, PCI_COMMAND
, tmp16
);
292 static void ahci_print_info(struct ahci_probe_ent
*probe_ent
)
294 #ifndef CONFIG_SCSI_AHCI_PLAT
295 pci_dev_t pdev
= probe_ent
->dev
;
298 volatile u8
*mmio
= (volatile u8
*)probe_ent
->mmio_base
;
299 u32 vers
, cap
, cap2
, impl
, speed
;
303 vers
= readl(mmio
+ HOST_VERSION
);
304 cap
= probe_ent
->cap
;
305 cap2
= readl(mmio
+ HOST_CAP2
);
306 impl
= probe_ent
->port_map
;
308 speed
= (cap
>> 20) & 0xf;
318 #ifdef CONFIG_SCSI_AHCI_PLAT
321 pci_read_config_word(pdev
, 0x0a, &cc
);
324 else if (cc
== 0x0106)
326 else if (cc
== 0x0104)
331 printf("AHCI %02x%02x.%02x%02x "
332 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
337 ((cap
>> 8) & 0x1f) + 1, (cap
& 0x1f) + 1, speed_s
, impl
, scc_s
);
343 cap
& (1 << 31) ? "64bit " : "",
344 cap
& (1 << 30) ? "ncq " : "",
345 cap
& (1 << 28) ? "ilck " : "",
346 cap
& (1 << 27) ? "stag " : "",
347 cap
& (1 << 26) ? "pm " : "",
348 cap
& (1 << 25) ? "led " : "",
349 cap
& (1 << 24) ? "clo " : "",
350 cap
& (1 << 19) ? "nz " : "",
351 cap
& (1 << 18) ? "only " : "",
352 cap
& (1 << 17) ? "pmp " : "",
353 cap
& (1 << 16) ? "fbss " : "",
354 cap
& (1 << 15) ? "pio " : "",
355 cap
& (1 << 14) ? "slum " : "",
356 cap
& (1 << 13) ? "part " : "",
357 cap
& (1 << 7) ? "ccc " : "",
358 cap
& (1 << 6) ? "ems " : "",
359 cap
& (1 << 5) ? "sxs " : "",
360 cap2
& (1 << 2) ? "apst " : "",
361 cap2
& (1 << 1) ? "nvmp " : "",
362 cap2
& (1 << 0) ? "boh " : "");
365 #ifndef CONFIG_SCSI_AHCI_PLAT
366 static int ahci_init_one(pci_dev_t pdev
)
371 memset((void *)ataid
, 0, sizeof(hd_driveid_t
*) * AHCI_MAX_PORTS
);
373 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
374 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
375 probe_ent
->dev
= pdev
;
377 probe_ent
->host_flags
= ATA_FLAG_SATA
382 probe_ent
->pio_mask
= 0x1f;
383 probe_ent
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
385 pci_read_config_dword(pdev
, PCI_BASE_ADDRESS_5
, &probe_ent
->mmio_base
);
386 debug("ahci mmio_base=0x%08x\n", probe_ent
->mmio_base
);
389 * JMicron-specific fixup:
390 * make sure we're in AHCI mode
392 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
393 if (vendor
== 0x197b)
394 pci_write_config_byte(pdev
, 0x41, 0xa1);
396 /* initialize adapter */
397 rc
= ahci_host_init(probe_ent
);
401 ahci_print_info(probe_ent
);
410 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
412 static int ahci_fill_sg(u8 port
, unsigned char *buf
, int buf_len
)
414 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
415 struct ahci_sg
*ahci_sg
= pp
->cmd_tbl_sg
;
419 sg_count
= ((buf_len
- 1) / MAX_DATA_BYTE_COUNT
) + 1;
420 if (sg_count
> AHCI_MAX_SG
) {
421 printf("Error:Too much sg!\n");
425 for (i
= 0; i
< sg_count
; i
++) {
427 cpu_to_le32((u32
) buf
+ i
* MAX_DATA_BYTE_COUNT
);
428 ahci_sg
->addr_hi
= 0;
429 ahci_sg
->flags_size
= cpu_to_le32(0x3fffff &
430 (buf_len
< MAX_DATA_BYTE_COUNT
432 : (MAX_DATA_BYTE_COUNT
- 1)));
434 buf_len
-= MAX_DATA_BYTE_COUNT
;
441 static void ahci_fill_cmd_slot(struct ahci_ioports
*pp
, u32 opts
)
443 pp
->cmd_slot
->opts
= cpu_to_le32(opts
);
444 pp
->cmd_slot
->status
= 0;
445 pp
->cmd_slot
->tbl_addr
= cpu_to_le32(pp
->cmd_tbl
& 0xffffffff);
446 pp
->cmd_slot
->tbl_addr_hi
= 0;
450 #ifdef CONFIG_AHCI_SETFEATURES_XFER
451 static void ahci_set_feature(u8 port
)
453 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
454 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
455 u32 cmd_fis_len
= 5; /* five dwords */
459 memset(fis
, 0, sizeof(fis
));
462 fis
[2] = ATA_CMD_SETF
;
463 fis
[3] = SETFEATURES_XFER
;
464 fis
[12] = __ilog2(probe_ent
->udma_mask
+ 1) + 0x40 - 0x01;
466 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, sizeof(fis
));
467 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
468 ahci_dcache_flush_sata_cmd(pp
);
469 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
470 readl(port_mmio
+ PORT_CMD_ISSUE
);
472 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
473 WAIT_MS_DATAIO
, 0x1)) {
474 printf("set feature error on port %d!\n", port
);
480 static int ahci_port_start(u8 port
)
482 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
483 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
487 debug("Enter start port: %d\n", port
);
488 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
489 debug("Port %d status: %x\n", port
, port_status
);
490 if ((port_status
& 0xf) != 0x03) {
491 printf("No Link on this port!\n");
495 mem
= (u32
) malloc(AHCI_PORT_PRIV_DMA_SZ
+ 2048);
498 printf("No mem for table!\n");
502 mem
= (mem
+ 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
503 memset((u8
*) mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
506 * First item in chunk of DMA memory: 32-slot command table,
507 * 32 bytes each in size
510 (struct ahci_cmd_hdr
*)(uintptr_t)virt_to_phys((void *)mem
);
511 debug("cmd_slot = 0x%x\n", (unsigned)pp
->cmd_slot
);
512 mem
+= (AHCI_CMD_SLOT_SZ
+ 224);
515 * Second item: Received-FIS area
517 pp
->rx_fis
= virt_to_phys((void *)mem
);
518 mem
+= AHCI_RX_FIS_SZ
;
521 * Third item: data area for storing a single command
522 * and its scatter-gather table
524 pp
->cmd_tbl
= virt_to_phys((void *)mem
);
525 debug("cmd_tbl_dma = 0x%x\n", pp
->cmd_tbl
);
527 mem
+= AHCI_CMD_TBL_HDR
;
529 (struct ahci_sg
*)(uintptr_t)virt_to_phys((void *)mem
);
531 writel_with_flush((u32
) pp
->cmd_slot
, port_mmio
+ PORT_LST_ADDR
);
533 writel_with_flush(pp
->rx_fis
, port_mmio
+ PORT_FIS_ADDR
);
535 writel_with_flush(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
536 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
537 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
539 debug("Exit start port %d\n", port
);
545 static int ahci_device_data_io(u8 port
, u8
*fis
, int fis_len
, u8
*buf
,
546 int buf_len
, u8 is_write
)
549 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
550 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
555 debug("Enter %s: for port %d\n", __func__
, port
);
557 if (port
> probe_ent
->n_ports
) {
558 printf("Invalid port number %d\n", port
);
562 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
563 if ((port_status
& 0xf) != 0x03) {
564 debug("No Link on port %d!\n", port
);
568 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, fis_len
);
570 sg_count
= ahci_fill_sg(port
, buf
, buf_len
);
571 opts
= (fis_len
>> 2) | (sg_count
<< 16) | (is_write
<< 6);
572 ahci_fill_cmd_slot(pp
, opts
);
574 ahci_dcache_flush_sata_cmd(pp
);
575 ahci_dcache_flush_range((unsigned)buf
, (unsigned)buf_len
);
577 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
579 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
580 WAIT_MS_DATAIO
, 0x1)) {
581 printf("timeout exit!\n");
585 ahci_dcache_invalidate_range((unsigned)buf
, (unsigned)buf_len
);
586 debug("%s: %d byte transferred.\n", __func__
, pp
->cmd_slot
->status
);
592 static char *ata_id_strcpy(u16
*target
, u16
*src
, int len
)
595 for (i
= 0; i
< len
/ 2; i
++)
596 target
[i
] = swab16(src
[i
]);
597 return (char *)target
;
601 static void dump_ataid(hd_driveid_t
*ataid
)
603 debug("(49)ataid->capability = 0x%x\n", ataid
->capability
);
604 debug("(53)ataid->field_valid =0x%x\n", ataid
->field_valid
);
605 debug("(63)ataid->dma_mword = 0x%x\n", ataid
->dma_mword
);
606 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid
->eide_pio_modes
);
607 debug("(75)ataid->queue_depth = 0x%x\n", ataid
->queue_depth
);
608 debug("(80)ataid->major_rev_num = 0x%x\n", ataid
->major_rev_num
);
609 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid
->minor_rev_num
);
610 debug("(82)ataid->command_set_1 = 0x%x\n", ataid
->command_set_1
);
611 debug("(83)ataid->command_set_2 = 0x%x\n", ataid
->command_set_2
);
612 debug("(84)ataid->cfsse = 0x%x\n", ataid
->cfsse
);
613 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid
->cfs_enable_1
);
614 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid
->cfs_enable_2
);
615 debug("(87)ataid->csf_default = 0x%x\n", ataid
->csf_default
);
616 debug("(88)ataid->dma_ultra = 0x%x\n", ataid
->dma_ultra
);
617 debug("(93)ataid->hw_config = 0x%x\n", ataid
->hw_config
);
622 * SCSI INQUIRY command operation.
624 static int ata_scsiop_inquiry(ccb
*pccb
)
629 0x5, /* claim SPC-3 version compatibility */
637 /* Clean ccb data buffer */
638 memset(pccb
->pdata
, 0, pccb
->datalen
);
640 memcpy(pccb
->pdata
, hdr
, sizeof(hdr
));
642 if (pccb
->datalen
<= 35)
645 memset(fis
, 0, sizeof(fis
));
646 /* Construct the FIS */
647 fis
[0] = 0x27; /* Host to device FIS. */
648 fis
[1] = 1 << 7; /* Command FIS. */
649 fis
[2] = ATA_CMD_IDENT
; /* Command byte. */
651 /* Read id from sata */
653 if (!(tmpid
= malloc(sizeof(hd_driveid_t
))))
656 if (ahci_device_data_io(port
, (u8
*) &fis
, sizeof(fis
), tmpid
,
657 sizeof(hd_driveid_t
), 0)) {
658 debug("scsi_ahci: SCSI inquiry command failure.\n");
664 ataid
[port
] = (hd_driveid_t
*) tmpid
;
666 memcpy(&pccb
->pdata
[8], "ATA ", 8);
667 ata_id_strcpy((u16
*) &pccb
->pdata
[16], (u16
*)ataid
[port
]->model
, 16);
668 ata_id_strcpy((u16
*) &pccb
->pdata
[32], (u16
*)ataid
[port
]->fw_rev
, 4);
670 dump_ataid(ataid
[port
]);
676 * SCSI READ10/WRITE10 command operation.
678 static int ata_scsiop_read_write(ccb
*pccb
, u8 is_write
)
683 u8
*user_buffer
= pccb
->pdata
;
684 u32 user_buffer_size
= pccb
->datalen
;
686 /* Retrieve the base LBA number from the ccb structure. */
687 memcpy(&lba
, pccb
->cmd
+ 2, sizeof(lba
));
688 lba
= be32_to_cpu(lba
);
691 * And the number of blocks.
693 * For 10-byte and 16-byte SCSI R/W commands, transfer
694 * length 0 means transfer 0 block of data.
695 * However, for ATA R/W commands, sector count 0 means
696 * 256 or 65536 sectors, not 0 sectors as in SCSI.
698 * WARNING: one or two older ATA drives treat 0 as 0...
700 blocks
= (((u16
)pccb
->cmd
[7]) << 8) | ((u16
) pccb
->cmd
[8]);
702 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
703 is_write
? "write" : "read", (unsigned)lba
, blocks
);
706 memset(fis
, 0, sizeof(fis
));
707 fis
[0] = 0x27; /* Host to device FIS. */
708 fis
[1] = 1 << 7; /* Command FIS. */
709 /* Command byte (read/write). */
710 fis
[2] = is_write
? ATA_CMD_WRITE_EXT
: ATA_CMD_READ_EXT
;
713 u16 now_blocks
; /* number of blocks per iteration */
714 u32 transfer_size
; /* number of bytes per iteration */
716 now_blocks
= min(MAX_SATA_BLOCKS_READ_WRITE
, blocks
);
718 transfer_size
= ATA_BLOCKSIZE
* now_blocks
;
719 if (transfer_size
> user_buffer_size
) {
720 printf("scsi_ahci: Error: buffer too small.\n");
724 /* LBA48 SATA command but only use 32bit address range within
725 * that. The next smaller command range (28bit) is too small.
727 fis
[4] = (lba
>> 0) & 0xff;
728 fis
[5] = (lba
>> 8) & 0xff;
729 fis
[6] = (lba
>> 16) & 0xff;
730 fis
[7] = 1 << 6; /* device reg: set LBA mode */
731 fis
[8] = ((lba
>> 24) & 0xff);
732 fis
[3] = 0xe0; /* features */
734 /* Block (sector) count */
735 fis
[12] = (now_blocks
>> 0) & 0xff;
736 fis
[13] = (now_blocks
>> 8) & 0xff;
738 /* Read/Write from ahci */
739 if (ahci_device_data_io(pccb
->target
, (u8
*) &fis
, sizeof(fis
),
740 user_buffer
, user_buffer_size
,
742 debug("scsi_ahci: SCSI %s10 command failure.\n",
743 is_write
? "WRITE" : "READ");
747 /* If this transaction is a write, do a following flush.
748 * Writes in u-boot are so rare, and the logic to know when is
749 * the last write and do a flush only there is sufficiently
750 * difficult. Just do a flush after every write. This incurs,
751 * usually, one extra flush when the rare writes do happen.
754 if (-EIO
== ata_io_flush(pccb
->target
))
757 user_buffer
+= transfer_size
;
758 user_buffer_size
-= transfer_size
;
759 blocks
-= now_blocks
;
768 * SCSI READ CAPACITY10 command operation.
770 static int ata_scsiop_read_capacity10(ccb
*pccb
)
775 if (!ataid
[pccb
->target
]) {
776 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
778 "\tPlease run SCSI commmand INQUIRY firstly!\n");
782 cap
= le32_to_cpu(ataid
[pccb
->target
]->lba_capacity
);
783 if (cap
== 0xfffffff) {
784 unsigned short *cap48
= ataid
[pccb
->target
]->lba48_capacity
;
785 if (cap48
[2] || cap48
[3]) {
788 cap
= (le16_to_cpu(cap48
[1]) << 16) |
789 (le16_to_cpu(cap48
[0]));
793 cap
= cpu_to_be32(cap
);
794 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
796 block_size
= cpu_to_be32((u32
)512);
797 memcpy(&pccb
->pdata
[4], &block_size
, 4);
804 * SCSI READ CAPACITY16 command operation.
806 static int ata_scsiop_read_capacity16(ccb
*pccb
)
811 if (!ataid
[pccb
->target
]) {
812 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
814 "\tPlease run SCSI commmand INQUIRY firstly!\n");
818 cap
= le32_to_cpu(ataid
[pccb
->target
]->lba_capacity
);
819 if (cap
== 0xfffffff) {
820 memcpy(&cap
, ataid
[pccb
->target
]->lba48_capacity
, sizeof(cap
));
821 cap
= le64_to_cpu(cap
);
824 cap
= cpu_to_be64(cap
);
825 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
827 block_size
= cpu_to_be64((u64
)512);
828 memcpy(&pccb
->pdata
[8], &block_size
, 8);
835 * SCSI TEST UNIT READY command operation.
837 static int ata_scsiop_test_unit_ready(ccb
*pccb
)
839 return (ataid
[pccb
->target
]) ? 0 : -EPERM
;
843 int scsi_exec(ccb
*pccb
)
847 switch (pccb
->cmd
[0]) {
849 ret
= ata_scsiop_read_write(pccb
, 0);
852 ret
= ata_scsiop_read_write(pccb
, 1);
854 case SCSI_RD_CAPAC10
:
855 ret
= ata_scsiop_read_capacity10(pccb
);
857 case SCSI_RD_CAPAC16
:
858 ret
= ata_scsiop_read_capacity16(pccb
);
861 ret
= ata_scsiop_test_unit_ready(pccb
);
864 ret
= ata_scsiop_inquiry(pccb
);
867 printf("Unsupport SCSI command 0x%02x\n", pccb
->cmd
[0]);
872 debug("SCSI command 0x%02x ret errno %d\n", pccb
->cmd
[0], ret
);
880 void scsi_low_level_init(int busdevfunc
)
885 #ifndef CONFIG_SCSI_AHCI_PLAT
886 ahci_init_one(busdevfunc
);
889 linkmap
= probe_ent
->link_port_map
;
891 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
892 if (((linkmap
>> i
) & 0x01)) {
893 if (ahci_port_start((u8
) i
)) {
894 printf("Can not start port %d\n", i
);
897 #ifdef CONFIG_AHCI_SETFEATURES_XFER
898 ahci_set_feature((u8
) i
);
904 #ifdef CONFIG_SCSI_AHCI_PLAT
905 int ahci_init(u32 base
)
910 memset(ataid
, 0, sizeof(ataid
));
912 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
913 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
915 probe_ent
->host_flags
= ATA_FLAG_SATA
920 probe_ent
->pio_mask
= 0x1f;
921 probe_ent
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
923 probe_ent
->mmio_base
= base
;
925 /* initialize adapter */
926 rc
= ahci_host_init(probe_ent
);
930 ahci_print_info(probe_ent
);
932 linkmap
= probe_ent
->link_port_map
;
934 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
935 if (((linkmap
>> i
) & 0x01)) {
936 if (ahci_port_start((u8
) i
)) {
937 printf("Can not start port %d\n", i
);
940 #ifdef CONFIG_AHCI_SETFEATURES_XFER
941 ahci_set_feature((u8
) i
);
951 * In the general case of generic rotating media it makes sense to have a
952 * flush capability. It probably even makes sense in the case of SSDs because
953 * one cannot always know for sure what kind of internal cache/flush mechanism
954 * is embodied therein. At first it was planned to invoke this after the last
955 * write to disk and before rebooting. In practice, knowing, a priori, which
956 * is the last write is difficult. Because writing to the disk in u-boot is
957 * very rare, this flush command will be invoked after every block write.
959 static int ata_io_flush(u8 port
)
962 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
963 volatile u8
*port_mmio
= (volatile u8
*)pp
->port_mmio
;
964 u32 cmd_fis_len
= 5; /* five dwords */
968 fis
[0] = 0x27; /* Host to device FIS. */
969 fis
[1] = 1 << 7; /* Command FIS. */
970 fis
[2] = ATA_CMD_FLUSH_EXT
;
972 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, 20);
973 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
974 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
976 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
977 WAIT_MS_FLUSH
, 0x1)) {
978 debug("scsi_ahci: flush command timeout on port %d.\n", port
);
986 void scsi_bus_reset(void)
992 void scsi_print_error(ccb
* pccb
)
994 /*The ahci error info can be read in the ahci driver*/