]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/block/ata_piix.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / drivers / block / ata_piix.c
1 /*
2 * Copyright (C) Procsys. All rights reserved.
3 * Author: Mushtaq Khan <mushtaq_k@procsys.com>
4 * <mushtaqk_921@yahoo.co.in>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 *
21 * with the reference to ata_piix driver in kernel 2.4.32
22 */
23
24 /*
25 * This file contains SATA controller and SATA drive initialization functions
26 */
27
28 #include <common.h>
29 #include <asm/io.h>
30 #include <pci.h>
31 #include <command.h>
32 #include <config.h>
33 #include <asm/byteorder.h>
34 #include <part.h>
35 #include <ide.h>
36 #include <ata.h>
37
38 extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
39 extern int curr_device;
40
41 #define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
42
43 #define SATA_DECL
44 #define DRV_DECL /*For file specific declarations */
45 #include "ata_piix.h"
46
47 /*Macros realted to PCI*/
48 #define PCI_SATA_BUS 0x00
49 #define PCI_SATA_DEV 0x1f
50 #define PCI_SATA_FUNC 0x02
51
52 #define PCI_SATA_BASE1 0x10
53 #define PCI_SATA_BASE2 0x14
54 #define PCI_SATA_BASE3 0x18
55 #define PCI_SATA_BASE4 0x1c
56 #define PCI_SATA_BASE5 0x20
57 #define PCI_PMR 0x90
58 #define PCI_PI 0x09
59 #define PCI_PCS 0x92
60 #define PCI_DMA_CTL 0x48
61
62 #define PORT_PRESENT (1<<0)
63 #define PORT_ENABLED (1<<4)
64
65 u32 bdf;
66 u32 iobase1 = 0; /*Primary cmd block */
67 u32 iobase2 = 0; /*Primary ctl block */
68 u32 iobase3 = 0; /*Sec cmd block */
69 u32 iobase4 = 0; /*sec ctl block */
70 u32 iobase5 = 0; /*BMDMA*/
71 int
72 pci_sata_init (void)
73 {
74 u32 bus = PCI_SATA_BUS;
75 u32 dev = PCI_SATA_DEV;
76 u32 fun = PCI_SATA_FUNC;
77 u16 cmd = 0;
78 u8 lat = 0, pcibios_max_latency = 0xff;
79 u8 pmr; /*Port mapping reg */
80 u8 pi; /*Prgming Interface reg */
81
82 bdf = PCI_BDF (bus, dev, fun);
83 pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
84 pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
85 pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
86 pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
87 pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
88
89 if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
90 (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
91 (iobase5 == 0xFFFFFFFF)) {
92 printf ("error no base addr for SATA controller\n");
93 return 1;
94 /*ERROR*/}
95
96 iobase1 &= 0xFFFFFFFE;
97 iobase2 &= 0xFFFFFFFE;
98 iobase3 &= 0xFFFFFFFE;
99 iobase4 &= 0xFFFFFFFE;
100 iobase5 &= 0xFFFFFFFE;
101
102 /*check for mode */
103 pci_read_config_byte (bdf, PCI_PMR, &pmr);
104 if (pmr > 1) {
105 printf ("combined mode not supported\n");
106 return 1;
107 }
108
109 pci_read_config_byte (bdf, PCI_PI, &pi);
110 if ((pi & 0x05) != 0x05) {
111 printf ("Sata is in Legacy mode\n");
112 return 1;
113 } else {
114 printf ("sata is in Native mode\n");
115 }
116
117 /*MASTER CFG AND IO CFG */
118 pci_read_config_word (bdf, PCI_COMMAND, &cmd);
119 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
120 pci_write_config_word (bdf, PCI_COMMAND, cmd);
121 pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
122
123 if (lat < 16)
124 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
125 else if (lat > pcibios_max_latency)
126 lat = pcibios_max_latency;
127 pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
128
129 return 0;
130 }
131
132 int
133 sata_bus_probe (int port_no)
134 {
135 int orig_mask, mask;
136 u16 pcs;
137
138 mask = (PORT_PRESENT << port_no);
139 pci_read_config_word (bdf, PCI_PCS, &pcs);
140 orig_mask = (int) pcs & 0xff;
141 if ((orig_mask & mask) != mask)
142 return 0;
143 else
144 return 1;
145 }
146
147 int
148 init_sata (int dev)
149 {
150 static int done = 0;
151 u8 i, rv = 0;
152
153 if (!done)
154 done = 1;
155 else
156 return 0;
157
158 rv = pci_sata_init ();
159 if (rv == 1) {
160 printf ("pci initialization failed\n");
161 return 1;
162 }
163
164 port[0].port_no = 0;
165 port[0].ioaddr.cmd_addr = iobase1;
166 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
167 iobase2 | ATA_PCI_CTL_OFS;
168 port[0].ioaddr.bmdma_addr = iobase5;
169
170 port[1].port_no = 1;
171 port[1].ioaddr.cmd_addr = iobase3;
172 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
173 iobase4 | ATA_PCI_CTL_OFS;
174 port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
175
176 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
177 sata_port (&port[i].ioaddr);
178
179 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
180 if (!(sata_bus_probe (i))) {
181 port[i].port_state = 0;
182 printf ("SATA#%d port is not present \n", i);
183 } else {
184 printf ("SATA#%d port is present\n", i);
185 if (sata_bus_softreset (i)) {
186 port[i].port_state = 0;
187 } else {
188 port[i].port_state = 1;
189 }
190 }
191 }
192
193 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
194 u8 j, devno;
195
196 if (port[i].port_state == 0)
197 continue;
198 for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
199 sata_identify (i, j);
200 set_Feature_cmd (i, j);
201 devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
202 if ((sata_dev_desc[devno].lba > 0) &&
203 (sata_dev_desc[devno].blksz > 0)) {
204 dev_print (&sata_dev_desc[devno]);
205 /* initialize partition type */
206 init_part (&sata_dev_desc[devno]);
207 if (curr_device < 0)
208 curr_device =
209 i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
210 }
211 }
212 }
213 return 0;
214 }
215
216 static u8 __inline__
217 sata_inb (unsigned long ioaddr)
218 {
219 return inb (ioaddr);
220 }
221
222 static void __inline__
223 sata_outb (unsigned char val, unsigned long ioaddr)
224 {
225 outb (val, ioaddr);
226 }
227
228 static void
229 output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
230 {
231 outsw (ioaddr->data_addr, sect_buf, words << 1);
232 }
233
234 static int
235 input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
236 {
237 insw (ioaddr->data_addr, sect_buf, words << 1);
238 return 0;
239 }
240
241 static void
242 sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
243 {
244 unsigned char *end, *last;
245
246 last = dst;
247 end = src + len - 1;
248
249 /* reserve space for '\0' */
250 if (len < 2)
251 goto OUT;
252
253 /* skip leading white space */
254 while ((*src) && (src < end) && (*src == ' '))
255 ++src;
256
257 /* copy string, omitting trailing white space */
258 while ((*src) && (src < end)) {
259 *dst++ = *src;
260 if (*src++ != ' ')
261 last = dst;
262 }
263 OUT:
264 *last = '\0';
265 }
266
267 int
268 sata_bus_softreset (int num)
269 {
270 u8 dev = 0, status = 0, i;
271
272 port[num].dev_mask = 0;
273
274 for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
275 if (!(sata_devchk (&port[num].ioaddr, i))) {
276 PRINTF ("dev_chk failed for dev#%d\n", i);
277 } else {
278 port[num].dev_mask |= (1 << i);
279 PRINTF ("dev_chk passed for dev#%d\n", i);
280 }
281 }
282
283 if (!(port[num].dev_mask)) {
284 printf ("no devices on port%d\n", num);
285 return 1;
286 }
287
288 dev_select (&port[num].ioaddr, dev);
289
290 port[num].ctl_reg = 0x08; /*Default value of control reg */
291 sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
292 udelay (10);
293 sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
294 udelay (10);
295 sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
296
297 /* spec mandates ">= 2ms" before checking status.
298 * We wait 150ms, because that was the magic delay used for
299 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
300 * between when the ATA command register is written, and then
301 * status is checked. Because waiting for "a while" before
302 * checking status is fine, post SRST, we perform this magic
303 * delay here as well.
304 */
305 msleep (150);
306 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
307 while ((status & ATA_BUSY)) {
308 msleep (100);
309 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
310 }
311
312 if (status & ATA_BUSY)
313 printf ("ata%u is slow to respond,plz be patient\n", port);
314
315 while ((status & ATA_BUSY)) {
316 msleep (100);
317 status = sata_chk_status (&port[num].ioaddr);
318 }
319
320 if (status & ATA_BUSY) {
321 printf ("ata%u failed to respond : ", port);
322 printf ("bus reset failed\n");
323 return 1;
324 }
325 return 0;
326 }
327
328 void
329 sata_identify (int num, int dev)
330 {
331 u8 cmd = 0, status = 0, devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
332 u16 iobuf[ATA_SECT_SIZE];
333 u64 n_sectors = 0;
334 u8 mask = 0;
335
336 memset (iobuf, 0, sizeof (iobuf));
337 hd_driveid_t *iop = (hd_driveid_t *) iobuf;
338
339 if (dev == 0)
340 mask = 0x01;
341 else
342 mask = 0x02;
343
344 if (!(port[num].dev_mask & mask)) {
345 printf ("dev%d is not present on port#%d\n", dev, num);
346 return;
347 }
348
349 printf ("port=%d dev=%d\n", num, dev);
350
351 dev_select (&port[num].ioaddr, dev);
352
353 status = 0;
354 cmd = ATA_CMD_IDENT; /*Device Identify Command */
355 sata_outb (cmd, port[num].ioaddr.command_addr);
356 sata_inb (port[num].ioaddr.altstatus_addr);
357 udelay (10);
358
359 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
360 if (status & ATA_ERR) {
361 printf ("\ndevice not responding\n");
362 port[num].dev_mask &= ~mask;
363 return;
364 }
365
366 input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
367
368 PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
369 "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
370 iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
371 iobuf[87], iobuf[88]);
372
373 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
374 if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
375 PRINTF ("ata%u: no dma/lba\n", num);
376 }
377 ata_dump_id (iobuf);
378
379 if (ata_id_has_lba48 (iobuf)) {
380 n_sectors = ata_id_u64 (iobuf, 100);
381 } else {
382 n_sectors = ata_id_u32 (iobuf, 60);
383 }
384 PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
385 PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
386
387 if (n_sectors == 0) {
388 port[num].dev_mask &= ~mask;
389 return;
390 }
391
392 sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev,
393 sizeof (sata_dev_desc[devno].revision));
394 sata_cpy (sata_dev_desc[devno].vendor, iop->model,
395 sizeof (sata_dev_desc[devno].vendor));
396 sata_cpy (sata_dev_desc[devno].product, iop->serial_no,
397 sizeof (sata_dev_desc[devno].product));
398 strswab (sata_dev_desc[devno].revision);
399 strswab (sata_dev_desc[devno].vendor);
400
401 if ((iop->config & 0x0080) == 0x0080) {
402 sata_dev_desc[devno].removable = 1;
403 } else {
404 sata_dev_desc[devno].removable = 0;
405 }
406
407 sata_dev_desc[devno].lba = iop->lba_capacity;
408 PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
409
410 #ifdef CONFIG_LBA48
411 if (iop->command_set_2 & 0x0400) {
412 sata_dev_desc[devno].lba48 = 1;
413 lba = (unsigned long long) iop->lba48_capacity[0] |
414 ((unsigned long long) iop->lba48_capacity[1] << 16) |
415 ((unsigned long long) iop->lba48_capacity[2] << 32) |
416 ((unsigned long long) iop->lba48_capacity[3] << 48);
417 } else {
418 sata_dev_desc[devno].lba48 = 0;
419 }
420 #endif
421
422 /* assuming HD */
423 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
424 sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
425 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
426 }
427
428 void
429 set_Feature_cmd (int num, int dev)
430 {
431 u8 mask = 0x00, status = 0;
432
433 if (dev == 0)
434 mask = 0x01;
435 else
436 mask = 0x02;
437
438 if (!(port[num].dev_mask & mask)) {
439 PRINTF ("dev%d is not present on port#%d\n", dev, num);
440 return;
441 }
442
443 dev_select (&port[num].ioaddr, dev);
444
445 sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
446 sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
447 sata_outb (0, port[num].ioaddr.lbal_addr);
448 sata_outb (0, port[num].ioaddr.lbam_addr);
449 sata_outb (0, port[num].ioaddr.lbah_addr);
450
451 sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
452 sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
453
454 udelay (50);
455 msleep (150);
456
457 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
458 if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
459 printf ("Error : status 0x%02x\n", status);
460 port[num].dev_mask &= ~mask;
461 }
462 }
463
464 void
465 sata_port (struct sata_ioports *ioport)
466 {
467 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
468 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
469 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
470 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
471 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
472 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
473 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
474 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
475 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
476 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
477 }
478
479 int
480 sata_devchk (struct sata_ioports *ioaddr, int dev)
481 {
482 u8 nsect, lbal;
483
484 dev_select (ioaddr, dev);
485
486 sata_outb (0x55, ioaddr->nsect_addr);
487 sata_outb (0xaa, ioaddr->lbal_addr);
488
489 sata_outb (0xaa, ioaddr->nsect_addr);
490 sata_outb (0x55, ioaddr->lbal_addr);
491
492 sata_outb (0x55, ioaddr->nsect_addr);
493 sata_outb (0xaa, ioaddr->lbal_addr);
494
495 nsect = sata_inb (ioaddr->nsect_addr);
496 lbal = sata_inb (ioaddr->lbal_addr);
497
498 if ((nsect == 0x55) && (lbal == 0xaa))
499 return 1; /* we found a device */
500 else
501 return 0; /* nothing found */
502 }
503
504 void
505 dev_select (struct sata_ioports *ioaddr, int dev)
506 {
507 u8 tmp = 0;
508
509 if (dev == 0)
510 tmp = ATA_DEVICE_OBS;
511 else
512 tmp = ATA_DEVICE_OBS | ATA_DEV1;
513
514 sata_outb (tmp, ioaddr->device_addr);
515 sata_inb (ioaddr->altstatus_addr);
516 udelay (5);
517 }
518
519 u8
520 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
521 {
522 u8 status;
523
524 do {
525 udelay (1000);
526 status = sata_chk_status (ioaddr);
527 max--;
528 } while ((status & bits) && (max > 0));
529
530 return status;
531 }
532
533 u8
534 sata_chk_status (struct sata_ioports * ioaddr)
535 {
536 return sata_inb (ioaddr->status_addr);
537 }
538
539 void
540 msleep (int count)
541 {
542 int i;
543
544 for (i = 0; i < count; i++)
545 udelay (1000);
546 }
547
548 ulong
549 sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
550 {
551 ulong n = 0, *buffer = (ulong *)buff;
552 u8 dev = 0, num = 0, mask = 0, status = 0;
553
554 #ifdef CONFIG_LBA48
555 unsigned char lba48 = 0;
556
557 if (blknr & 0x0000fffff0000000) {
558 if (!sata_dev_desc[devno].lba48) {
559 printf ("Drive doesn't support 48-bit addressing\n");
560 return 0;
561 }
562 /* more than 28 bits used, use 48bit mode */
563 lba48 = 1;
564 }
565 #endif
566 /*Port Number */
567 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
568 /*dev on the port */
569 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
570 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
571 else
572 dev = device;
573
574 if (dev == 0)
575 mask = 0x01;
576 else
577 mask = 0x02;
578
579 if (!(port[num].dev_mask & mask)) {
580 printf ("dev%d is not present on port#%d\n", dev, num);
581 return 0;
582 }
583
584 /* Select device */
585 dev_select (&port[num].ioaddr, dev);
586
587 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
588 if (status & ATA_BUSY) {
589 printf ("ata%u failed to respond\n", port[num].port_no);
590 return n;
591 }
592 while (blkcnt-- > 0) {
593 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
594 if (status & ATA_BUSY) {
595 printf ("ata%u failed to respond\n", 0);
596 return n;
597 }
598 #ifdef CONFIG_LBA48
599 if (lba48) {
600 /* write high bits */
601 sata_outb (0, port[num].ioaddr.nsect_addr);
602 sata_outb ((blknr >> 24) & 0xFF,
603 port[num].ioaddr.lbal_addr);
604 sata_outb ((blknr >> 32) & 0xFF,
605 port[num].ioaddr.lbam_addr);
606 sata_outb ((blknr >> 40) & 0xFF,
607 port[num].ioaddr.lbah_addr);
608 }
609 #endif
610 sata_outb (1, port[num].ioaddr.nsect_addr);
611 sata_outb (((blknr) >> 0) & 0xFF,
612 port[num].ioaddr.lbal_addr);
613 sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
614 sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
615
616 #ifdef CONFIG_LBA48
617 if (lba48) {
618 sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
619 sata_outb (ATA_CMD_READ_EXT,
620 port[num].ioaddr.command_addr);
621 } else
622 #endif
623 {
624 sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
625 port[num].ioaddr.device_addr);
626 sata_outb (ATA_CMD_READ,
627 port[num].ioaddr.command_addr);
628 }
629
630 msleep (50);
631 /*may take up to 4 sec */
632 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
633
634 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
635 != ATA_STAT_DRQ) {
636 u8 err = 0;
637
638 printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
639 device, (ulong) blknr, status);
640 err = sata_inb (port[num].ioaddr.error_addr);
641 printf ("Error reg = 0x%x\n", err);
642 return (n);
643 }
644 input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
645 sata_inb (port[num].ioaddr.altstatus_addr);
646 udelay (50);
647
648 ++n;
649 ++blknr;
650 buffer += ATA_SECTORWORDS;
651 }
652 return n;
653 }
654
655 ulong
656 sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
657 {
658 ulong n = 0, *buffer = (ulong *)buff;
659 unsigned char status = 0, num = 0, dev = 0, mask = 0;
660
661 #ifdef CONFIG_LBA48
662 unsigned char lba48 = 0;
663
664 if (blknr & 0x0000fffff0000000) {
665 if (!sata_dev_desc[devno].lba48) {
666 printf ("Drive doesn't support 48-bit addressing\n");
667 return 0;
668 }
669 /* more than 28 bits used, use 48bit mode */
670 lba48 = 1;
671 }
672 #endif
673 /*Port Number */
674 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
675 /*dev on the Port */
676 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
677 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
678 else
679 dev = device;
680
681 if (dev == 0)
682 mask = 0x01;
683 else
684 mask = 0x02;
685
686 /* Select device */
687 dev_select (&port[num].ioaddr, dev);
688
689 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
690 if (status & ATA_BUSY) {
691 printf ("ata%u failed to respond\n", port[num].port_no);
692 return n;
693 }
694
695 while (blkcnt-- > 0) {
696 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
697 if (status & ATA_BUSY) {
698 printf ("ata%u failed to respond\n",
699 port[num].port_no);
700 return n;
701 }
702 #ifdef CONFIG_LBA48
703 if (lba48) {
704 /* write high bits */
705 sata_outb (0, port[num].ioaddr.nsect_addr);
706 sata_outb ((blknr >> 24) & 0xFF,
707 port[num].ioaddr.lbal_addr);
708 sata_outb ((blknr >> 32) & 0xFF,
709 port[num].ioaddr.lbam_addr);
710 sata_outb ((blknr >> 40) & 0xFF,
711 port[num].ioaddr.lbah_addr);
712 }
713 #endif
714 sata_outb (1, port[num].ioaddr.nsect_addr);
715 sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
716 sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
717 sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
718 #ifdef CONFIG_LBA48
719 if (lba48) {
720 sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
721 sata_outb (ATA_CMD_WRITE_EXT,
722 port[num].ioaddr.command_addr);
723 } else
724 #endif
725 {
726 sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
727 port[num].ioaddr.device_addr);
728 sata_outb (ATA_CMD_WRITE,
729 port[num].ioaddr.command_addr);
730 }
731
732 msleep (50);
733 /*may take up to 4 sec */
734 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
735 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
736 != ATA_STAT_DRQ) {
737 printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
738 device, (ulong) blknr, status);
739 return (n);
740 }
741
742 output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
743 sata_inb (port[num].ioaddr.altstatus_addr);
744 udelay (50);
745
746 ++n;
747 ++blknr;
748 buffer += ATA_SECTORWORDS;
749 }
750 return n;
751 }
752
753 int scan_sata(int dev)
754 {
755 return 0;
756 }
"Das U-Boot" Source Tree