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ata_piix: Fix checkpatch issues
[people/ms/u-boot.git] / drivers / block / ata_piix.c
1 /*
2 * Copyright (C) Procsys. All rights reserved.
3 * Author: Mushtaq Khan <mushtaq_k@procsys.com>
4 * <mushtaqk_921@yahoo.co.in>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 *
21 * with the reference to ata_piix driver in kernel 2.4.32
22 */
23
24 /*
25 * This file contains SATA controller and SATA drive initialization functions
26 */
27
28 #include <common.h>
29 #include <asm/io.h>
30 #include <pci.h>
31 #include <command.h>
32 #include <config.h>
33 #include <asm/byteorder.h>
34 #include <part.h>
35 #include <ide.h>
36 #include <ata.h>
37
38 extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
39 extern int sata_curr_device;
40
41 #define DEBUG_SATA 0 /* For debug prints set DEBUG_SATA to 1 */
42
43 #define SATA_DECL
44 #define DRV_DECL /* For file specific declarations */
45 #include "ata_piix.h"
46
47 /* Macros realted to PCI */
48 #define PCI_SATA_BUS 0x00
49 #define PCI_SATA_DEV 0x1f
50 #define PCI_SATA_FUNC 0x02
51
52 #define PCI_SATA_BASE1 0x10
53 #define PCI_SATA_BASE2 0x14
54 #define PCI_SATA_BASE3 0x18
55 #define PCI_SATA_BASE4 0x1c
56 #define PCI_SATA_BASE5 0x20
57 #define PCI_PMR 0x90
58 #define PCI_PI 0x09
59 #define PCI_PCS 0x92
60 #define PCI_DMA_CTL 0x48
61
62 #define PORT_PRESENT (1<<0)
63 #define PORT_ENABLED (1<<4)
64
65 u32 bdf;
66 u32 iobase1; /* Primary cmd block */
67 u32 iobase2; /* Primary ctl block */
68 u32 iobase3; /* Sec cmd block */
69 u32 iobase4; /* sec ctl block */
70 u32 iobase5; /* BMDMA*/
71
72 int pci_sata_init(void)
73 {
74 u32 bus = PCI_SATA_BUS;
75 u32 dev = PCI_SATA_DEV;
76 u32 fun = PCI_SATA_FUNC;
77 u16 cmd = 0;
78 u8 lat = 0, pcibios_max_latency = 0xff;
79 u8 pmr; /* Port mapping reg */
80 u8 pi; /* Prgming Interface reg */
81
82 bdf = PCI_BDF(bus, dev, fun);
83 pci_read_config_dword(bdf, PCI_SATA_BASE1, &iobase1);
84 pci_read_config_dword(bdf, PCI_SATA_BASE2, &iobase2);
85 pci_read_config_dword(bdf, PCI_SATA_BASE3, &iobase3);
86 pci_read_config_dword(bdf, PCI_SATA_BASE4, &iobase4);
87 pci_read_config_dword(bdf, PCI_SATA_BASE5, &iobase5);
88
89 if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
90 (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
91 (iobase5 == 0xFFFFFFFF)) {
92 /* ERROR */
93 printf("error no base addr for SATA controller\n");
94 return 1;
95 }
96
97 iobase1 &= 0xFFFFFFFE;
98 iobase2 &= 0xFFFFFFFE;
99 iobase3 &= 0xFFFFFFFE;
100 iobase4 &= 0xFFFFFFFE;
101 iobase5 &= 0xFFFFFFFE;
102
103 /* check for mode */
104 pci_read_config_byte(bdf, PCI_PMR, &pmr);
105 if (pmr > 1) {
106 puts("combined mode not supported\n");
107 return 1;
108 }
109
110 pci_read_config_byte(bdf, PCI_PI, &pi);
111 if ((pi & 0x05) != 0x05) {
112 puts("Sata is in Legacy mode\n");
113 return 1;
114 } else
115 puts("sata is in Native mode\n");
116
117 /* MASTER CFG AND IO CFG */
118 pci_read_config_word(bdf, PCI_COMMAND, &cmd);
119 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
120 pci_write_config_word(bdf, PCI_COMMAND, cmd);
121 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
122
123 if (lat < 16)
124 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
125 else if (lat > pcibios_max_latency)
126 lat = pcibios_max_latency;
127 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
128
129 return 0;
130 }
131
132 int sata_bus_probe(int port_no)
133 {
134 int orig_mask, mask;
135 u16 pcs;
136
137 mask = (PORT_PRESENT << port_no);
138 pci_read_config_word(bdf, PCI_PCS, &pcs);
139 orig_mask = (int) pcs & 0xff;
140 if ((orig_mask & mask) != mask)
141 return 0;
142 else
143 return 1;
144 }
145
146 int init_sata(int dev)
147 {
148 static int done;
149 u8 i, rv = 0;
150
151 if (!done)
152 done = 1;
153 else
154 return 0;
155
156 rv = pci_sata_init();
157 if (rv == 1) {
158 puts("pci initialization failed\n");
159 return 1;
160 }
161
162 port[0].port_no = 0;
163 port[0].ioaddr.cmd_addr = iobase1;
164 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
165 iobase2 | ATA_PCI_CTL_OFS;
166 port[0].ioaddr.bmdma_addr = iobase5;
167
168 port[1].port_no = 1;
169 port[1].ioaddr.cmd_addr = iobase3;
170 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
171 iobase4 | ATA_PCI_CTL_OFS;
172 port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
173
174 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
175 sata_port(&port[i].ioaddr);
176
177 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
178 if (!(sata_bus_probe(i))) {
179 port[i].port_state = 0;
180 printf("SATA#%d port is not present\n", i);
181 } else {
182 printf("SATA#%d port is present\n", i);
183 if (sata_bus_softreset(i))
184 port[i].port_state = 0;
185 else
186 port[i].port_state = 1;
187 }
188 }
189
190 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
191 u8 j, devno;
192
193 if (port[i].port_state == 0)
194 continue;
195 for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
196 sata_identify(i, j);
197 set_Feature_cmd(i, j);
198 devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
199 if ((sata_dev_desc[devno].lba > 0) &&
200 (sata_dev_desc[devno].blksz > 0)) {
201 dev_print(&sata_dev_desc[devno]);
202 /* initialize partition type */
203 init_part(&sata_dev_desc[devno]);
204 }
205 }
206 }
207 return 0;
208 }
209
210 static inline u8 sata_inb(unsigned long ioaddr)
211 {
212 return inb(ioaddr);
213 }
214
215 static inline void sata_outb(unsigned char val, unsigned long ioaddr)
216 {
217 outb(val, ioaddr);
218 }
219
220 static void output_data(struct sata_ioports *ioaddr, ulong * sect_buf,
221 int words)
222 {
223 outsw(ioaddr->data_addr, sect_buf, words << 1);
224 }
225
226 static int input_data(struct sata_ioports *ioaddr, ulong * sect_buf, int words)
227 {
228 insw(ioaddr->data_addr, sect_buf, words << 1);
229 return 0;
230 }
231
232 static void sata_cpy(unsigned char *dst, unsigned char *src, unsigned int len)
233 {
234 unsigned char *end, *last;
235
236 last = dst;
237 end = src + len - 1;
238
239 /* reserve space for '\0' */
240 if (len < 2)
241 goto OUT;
242
243 /* skip leading white space */
244 while ((*src) && (src < end) && (*src == ' '))
245 ++src;
246
247 /* copy string, omitting trailing white space */
248 while ((*src) && (src < end)) {
249 *dst++ = *src;
250 if (*src++ != ' ')
251 last = dst;
252 }
253 OUT:
254 *last = '\0';
255 }
256
257 int sata_bus_softreset(int num)
258 {
259 u8 dev = 0, status = 0, i;
260
261 port[num].dev_mask = 0;
262
263 for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
264 if (!(sata_devchk(&port[num].ioaddr, i))) {
265 debug("dev_chk failed for dev#%d\n", i);
266 } else {
267 port[num].dev_mask |= (1 << i);
268 debug("dev_chk passed for dev#%d\n", i);
269 }
270 }
271
272 if (!(port[num].dev_mask)) {
273 printf("no devices on port%d\n", num);
274 return 1;
275 }
276
277 dev_select(&port[num].ioaddr, dev);
278
279 port[num].ctl_reg = 0x08; /* Default value of control reg */
280 sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
281 udelay(10);
282 sata_outb(port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
283 udelay(10);
284 sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
285
286 /*
287 * spec mandates ">= 2ms" before checking status.
288 * We wait 150ms, because that was the magic delay used for
289 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
290 * between when the ATA command register is written, and then
291 * status is checked. Because waiting for "a while" before
292 * checking status is fine, post SRST, we perform this magic
293 * delay here as well.
294 */
295 mdelay(150);
296 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 300);
297 while ((status & ATA_BUSY)) {
298 mdelay(100);
299 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 3);
300 }
301
302 if (status & ATA_BUSY)
303 printf("ata%u is slow to respond,plz be patient\n", num);
304
305 while ((status & ATA_BUSY)) {
306 mdelay(100);
307 status = sata_chk_status(&port[num].ioaddr);
308 }
309
310 if (status & ATA_BUSY) {
311 printf("ata%u failed to respond : bus reset failed\n", num);
312 return 1;
313 }
314 return 0;
315 }
316
317 void sata_identify(int num, int dev)
318 {
319 u8 cmd = 0, status = 0;
320 u8 devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
321 u16 iobuf[ATA_SECT_SIZE];
322 u64 n_sectors = 0;
323 u8 mask = 0;
324
325 memset(iobuf, 0, sizeof(iobuf));
326 hd_driveid_t *iop = (hd_driveid_t *) iobuf;
327
328 if (dev == 0)
329 mask = 0x01;
330 else
331 mask = 0x02;
332
333 if (!(port[num].dev_mask & mask)) {
334 printf("dev%d is not present on port#%d\n", dev, num);
335 return;
336 }
337
338 printf("port=%d dev=%d\n", num, dev);
339
340 dev_select(&port[num].ioaddr, dev);
341
342 status = 0;
343 cmd = ATA_CMD_IDENT; /* Device Identify Command */
344 sata_outb(cmd, port[num].ioaddr.command_addr);
345 sata_inb(port[num].ioaddr.altstatus_addr);
346 udelay(10);
347
348 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 1000);
349 if (status & ATA_ERR) {
350 puts("\ndevice not responding\n");
351 port[num].dev_mask &= ~mask;
352 return;
353 }
354
355 input_data(&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
356
357 debug("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
358 "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
359 iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
360 iobuf[87], iobuf[88]);
361
362 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
363 if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
364 debug("ata%u: no dma/lba\n", num);
365 ata_dump_id(iobuf);
366
367 if (ata_id_has_lba48(iobuf))
368 n_sectors = ata_id_u64(iobuf, 100);
369 else
370 n_sectors = ata_id_u32(iobuf, 60);
371 debug("no. of sectors %u\n", ata_id_u64(iobuf, 100));
372 debug("no. of sectors %u\n", ata_id_u32(iobuf, 60));
373
374 if (n_sectors == 0) {
375 port[num].dev_mask &= ~mask;
376 return;
377 }
378
379 sata_cpy((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
380 sizeof(sata_dev_desc[devno].revision));
381 sata_cpy((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
382 sizeof(sata_dev_desc[devno].vendor));
383 sata_cpy((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
384 sizeof(sata_dev_desc[devno].product));
385 strswab(sata_dev_desc[devno].revision);
386 strswab(sata_dev_desc[devno].vendor);
387
388 if ((iop->config & 0x0080) == 0x0080)
389 sata_dev_desc[devno].removable = 1;
390 else
391 sata_dev_desc[devno].removable = 0;
392
393 sata_dev_desc[devno].lba = iop->lba_capacity;
394 debug("lba=0x%x", sata_dev_desc[devno].lba);
395
396 #ifdef CONFIG_LBA48
397 if (iop->command_set_2 & 0x0400) {
398 sata_dev_desc[devno].lba48 = 1;
399 lba = (unsigned long long) iop->lba48_capacity[0] |
400 ((unsigned long long) iop->lba48_capacity[1] << 16) |
401 ((unsigned long long) iop->lba48_capacity[2] << 32) |
402 ((unsigned long long) iop->lba48_capacity[3] << 48);
403 } else {
404 sata_dev_desc[devno].lba48 = 0;
405 }
406 #endif
407
408 /* assuming HD */
409 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
410 sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
411 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
412 }
413
414 void set_Feature_cmd(int num, int dev)
415 {
416 u8 mask = 0x00, status = 0;
417
418 if (dev == 0)
419 mask = 0x01;
420 else
421 mask = 0x02;
422
423 if (!(port[num].dev_mask & mask)) {
424 debug("dev%d is not present on port#%d\n", dev, num);
425 return;
426 }
427
428 dev_select(&port[num].ioaddr, dev);
429
430 sata_outb(SETFEATURES_XFER, port[num].ioaddr.feature_addr);
431 sata_outb(XFER_PIO_4, port[num].ioaddr.nsect_addr);
432 sata_outb(0, port[num].ioaddr.lbal_addr);
433 sata_outb(0, port[num].ioaddr.lbam_addr);
434 sata_outb(0, port[num].ioaddr.lbah_addr);
435
436 sata_outb(ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
437 sata_outb(ATA_CMD_SETF, port[num].ioaddr.command_addr);
438
439 udelay(50);
440 mdelay(150);
441
442 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 5000);
443 if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
444 printf("Error : status 0x%02x\n", status);
445 port[num].dev_mask &= ~mask;
446 }
447 }
448
449 void sata_port(struct sata_ioports *ioport)
450 {
451 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
452 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
453 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
454 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
455 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
456 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
457 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
458 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
459 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
460 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
461 }
462
463 int sata_devchk(struct sata_ioports *ioaddr, int dev)
464 {
465 u8 nsect, lbal;
466
467 dev_select(ioaddr, dev);
468
469 sata_outb(0x55, ioaddr->nsect_addr);
470 sata_outb(0xaa, ioaddr->lbal_addr);
471
472 sata_outb(0xaa, ioaddr->nsect_addr);
473 sata_outb(0x55, ioaddr->lbal_addr);
474
475 sata_outb(0x55, ioaddr->nsect_addr);
476 sata_outb(0xaa, ioaddr->lbal_addr);
477
478 nsect = sata_inb(ioaddr->nsect_addr);
479 lbal = sata_inb(ioaddr->lbal_addr);
480
481 if ((nsect == 0x55) && (lbal == 0xaa))
482 return 1; /* we found a device */
483 else
484 return 0; /* nothing found */
485 }
486
487 void dev_select(struct sata_ioports *ioaddr, int dev)
488 {
489 u8 tmp = 0;
490
491 if (dev == 0)
492 tmp = ATA_DEVICE_OBS;
493 else
494 tmp = ATA_DEVICE_OBS | ATA_DEV1;
495
496 sata_outb(tmp, ioaddr->device_addr);
497 sata_inb(ioaddr->altstatus_addr);
498 udelay(5);
499 }
500
501 u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max)
502 {
503 u8 status;
504
505 do {
506 udelay(1000);
507 status = sata_chk_status(ioaddr);
508 max--;
509 } while ((status & bits) && (max > 0));
510
511 return status;
512 }
513
514 u8 sata_chk_status(struct sata_ioports *ioaddr)
515 {
516 return sata_inb(ioaddr->status_addr);
517 }
518
519
520 ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buff)
521 {
522 ulong n = 0, *buffer = (ulong *)buff;
523 u8 dev = 0, num = 0, mask = 0, status = 0;
524
525 #ifdef CONFIG_LBA48
526 unsigned char lba48 = 0;
527
528 if (blknr & 0x0000fffff0000000) {
529 if (!sata_dev_desc[devno].lba48) {
530 printf("Drive doesn't support 48-bit addressing\n");
531 return 0;
532 }
533 /* more than 28 bits used, use 48bit mode */
534 lba48 = 1;
535 }
536 #endif
537 /* Port Number */
538 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
539 /* dev on the port */
540 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
541 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
542 else
543 dev = device;
544
545 if (dev == 0)
546 mask = 0x01;
547 else
548 mask = 0x02;
549
550 if (!(port[num].dev_mask & mask)) {
551 printf("dev%d is not present on port#%d\n", dev, num);
552 return 0;
553 }
554
555 /* Select device */
556 dev_select(&port[num].ioaddr, dev);
557
558 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
559 if (status & ATA_BUSY) {
560 printf("ata%u failed to respond\n", port[num].port_no);
561 return n;
562 }
563 while (blkcnt-- > 0) {
564 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
565 if (status & ATA_BUSY) {
566 printf("ata%u failed to respond\n", 0);
567 return n;
568 }
569 #ifdef CONFIG_LBA48
570 if (lba48) {
571 /* write high bits */
572 sata_outb(0, port[num].ioaddr.nsect_addr);
573 sata_outb((blknr >> 24) & 0xFF,
574 port[num].ioaddr.lbal_addr);
575 sata_outb((blknr >> 32) & 0xFF,
576 port[num].ioaddr.lbam_addr);
577 sata_outb((blknr >> 40) & 0xFF,
578 port[num].ioaddr.lbah_addr);
579 }
580 #endif
581 sata_outb(1, port[num].ioaddr.nsect_addr);
582 sata_outb(((blknr) >> 0) & 0xFF,
583 port[num].ioaddr.lbal_addr);
584 sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
585 sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
586
587 #ifdef CONFIG_LBA48
588 if (lba48) {
589 sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
590 sata_outb(ATA_CMD_READ_EXT,
591 port[num].ioaddr.command_addr);
592 } else
593 #endif
594 {
595 sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
596 port[num].ioaddr.device_addr);
597 sata_outb(ATA_CMD_READ,
598 port[num].ioaddr.command_addr);
599 }
600
601 mdelay(50);
602 /* may take up to 4 sec */
603 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
604
605 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
606 != ATA_STAT_DRQ) {
607 u8 err = 0;
608
609 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
610 device, (ulong) blknr, status);
611 err = sata_inb(port[num].ioaddr.error_addr);
612 printf("Error reg = 0x%x\n", err);
613 return n;
614 }
615 input_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
616 sata_inb(port[num].ioaddr.altstatus_addr);
617 udelay(50);
618
619 ++n;
620 ++blknr;
621 buffer += ATA_SECTORWORDS;
622 }
623 return n;
624 }
625
626 ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, void *buff)
627 {
628 ulong n = 0, *buffer = (ulong *)buff;
629 unsigned char status = 0, num = 0, dev = 0, mask = 0;
630
631 #ifdef CONFIG_LBA48
632 unsigned char lba48 = 0;
633
634 if (blknr & 0x0000fffff0000000) {
635 if (!sata_dev_desc[devno].lba48) {
636 printf("Drive doesn't support 48-bit addressing\n");
637 return 0;
638 }
639 /* more than 28 bits used, use 48bit mode */
640 lba48 = 1;
641 }
642 #endif
643 /* Port Number */
644 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
645 /* dev on the Port */
646 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
647 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
648 else
649 dev = device;
650
651 if (dev == 0)
652 mask = 0x01;
653 else
654 mask = 0x02;
655
656 /* Select device */
657 dev_select(&port[num].ioaddr, dev);
658
659 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
660 if (status & ATA_BUSY) {
661 printf("ata%u failed to respond\n", port[num].port_no);
662 return n;
663 }
664
665 while (blkcnt-- > 0) {
666 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
667 if (status & ATA_BUSY) {
668 printf("ata%u failed to respond\n",
669 port[num].port_no);
670 return n;
671 }
672 #ifdef CONFIG_LBA48
673 if (lba48) {
674 /* write high bits */
675 sata_outb(0, port[num].ioaddr.nsect_addr);
676 sata_outb((blknr >> 24) & 0xFF,
677 port[num].ioaddr.lbal_addr);
678 sata_outb((blknr >> 32) & 0xFF,
679 port[num].ioaddr.lbam_addr);
680 sata_outb((blknr >> 40) & 0xFF,
681 port[num].ioaddr.lbah_addr);
682 }
683 #endif
684 sata_outb(1, port[num].ioaddr.nsect_addr);
685 sata_outb((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
686 sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
687 sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
688 #ifdef CONFIG_LBA48
689 if (lba48) {
690 sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
691 sata_outb(ATA_CMD_WRITE_EXT,
692 port[num].ioaddr.command_addr);
693 } else
694 #endif
695 {
696 sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
697 port[num].ioaddr.device_addr);
698 sata_outb(ATA_CMD_WRITE,
699 port[num].ioaddr.command_addr);
700 }
701
702 mdelay(50);
703 /* may take up to 4 sec */
704 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
705 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
706 != ATA_STAT_DRQ) {
707 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
708 device, (ulong) blknr, status);
709 return n;
710 }
711
712 output_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
713 sata_inb(port[num].ioaddr.altstatus_addr);
714 udelay(50);
715
716 ++n;
717 ++blknr;
718 buffer += ATA_SECTORWORDS;
719 }
720 return n;
721 }
722
723 int scan_sata(int dev)
724 {
725 return 0;
726 }
"Das U-Boot" Source Tree