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remove unnecessary code in ata_piix
[people/ms/u-boot.git] / drivers / block / ata_piix.c
1 /*
2 * Copyright (C) Procsys. All rights reserved.
3 * Author: Mushtaq Khan <mushtaq_k@procsys.com>
4 * <mushtaqk_921@yahoo.co.in>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 *
21 * with the reference to ata_piix driver in kernel 2.4.32
22 */
23
24 /*
25 * This file contains SATA controller and SATA drive initialization functions
26 */
27
28 #include <common.h>
29 #include <asm/io.h>
30 #include <pci.h>
31 #include <command.h>
32 #include <config.h>
33 #include <asm/byteorder.h>
34 #include <part.h>
35 #include <ide.h>
36 #include <ata.h>
37
38 extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
39 extern int sata_curr_device;
40
41 #define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
42
43 #define SATA_DECL
44 #define DRV_DECL /*For file specific declarations */
45 #include "ata_piix.h"
46
47 /*Macros realted to PCI*/
48 #define PCI_SATA_BUS 0x00
49 #define PCI_SATA_DEV 0x1f
50 #define PCI_SATA_FUNC 0x02
51
52 #define PCI_SATA_BASE1 0x10
53 #define PCI_SATA_BASE2 0x14
54 #define PCI_SATA_BASE3 0x18
55 #define PCI_SATA_BASE4 0x1c
56 #define PCI_SATA_BASE5 0x20
57 #define PCI_PMR 0x90
58 #define PCI_PI 0x09
59 #define PCI_PCS 0x92
60 #define PCI_DMA_CTL 0x48
61
62 #define PORT_PRESENT (1<<0)
63 #define PORT_ENABLED (1<<4)
64
65 u32 bdf;
66 u32 iobase1 = 0; /*Primary cmd block */
67 u32 iobase2 = 0; /*Primary ctl block */
68 u32 iobase3 = 0; /*Sec cmd block */
69 u32 iobase4 = 0; /*sec ctl block */
70 u32 iobase5 = 0; /*BMDMA*/
71 int
72 pci_sata_init (void)
73 {
74 u32 bus = PCI_SATA_BUS;
75 u32 dev = PCI_SATA_DEV;
76 u32 fun = PCI_SATA_FUNC;
77 u16 cmd = 0;
78 u8 lat = 0, pcibios_max_latency = 0xff;
79 u8 pmr; /*Port mapping reg */
80 u8 pi; /*Prgming Interface reg */
81
82 bdf = PCI_BDF (bus, dev, fun);
83 pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
84 pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
85 pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
86 pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
87 pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
88
89 if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
90 (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
91 (iobase5 == 0xFFFFFFFF)) {
92 printf ("error no base addr for SATA controller\n");
93 return 1;
94 /*ERROR*/}
95
96 iobase1 &= 0xFFFFFFFE;
97 iobase2 &= 0xFFFFFFFE;
98 iobase3 &= 0xFFFFFFFE;
99 iobase4 &= 0xFFFFFFFE;
100 iobase5 &= 0xFFFFFFFE;
101
102 /*check for mode */
103 pci_read_config_byte (bdf, PCI_PMR, &pmr);
104 if (pmr > 1) {
105 printf ("combined mode not supported\n");
106 return 1;
107 }
108
109 pci_read_config_byte (bdf, PCI_PI, &pi);
110 if ((pi & 0x05) != 0x05) {
111 printf ("Sata is in Legacy mode\n");
112 return 1;
113 } else {
114 printf ("sata is in Native mode\n");
115 }
116
117 /*MASTER CFG AND IO CFG */
118 pci_read_config_word (bdf, PCI_COMMAND, &cmd);
119 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
120 pci_write_config_word (bdf, PCI_COMMAND, cmd);
121 pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
122
123 if (lat < 16)
124 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
125 else if (lat > pcibios_max_latency)
126 lat = pcibios_max_latency;
127 pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
128
129 return 0;
130 }
131
132 int
133 sata_bus_probe (int port_no)
134 {
135 int orig_mask, mask;
136 u16 pcs;
137
138 mask = (PORT_PRESENT << port_no);
139 pci_read_config_word (bdf, PCI_PCS, &pcs);
140 orig_mask = (int) pcs & 0xff;
141 if ((orig_mask & mask) != mask)
142 return 0;
143 else
144 return 1;
145 }
146
147 int
148 init_sata (int dev)
149 {
150 static int done = 0;
151 u8 i, rv = 0;
152
153 if (!done)
154 done = 1;
155 else
156 return 0;
157
158 rv = pci_sata_init ();
159 if (rv == 1) {
160 printf ("pci initialization failed\n");
161 return 1;
162 }
163
164 port[0].port_no = 0;
165 port[0].ioaddr.cmd_addr = iobase1;
166 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
167 iobase2 | ATA_PCI_CTL_OFS;
168 port[0].ioaddr.bmdma_addr = iobase5;
169
170 port[1].port_no = 1;
171 port[1].ioaddr.cmd_addr = iobase3;
172 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
173 iobase4 | ATA_PCI_CTL_OFS;
174 port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
175
176 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
177 sata_port (&port[i].ioaddr);
178
179 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
180 if (!(sata_bus_probe (i))) {
181 port[i].port_state = 0;
182 printf ("SATA#%d port is not present \n", i);
183 } else {
184 printf ("SATA#%d port is present\n", i);
185 if (sata_bus_softreset (i)) {
186 port[i].port_state = 0;
187 } else {
188 port[i].port_state = 1;
189 }
190 }
191 }
192
193 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
194 u8 j, devno;
195
196 if (port[i].port_state == 0)
197 continue;
198 for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
199 sata_identify (i, j);
200 set_Feature_cmd (i, j);
201 devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
202 if ((sata_dev_desc[devno].lba > 0) &&
203 (sata_dev_desc[devno].blksz > 0)) {
204 dev_print (&sata_dev_desc[devno]);
205 /* initialize partition type */
206 init_part (&sata_dev_desc[devno]);
207 }
208 }
209 }
210 return 0;
211 }
212
213 static u8 __inline__
214 sata_inb (unsigned long ioaddr)
215 {
216 return inb (ioaddr);
217 }
218
219 static void __inline__
220 sata_outb (unsigned char val, unsigned long ioaddr)
221 {
222 outb (val, ioaddr);
223 }
224
225 static void
226 output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
227 {
228 outsw (ioaddr->data_addr, sect_buf, words << 1);
229 }
230
231 static int
232 input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
233 {
234 insw (ioaddr->data_addr, sect_buf, words << 1);
235 return 0;
236 }
237
238 static void
239 sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
240 {
241 unsigned char *end, *last;
242
243 last = dst;
244 end = src + len - 1;
245
246 /* reserve space for '\0' */
247 if (len < 2)
248 goto OUT;
249
250 /* skip leading white space */
251 while ((*src) && (src < end) && (*src == ' '))
252 ++src;
253
254 /* copy string, omitting trailing white space */
255 while ((*src) && (src < end)) {
256 *dst++ = *src;
257 if (*src++ != ' ')
258 last = dst;
259 }
260 OUT:
261 *last = '\0';
262 }
263
264 int
265 sata_bus_softreset (int num)
266 {
267 u8 dev = 0, status = 0, i;
268
269 port[num].dev_mask = 0;
270
271 for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
272 if (!(sata_devchk (&port[num].ioaddr, i))) {
273 PRINTF ("dev_chk failed for dev#%d\n", i);
274 } else {
275 port[num].dev_mask |= (1 << i);
276 PRINTF ("dev_chk passed for dev#%d\n", i);
277 }
278 }
279
280 if (!(port[num].dev_mask)) {
281 printf ("no devices on port%d\n", num);
282 return 1;
283 }
284
285 dev_select (&port[num].ioaddr, dev);
286
287 port[num].ctl_reg = 0x08; /*Default value of control reg */
288 sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
289 udelay (10);
290 sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
291 udelay (10);
292 sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
293
294 /* spec mandates ">= 2ms" before checking status.
295 * We wait 150ms, because that was the magic delay used for
296 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
297 * between when the ATA command register is written, and then
298 * status is checked. Because waiting for "a while" before
299 * checking status is fine, post SRST, we perform this magic
300 * delay here as well.
301 */
302 msleep (150);
303 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
304 while ((status & ATA_BUSY)) {
305 msleep (100);
306 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
307 }
308
309 if (status & ATA_BUSY)
310 printf ("ata%u is slow to respond,plz be patient\n", num);
311
312 while ((status & ATA_BUSY)) {
313 msleep (100);
314 status = sata_chk_status (&port[num].ioaddr);
315 }
316
317 if (status & ATA_BUSY) {
318 printf ("ata%u failed to respond : ", num);
319 printf ("bus reset failed\n");
320 return 1;
321 }
322 return 0;
323 }
324
325 void
326 sata_identify (int num, int dev)
327 {
328 u8 cmd = 0, status = 0, devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
329 u16 iobuf[ATA_SECT_SIZE];
330 u64 n_sectors = 0;
331 u8 mask = 0;
332
333 memset (iobuf, 0, sizeof (iobuf));
334 hd_driveid_t *iop = (hd_driveid_t *) iobuf;
335
336 if (dev == 0)
337 mask = 0x01;
338 else
339 mask = 0x02;
340
341 if (!(port[num].dev_mask & mask)) {
342 printf ("dev%d is not present on port#%d\n", dev, num);
343 return;
344 }
345
346 printf ("port=%d dev=%d\n", num, dev);
347
348 dev_select (&port[num].ioaddr, dev);
349
350 status = 0;
351 cmd = ATA_CMD_IDENT; /*Device Identify Command */
352 sata_outb (cmd, port[num].ioaddr.command_addr);
353 sata_inb (port[num].ioaddr.altstatus_addr);
354 udelay (10);
355
356 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
357 if (status & ATA_ERR) {
358 printf ("\ndevice not responding\n");
359 port[num].dev_mask &= ~mask;
360 return;
361 }
362
363 input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
364
365 PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
366 "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
367 iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
368 iobuf[87], iobuf[88]);
369
370 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
371 if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
372 PRINTF ("ata%u: no dma/lba\n", num);
373 }
374 ata_dump_id (iobuf);
375
376 if (ata_id_has_lba48 (iobuf)) {
377 n_sectors = ata_id_u64 (iobuf, 100);
378 } else {
379 n_sectors = ata_id_u32 (iobuf, 60);
380 }
381 PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
382 PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
383
384 if (n_sectors == 0) {
385 port[num].dev_mask &= ~mask;
386 return;
387 }
388
389 sata_cpy ((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
390 sizeof (sata_dev_desc[devno].revision));
391 sata_cpy ((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
392 sizeof (sata_dev_desc[devno].vendor));
393 sata_cpy ((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
394 sizeof (sata_dev_desc[devno].product));
395 strswab (sata_dev_desc[devno].revision);
396 strswab (sata_dev_desc[devno].vendor);
397
398 if ((iop->config & 0x0080) == 0x0080) {
399 sata_dev_desc[devno].removable = 1;
400 } else {
401 sata_dev_desc[devno].removable = 0;
402 }
403
404 sata_dev_desc[devno].lba = iop->lba_capacity;
405 PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
406
407 #ifdef CONFIG_LBA48
408 if (iop->command_set_2 & 0x0400) {
409 sata_dev_desc[devno].lba48 = 1;
410 lba = (unsigned long long) iop->lba48_capacity[0] |
411 ((unsigned long long) iop->lba48_capacity[1] << 16) |
412 ((unsigned long long) iop->lba48_capacity[2] << 32) |
413 ((unsigned long long) iop->lba48_capacity[3] << 48);
414 } else {
415 sata_dev_desc[devno].lba48 = 0;
416 }
417 #endif
418
419 /* assuming HD */
420 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
421 sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
422 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
423 }
424
425 void
426 set_Feature_cmd (int num, int dev)
427 {
428 u8 mask = 0x00, status = 0;
429
430 if (dev == 0)
431 mask = 0x01;
432 else
433 mask = 0x02;
434
435 if (!(port[num].dev_mask & mask)) {
436 PRINTF ("dev%d is not present on port#%d\n", dev, num);
437 return;
438 }
439
440 dev_select (&port[num].ioaddr, dev);
441
442 sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
443 sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
444 sata_outb (0, port[num].ioaddr.lbal_addr);
445 sata_outb (0, port[num].ioaddr.lbam_addr);
446 sata_outb (0, port[num].ioaddr.lbah_addr);
447
448 sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
449 sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
450
451 udelay (50);
452 msleep (150);
453
454 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
455 if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
456 printf ("Error : status 0x%02x\n", status);
457 port[num].dev_mask &= ~mask;
458 }
459 }
460
461 void
462 sata_port (struct sata_ioports *ioport)
463 {
464 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
465 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
466 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
467 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
468 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
469 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
470 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
471 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
472 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
473 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
474 }
475
476 int
477 sata_devchk (struct sata_ioports *ioaddr, int dev)
478 {
479 u8 nsect, lbal;
480
481 dev_select (ioaddr, dev);
482
483 sata_outb (0x55, ioaddr->nsect_addr);
484 sata_outb (0xaa, ioaddr->lbal_addr);
485
486 sata_outb (0xaa, ioaddr->nsect_addr);
487 sata_outb (0x55, ioaddr->lbal_addr);
488
489 sata_outb (0x55, ioaddr->nsect_addr);
490 sata_outb (0xaa, ioaddr->lbal_addr);
491
492 nsect = sata_inb (ioaddr->nsect_addr);
493 lbal = sata_inb (ioaddr->lbal_addr);
494
495 if ((nsect == 0x55) && (lbal == 0xaa))
496 return 1; /* we found a device */
497 else
498 return 0; /* nothing found */
499 }
500
501 void
502 dev_select (struct sata_ioports *ioaddr, int dev)
503 {
504 u8 tmp = 0;
505
506 if (dev == 0)
507 tmp = ATA_DEVICE_OBS;
508 else
509 tmp = ATA_DEVICE_OBS | ATA_DEV1;
510
511 sata_outb (tmp, ioaddr->device_addr);
512 sata_inb (ioaddr->altstatus_addr);
513 udelay (5);
514 }
515
516 u8
517 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
518 {
519 u8 status;
520
521 do {
522 udelay (1000);
523 status = sata_chk_status (ioaddr);
524 max--;
525 } while ((status & bits) && (max > 0));
526
527 return status;
528 }
529
530 u8
531 sata_chk_status (struct sata_ioports * ioaddr)
532 {
533 return sata_inb (ioaddr->status_addr);
534 }
535
536 void
537 msleep (int count)
538 {
539 int i;
540
541 for (i = 0; i < count; i++)
542 udelay (1000);
543 }
544
545 ulong
546 sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
547 {
548 ulong n = 0, *buffer = (ulong *)buff;
549 u8 dev = 0, num = 0, mask = 0, status = 0;
550
551 #ifdef CONFIG_LBA48
552 unsigned char lba48 = 0;
553
554 if (blknr & 0x0000fffff0000000) {
555 if (!sata_dev_desc[devno].lba48) {
556 printf ("Drive doesn't support 48-bit addressing\n");
557 return 0;
558 }
559 /* more than 28 bits used, use 48bit mode */
560 lba48 = 1;
561 }
562 #endif
563 /*Port Number */
564 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
565 /*dev on the port */
566 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
567 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
568 else
569 dev = device;
570
571 if (dev == 0)
572 mask = 0x01;
573 else
574 mask = 0x02;
575
576 if (!(port[num].dev_mask & mask)) {
577 printf ("dev%d is not present on port#%d\n", dev, num);
578 return 0;
579 }
580
581 /* Select device */
582 dev_select (&port[num].ioaddr, dev);
583
584 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
585 if (status & ATA_BUSY) {
586 printf ("ata%u failed to respond\n", port[num].port_no);
587 return n;
588 }
589 while (blkcnt-- > 0) {
590 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
591 if (status & ATA_BUSY) {
592 printf ("ata%u failed to respond\n", 0);
593 return n;
594 }
595 #ifdef CONFIG_LBA48
596 if (lba48) {
597 /* write high bits */
598 sata_outb (0, port[num].ioaddr.nsect_addr);
599 sata_outb ((blknr >> 24) & 0xFF,
600 port[num].ioaddr.lbal_addr);
601 sata_outb ((blknr >> 32) & 0xFF,
602 port[num].ioaddr.lbam_addr);
603 sata_outb ((blknr >> 40) & 0xFF,
604 port[num].ioaddr.lbah_addr);
605 }
606 #endif
607 sata_outb (1, port[num].ioaddr.nsect_addr);
608 sata_outb (((blknr) >> 0) & 0xFF,
609 port[num].ioaddr.lbal_addr);
610 sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
611 sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
612
613 #ifdef CONFIG_LBA48
614 if (lba48) {
615 sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
616 sata_outb (ATA_CMD_READ_EXT,
617 port[num].ioaddr.command_addr);
618 } else
619 #endif
620 {
621 sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
622 port[num].ioaddr.device_addr);
623 sata_outb (ATA_CMD_READ,
624 port[num].ioaddr.command_addr);
625 }
626
627 msleep (50);
628 /*may take up to 4 sec */
629 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
630
631 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
632 != ATA_STAT_DRQ) {
633 u8 err = 0;
634
635 printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
636 device, (ulong) blknr, status);
637 err = sata_inb (port[num].ioaddr.error_addr);
638 printf ("Error reg = 0x%x\n", err);
639 return (n);
640 }
641 input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
642 sata_inb (port[num].ioaddr.altstatus_addr);
643 udelay (50);
644
645 ++n;
646 ++blknr;
647 buffer += ATA_SECTORWORDS;
648 }
649 return n;
650 }
651
652 ulong
653 sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
654 {
655 ulong n = 0, *buffer = (ulong *)buff;
656 unsigned char status = 0, num = 0, dev = 0, mask = 0;
657
658 #ifdef CONFIG_LBA48
659 unsigned char lba48 = 0;
660
661 if (blknr & 0x0000fffff0000000) {
662 if (!sata_dev_desc[devno].lba48) {
663 printf ("Drive doesn't support 48-bit addressing\n");
664 return 0;
665 }
666 /* more than 28 bits used, use 48bit mode */
667 lba48 = 1;
668 }
669 #endif
670 /*Port Number */
671 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
672 /*dev on the Port */
673 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
674 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
675 else
676 dev = device;
677
678 if (dev == 0)
679 mask = 0x01;
680 else
681 mask = 0x02;
682
683 /* Select device */
684 dev_select (&port[num].ioaddr, dev);
685
686 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
687 if (status & ATA_BUSY) {
688 printf ("ata%u failed to respond\n", port[num].port_no);
689 return n;
690 }
691
692 while (blkcnt-- > 0) {
693 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
694 if (status & ATA_BUSY) {
695 printf ("ata%u failed to respond\n",
696 port[num].port_no);
697 return n;
698 }
699 #ifdef CONFIG_LBA48
700 if (lba48) {
701 /* write high bits */
702 sata_outb (0, port[num].ioaddr.nsect_addr);
703 sata_outb ((blknr >> 24) & 0xFF,
704 port[num].ioaddr.lbal_addr);
705 sata_outb ((blknr >> 32) & 0xFF,
706 port[num].ioaddr.lbam_addr);
707 sata_outb ((blknr >> 40) & 0xFF,
708 port[num].ioaddr.lbah_addr);
709 }
710 #endif
711 sata_outb (1, port[num].ioaddr.nsect_addr);
712 sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
713 sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
714 sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
715 #ifdef CONFIG_LBA48
716 if (lba48) {
717 sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
718 sata_outb (ATA_CMD_WRITE_EXT,
719 port[num].ioaddr.command_addr);
720 } else
721 #endif
722 {
723 sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
724 port[num].ioaddr.device_addr);
725 sata_outb (ATA_CMD_WRITE,
726 port[num].ioaddr.command_addr);
727 }
728
729 msleep (50);
730 /*may take up to 4 sec */
731 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
732 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
733 != ATA_STAT_DRQ) {
734 printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
735 device, (ulong) blknr, status);
736 return (n);
737 }
738
739 output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
740 sata_inb (port[num].ioaddr.altstatus_addr);
741 udelay (50);
742
743 ++n;
744 ++blknr;
745 buffer += ATA_SECTORWORDS;
746 }
747 return n;
748 }
749
750 int scan_sata(int dev)
751 {
752 return 0;
753 }
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