2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <linux/ctype.h>
16 #include <asm/errno.h>
18 #include <linux/bitops.h>
19 #include <asm/arch/clock.h>
20 #include "dwc_ahsata.h"
22 struct sata_port_regs
{
46 struct sata_host_regs
{
75 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
76 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
78 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
82 static inline u32
ahci_port_base(u32 base
, u32 port
)
84 return base
+ 0x100 + (port
* 0x80);
87 static int waiting_for_cmd_completed(u8
*offset
,
95 ((status
= readl(offset
)) & sign
) && i
< timeout_msec
;
99 return (i
< timeout_msec
) ? 0 : -1;
102 static int ahci_setup_oobr(struct ahci_probe_ent
*probe_ent
,
105 struct sata_host_regs
*host_mmio
=
106 (struct sata_host_regs
*)probe_ent
->mmio_base
;
108 writel(SATA_HOST_OOBR_WE
, &(host_mmio
->oobr
));
109 writel(0x02060b14, &(host_mmio
->oobr
));
114 static int ahci_host_init(struct ahci_probe_ent
*probe_ent
)
116 u32 tmp
, cap_save
, num_ports
;
117 int i
, j
, timeout
= 1000;
118 struct sata_port_regs
*port_mmio
= NULL
;
119 struct sata_host_regs
*host_mmio
=
120 (struct sata_host_regs
*)probe_ent
->mmio_base
;
121 int clk
= mxc_get_clock(MXC_SATA_CLK
);
123 cap_save
= readl(&(host_mmio
->cap
));
124 cap_save
|= SATA_HOST_CAP_SSS
;
126 /* global controller reset */
127 tmp
= readl(&(host_mmio
->ghc
));
128 if ((tmp
& SATA_HOST_GHC_HR
) == 0)
129 writel_with_flush(tmp
| SATA_HOST_GHC_HR
, &(host_mmio
->ghc
));
131 while ((readl(&(host_mmio
->ghc
)) & SATA_HOST_GHC_HR
)
136 debug("controller reset failed (0x%x)\n", tmp
);
141 writel(clk
/ 1000, &(host_mmio
->timer1ms
));
143 ahci_setup_oobr(probe_ent
, 0);
145 writel_with_flush(SATA_HOST_GHC_AE
, &(host_mmio
->ghc
));
146 writel(cap_save
, &(host_mmio
->cap
));
147 num_ports
= (cap_save
& SATA_HOST_CAP_NP_MASK
) + 1;
148 writel_with_flush((1 << num_ports
) - 1,
152 * Determine which Ports are implemented by the DWC_ahsata,
153 * by reading the PI register. This bit map value aids the
154 * software to determine how many Ports are available and
155 * which Port registers need to be initialized.
157 probe_ent
->cap
= readl(&(host_mmio
->cap
));
158 probe_ent
->port_map
= readl(&(host_mmio
->pi
));
160 /* Determine how many command slots the HBA supports */
162 (probe_ent
->cap
& SATA_HOST_CAP_NP_MASK
) + 1;
164 debug("cap 0x%x port_map 0x%x n_ports %d\n",
165 probe_ent
->cap
, probe_ent
->port_map
, probe_ent
->n_ports
);
167 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
168 probe_ent
->port
[i
].port_mmio
=
169 ahci_port_base((u32
)host_mmio
, i
);
171 (struct sata_port_regs
*)probe_ent
->port
[i
].port_mmio
;
173 /* Ensure that the DWC_ahsata is in idle state */
174 tmp
= readl(&(port_mmio
->cmd
));
177 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
178 * are all cleared, the Port is in an idle state.
180 if (tmp
& (SATA_PORT_CMD_CR
| SATA_PORT_CMD_FR
|
181 SATA_PORT_CMD_FRE
| SATA_PORT_CMD_ST
)) {
184 * System software places a Port into the idle state by
185 * clearing P#CMD.ST and waiting for P#CMD.CR to return
188 tmp
&= ~SATA_PORT_CMD_ST
;
189 writel_with_flush(tmp
, &(port_mmio
->cmd
));
192 * spec says 500 msecs for each bit, so
193 * this is slightly incorrect.
198 while ((readl(&(port_mmio
->cmd
)) & SATA_PORT_CMD_CR
)
203 debug("port reset failed (0x%x)\n", tmp
);
209 tmp
= readl(&(port_mmio
->cmd
));
210 writel((tmp
| SATA_PORT_CMD_SUD
), &(port_mmio
->cmd
));
212 /* Wait for spin-up to finish */
214 while (!(readl(&(port_mmio
->cmd
)) | SATA_PORT_CMD_SUD
)
218 debug("Spin-Up can't finish!\n");
222 for (j
= 0; j
< 100; ++j
) {
224 tmp
= readl(&(port_mmio
->ssts
));
225 if (((tmp
& SATA_PORT_SSTS_DET_MASK
) == 0x3) ||
226 ((tmp
& SATA_PORT_SSTS_DET_MASK
) == 0x1))
230 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
232 while (!(readl(&(port_mmio
->serr
)) | SATA_PORT_SERR_DIAG_X
)
236 debug("Can't find DIAG_X set!\n");
241 * For each implemented Port, clear the P#SERR
242 * register, by writing ones to each implemented\
245 tmp
= readl(&(port_mmio
->serr
));
246 debug("P#SERR 0x%x\n",
248 writel(tmp
, &(port_mmio
->serr
));
250 /* Ack any pending irq events for this port */
251 tmp
= readl(&(host_mmio
->is
));
252 debug("IS 0x%x\n", tmp
);
254 writel(tmp
, &(host_mmio
->is
));
256 writel(1 << i
, &(host_mmio
->is
));
258 /* set irq mask (enables interrupts) */
259 writel(DEF_PORT_IRQ
, &(port_mmio
->ie
));
261 /* register linkup ports */
262 tmp
= readl(&(port_mmio
->ssts
));
263 debug("Port %d status: 0x%x\n", i
, tmp
);
264 if ((tmp
& SATA_PORT_SSTS_DET_MASK
) == 0x03)
265 probe_ent
->link_port_map
|= (0x01 << i
);
268 tmp
= readl(&(host_mmio
->ghc
));
269 debug("GHC 0x%x\n", tmp
);
270 writel(tmp
| SATA_HOST_GHC_IE
, &(host_mmio
->ghc
));
271 tmp
= readl(&(host_mmio
->ghc
));
272 debug("GHC 0x%x\n", tmp
);
277 static void ahci_print_info(struct ahci_probe_ent
*probe_ent
)
279 struct sata_host_regs
*host_mmio
=
280 (struct sata_host_regs
*)probe_ent
->mmio_base
;
281 u32 vers
, cap
, impl
, speed
;
285 vers
= readl(&(host_mmio
->vs
));
286 cap
= probe_ent
->cap
;
287 impl
= probe_ent
->port_map
;
289 speed
= (cap
& SATA_HOST_CAP_ISS_MASK
)
290 >> SATA_HOST_CAP_ISS_OFFSET
;
300 printf("AHCI %02x%02x.%02x%02x "
301 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
306 ((cap
>> 8) & 0x1f) + 1,
315 cap
& (1 << 31) ? "64bit " : "",
316 cap
& (1 << 30) ? "ncq " : "",
317 cap
& (1 << 28) ? "ilck " : "",
318 cap
& (1 << 27) ? "stag " : "",
319 cap
& (1 << 26) ? "pm " : "",
320 cap
& (1 << 25) ? "led " : "",
321 cap
& (1 << 24) ? "clo " : "",
322 cap
& (1 << 19) ? "nz " : "",
323 cap
& (1 << 18) ? "only " : "",
324 cap
& (1 << 17) ? "pmp " : "",
325 cap
& (1 << 15) ? "pio " : "",
326 cap
& (1 << 14) ? "slum " : "",
327 cap
& (1 << 13) ? "part " : "");
330 static int ahci_init_one(int pdev
)
333 struct ahci_probe_ent
*probe_ent
= NULL
;
335 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
336 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
337 probe_ent
->dev
= pdev
;
339 probe_ent
->host_flags
= ATA_FLAG_SATA
345 probe_ent
->mmio_base
= CONFIG_DWC_AHSATA_BASE_ADDR
;
347 /* initialize adapter */
348 rc
= ahci_host_init(probe_ent
);
352 ahci_print_info(probe_ent
);
354 /* Save the private struct to block device struct */
355 sata_dev_desc
[pdev
].priv
= (void *)probe_ent
;
363 static int ahci_fill_sg(struct ahci_probe_ent
*probe_ent
,
364 u8 port
, unsigned char *buf
, int buf_len
)
366 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
367 struct ahci_sg
*ahci_sg
= pp
->cmd_tbl_sg
;
368 u32 sg_count
, max_bytes
;
371 max_bytes
= MAX_DATA_BYTES_PER_SG
;
372 sg_count
= ((buf_len
- 1) / max_bytes
) + 1;
373 if (sg_count
> AHCI_MAX_SG
) {
374 printf("Error:Too much sg!\n");
378 for (i
= 0; i
< sg_count
; i
++) {
380 cpu_to_le32((u32
)buf
+ i
* max_bytes
);
381 ahci_sg
->addr_hi
= 0;
382 ahci_sg
->flags_size
= cpu_to_le32(0x3fffff &
387 buf_len
-= max_bytes
;
393 static void ahci_fill_cmd_slot(struct ahci_ioports
*pp
, u32 cmd_slot
, u32 opts
)
395 struct ahci_cmd_hdr
*cmd_hdr
= (struct ahci_cmd_hdr
*)(pp
->cmd_slot
+
396 AHCI_CMD_SLOT_SZ
* cmd_slot
);
398 memset(cmd_hdr
, 0, AHCI_CMD_SLOT_SZ
);
399 cmd_hdr
->opts
= cpu_to_le32(opts
);
401 cmd_hdr
->tbl_addr
= cpu_to_le32(pp
->cmd_tbl
& 0xffffffff);
402 cmd_hdr
->tbl_addr_hi
= 0;
405 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
407 static int ahci_exec_ata_cmd(struct ahci_probe_ent
*probe_ent
,
408 u8 port
, struct sata_fis_h2d
*cfis
,
409 u8
*buf
, u32 buf_len
, s32 is_write
)
411 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
412 struct sata_port_regs
*port_mmio
=
413 (struct sata_port_regs
*)pp
->port_mmio
;
415 int sg_count
= 0, cmd_slot
= 0;
417 cmd_slot
= AHCI_GET_CMD_SLOT(readl(&(port_mmio
->ci
)));
418 if (32 == cmd_slot
) {
419 printf("Can't find empty command slot!\n");
423 /* Check xfer length */
424 if (buf_len
> MAX_BYTES_PER_TRANS
) {
425 printf("Max transfer length is %dB\n\r",
426 MAX_BYTES_PER_TRANS
);
430 memcpy((u8
*)(pp
->cmd_tbl
), cfis
, sizeof(struct sata_fis_h2d
));
432 sg_count
= ahci_fill_sg(probe_ent
, port
, buf
, buf_len
);
433 opts
= (sizeof(struct sata_fis_h2d
) >> 2) | (sg_count
<< 16);
436 flush_cache((ulong
)buf
, buf_len
);
438 ahci_fill_cmd_slot(pp
, cmd_slot
, opts
);
440 flush_cache((int)(pp
->cmd_slot
), AHCI_PORT_PRIV_DMA_SZ
);
441 writel_with_flush(1 << cmd_slot
, &(port_mmio
->ci
));
443 if (waiting_for_cmd_completed((u8
*)&(port_mmio
->ci
),
444 10000, 0x1 << cmd_slot
)) {
445 printf("timeout exit!\n");
448 invalidate_dcache_range((int)(pp
->cmd_slot
),
449 (int)(pp
->cmd_slot
)+AHCI_PORT_PRIV_DMA_SZ
);
450 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
451 pp
->cmd_slot
->status
);
453 invalidate_dcache_range((ulong
)buf
, (ulong
)buf
+buf_len
);
458 static void ahci_set_feature(u8 dev
, u8 port
)
460 struct ahci_probe_ent
*probe_ent
=
461 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
462 struct sata_fis_h2d h2d
__aligned(ARCH_DMA_MINALIGN
);
463 struct sata_fis_h2d
*cfis
= &h2d
;
465 memset(cfis
, 0, sizeof(struct sata_fis_h2d
));
466 cfis
->fis_type
= SATA_FIS_TYPE_REGISTER_H2D
;
467 cfis
->pm_port_c
= 1 << 7;
468 cfis
->command
= ATA_CMD_SET_FEATURES
;
469 cfis
->features
= SETFEATURES_XFER
;
470 cfis
->sector_count
= ffs(probe_ent
->udma_mask
+ 1) + 0x3e;
472 ahci_exec_ata_cmd(probe_ent
, port
, cfis
, NULL
, 0, READ_CMD
);
475 static int ahci_port_start(struct ahci_probe_ent
*probe_ent
,
478 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
479 struct sata_port_regs
*port_mmio
=
480 (struct sata_port_regs
*)pp
->port_mmio
;
483 int timeout
= 10000000;
485 debug("Enter start port: %d\n", port
);
486 port_status
= readl(&(port_mmio
->ssts
));
487 debug("Port %d status: %x\n", port
, port_status
);
488 if ((port_status
& 0xf) != 0x03) {
489 printf("No Link on this port!\n");
493 mem
= (u32
)malloc(AHCI_PORT_PRIV_DMA_SZ
+ 1024);
496 printf("No mem for table!\n");
500 mem
= (mem
+ 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
501 memset((u8
*)mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
504 * First item in chunk of DMA memory: 32-slot command table,
505 * 32 bytes each in size
507 pp
->cmd_slot
= (struct ahci_cmd_hdr
*)mem
;
508 debug("cmd_slot = 0x%x\n", (unsigned int) pp
->cmd_slot
);
509 mem
+= (AHCI_CMD_SLOT_SZ
* DWC_AHSATA_MAX_CMD_SLOTS
);
512 * Second item: Received-FIS area, 256-Byte aligned
515 mem
+= AHCI_RX_FIS_SZ
;
518 * Third item: data area for storing a single command
519 * and its scatter-gather table
522 debug("cmd_tbl_dma = 0x%x\n", pp
->cmd_tbl
);
524 mem
+= AHCI_CMD_TBL_HDR
;
526 writel_with_flush(0x00004444, &(port_mmio
->dmacr
));
527 pp
->cmd_tbl_sg
= (struct ahci_sg
*)mem
;
528 writel_with_flush((u32
)pp
->cmd_slot
, &(port_mmio
->clb
));
529 writel_with_flush(pp
->rx_fis
, &(port_mmio
->fb
));
532 writel_with_flush((SATA_PORT_CMD_FRE
| readl(&(port_mmio
->cmd
))),
535 /* Wait device ready */
536 while ((readl(&(port_mmio
->tfd
)) & (SATA_PORT_TFD_STS_ERR
|
537 SATA_PORT_TFD_STS_DRQ
| SATA_PORT_TFD_STS_BSY
))
541 debug("Device not ready for BSY, DRQ and"
546 writel_with_flush(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
547 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
548 PORT_CMD_START
, &(port_mmio
->cmd
));
550 debug("Exit start port %d\n", port
);
555 int init_sata(int dev
)
559 struct ahci_probe_ent
*probe_ent
= NULL
;
561 if (dev
< 0 || dev
> (CONFIG_SYS_SATA_MAX_DEVICE
- 1)) {
562 printf("The sata index %d is out of ranges\n\r", dev
);
568 probe_ent
= (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
569 linkmap
= probe_ent
->link_port_map
;
572 printf("No port device detected!\n");
576 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
577 if ((linkmap
>> i
) && ((linkmap
>> i
) & 0x01)) {
578 if (ahci_port_start(probe_ent
, (u8
)i
)) {
579 printf("Can not start port %d\n", i
);
582 probe_ent
->hard_port_no
= i
;
590 static void dwc_ahsata_print_info(int dev
)
592 block_dev_desc_t
*pdev
= &(sata_dev_desc
[dev
]);
594 printf("SATA Device Info:\n\r");
595 #ifdef CONFIG_SYS_64BIT_LBA
596 printf("S/N: %s\n\rProduct model number: %s\n\r"
597 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
598 pdev
->product
, pdev
->vendor
, pdev
->revision
, pdev
->lba
);
600 printf("S/N: %s\n\rProduct model number: %s\n\r"
601 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
602 pdev
->product
, pdev
->vendor
, pdev
->revision
, pdev
->lba
);
606 static void dwc_ahsata_identify(int dev
, u16
*id
)
608 struct ahci_probe_ent
*probe_ent
=
609 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
610 struct sata_fis_h2d h2d
__aligned(ARCH_DMA_MINALIGN
);
611 struct sata_fis_h2d
*cfis
= &h2d
;
612 u8 port
= probe_ent
->hard_port_no
;
614 memset(cfis
, 0, sizeof(struct sata_fis_h2d
));
616 cfis
->fis_type
= SATA_FIS_TYPE_REGISTER_H2D
;
617 cfis
->pm_port_c
= 0x80; /* is command */
618 cfis
->command
= ATA_CMD_ID_ATA
;
620 ahci_exec_ata_cmd(probe_ent
, port
, cfis
,
621 (u8
*)id
, ATA_ID_WORDS
* 2, READ_CMD
);
622 ata_swap_buf_le16(id
, ATA_ID_WORDS
);
625 static void dwc_ahsata_xfer_mode(int dev
, u16
*id
)
627 struct ahci_probe_ent
*probe_ent
=
628 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
630 probe_ent
->pio_mask
= id
[ATA_ID_PIO_MODES
];
631 probe_ent
->udma_mask
= id
[ATA_ID_UDMA_MODES
];
632 debug("pio %04x, udma %04x\n\r",
633 probe_ent
->pio_mask
, probe_ent
->udma_mask
);
636 static u32
dwc_ahsata_rw_cmd(int dev
, u32 start
, u32 blkcnt
,
637 u8
*buffer
, int is_write
)
639 struct ahci_probe_ent
*probe_ent
=
640 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
641 struct sata_fis_h2d h2d
__aligned(ARCH_DMA_MINALIGN
);
642 struct sata_fis_h2d
*cfis
= &h2d
;
643 u8 port
= probe_ent
->hard_port_no
;
648 memset(cfis
, 0, sizeof(struct sata_fis_h2d
));
650 cfis
->fis_type
= SATA_FIS_TYPE_REGISTER_H2D
;
651 cfis
->pm_port_c
= 0x80; /* is command */
652 cfis
->command
= (is_write
) ? ATA_CMD_WRITE
: ATA_CMD_READ
;
653 cfis
->device
= ATA_LBA
;
655 cfis
->device
|= (block
>> 24) & 0xf;
656 cfis
->lba_high
= (block
>> 16) & 0xff;
657 cfis
->lba_mid
= (block
>> 8) & 0xff;
658 cfis
->lba_low
= block
& 0xff;
659 cfis
->sector_count
= (u8
)(blkcnt
& 0xff);
661 if (ahci_exec_ata_cmd(probe_ent
, port
, cfis
,
662 buffer
, ATA_SECT_SIZE
* blkcnt
, is_write
) > 0)
668 void dwc_ahsata_flush_cache(int dev
)
670 struct ahci_probe_ent
*probe_ent
=
671 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
672 struct sata_fis_h2d h2d
__aligned(ARCH_DMA_MINALIGN
);
673 struct sata_fis_h2d
*cfis
= &h2d
;
674 u8 port
= probe_ent
->hard_port_no
;
676 memset(cfis
, 0, sizeof(struct sata_fis_h2d
));
678 cfis
->fis_type
= SATA_FIS_TYPE_REGISTER_H2D
;
679 cfis
->pm_port_c
= 0x80; /* is command */
680 cfis
->command
= ATA_CMD_FLUSH
;
682 ahci_exec_ata_cmd(probe_ent
, port
, cfis
, NULL
, 0, 0);
685 static u32
dwc_ahsata_rw_cmd_ext(int dev
, u32 start
, lbaint_t blkcnt
,
686 u8
*buffer
, int is_write
)
688 struct ahci_probe_ent
*probe_ent
=
689 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
690 struct sata_fis_h2d h2d
__aligned(ARCH_DMA_MINALIGN
);
691 struct sata_fis_h2d
*cfis
= &h2d
;
692 u8 port
= probe_ent
->hard_port_no
;
697 memset(cfis
, 0, sizeof(struct sata_fis_h2d
));
699 cfis
->fis_type
= SATA_FIS_TYPE_REGISTER_H2D
;
700 cfis
->pm_port_c
= 0x80; /* is command */
702 cfis
->command
= (is_write
) ? ATA_CMD_WRITE_EXT
705 cfis
->lba_high_exp
= (block
>> 40) & 0xff;
706 cfis
->lba_mid_exp
= (block
>> 32) & 0xff;
707 cfis
->lba_low_exp
= (block
>> 24) & 0xff;
708 cfis
->lba_high
= (block
>> 16) & 0xff;
709 cfis
->lba_mid
= (block
>> 8) & 0xff;
710 cfis
->lba_low
= block
& 0xff;
711 cfis
->device
= ATA_LBA
;
712 cfis
->sector_count_exp
= (blkcnt
>> 8) & 0xff;
713 cfis
->sector_count
= blkcnt
& 0xff;
715 if (ahci_exec_ata_cmd(probe_ent
, port
, cfis
, buffer
,
716 ATA_SECT_SIZE
* blkcnt
, is_write
) > 0)
722 u32
dwc_ahsata_rw_ncq_cmd(int dev
, u32 start
, lbaint_t blkcnt
,
723 u8
*buffer
, int is_write
)
725 struct ahci_probe_ent
*probe_ent
=
726 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
727 struct sata_fis_h2d h2d
__aligned(ARCH_DMA_MINALIGN
);
728 struct sata_fis_h2d
*cfis
= &h2d
;
729 u8 port
= probe_ent
->hard_port_no
;
732 if (sata_dev_desc
[dev
].lba48
!= 1) {
733 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
739 memset(cfis
, 0, sizeof(struct sata_fis_h2d
));
741 cfis
->fis_type
= SATA_FIS_TYPE_REGISTER_H2D
;
742 cfis
->pm_port_c
= 0x80; /* is command */
744 cfis
->command
= (is_write
) ? ATA_CMD_FPDMA_WRITE
745 : ATA_CMD_FPDMA_READ
;
747 cfis
->lba_high_exp
= (block
>> 40) & 0xff;
748 cfis
->lba_mid_exp
= (block
>> 32) & 0xff;
749 cfis
->lba_low_exp
= (block
>> 24) & 0xff;
750 cfis
->lba_high
= (block
>> 16) & 0xff;
751 cfis
->lba_mid
= (block
>> 8) & 0xff;
752 cfis
->lba_low
= block
& 0xff;
754 cfis
->device
= ATA_LBA
;
755 cfis
->features_exp
= (blkcnt
>> 8) & 0xff;
756 cfis
->features
= blkcnt
& 0xff;
758 /* Use the latest queue */
759 ahci_exec_ata_cmd(probe_ent
, port
, cfis
,
760 buffer
, ATA_SECT_SIZE
* blkcnt
, is_write
);
765 void dwc_ahsata_flush_cache_ext(int dev
)
767 struct ahci_probe_ent
*probe_ent
=
768 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
769 struct sata_fis_h2d h2d
__aligned(ARCH_DMA_MINALIGN
);
770 struct sata_fis_h2d
*cfis
= &h2d
;
771 u8 port
= probe_ent
->hard_port_no
;
773 memset(cfis
, 0, sizeof(struct sata_fis_h2d
));
775 cfis
->fis_type
= SATA_FIS_TYPE_REGISTER_H2D
;
776 cfis
->pm_port_c
= 0x80; /* is command */
777 cfis
->command
= ATA_CMD_FLUSH_EXT
;
779 ahci_exec_ata_cmd(probe_ent
, port
, cfis
, NULL
, 0, 0);
782 static void dwc_ahsata_init_wcache(int dev
, u16
*id
)
784 struct ahci_probe_ent
*probe_ent
=
785 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
787 if (ata_id_has_wcache(id
) && ata_id_wcache_enabled(id
))
788 probe_ent
->flags
|= SATA_FLAG_WCACHE
;
789 if (ata_id_has_flush(id
))
790 probe_ent
->flags
|= SATA_FLAG_FLUSH
;
791 if (ata_id_has_flush_ext(id
))
792 probe_ent
->flags
|= SATA_FLAG_FLUSH_EXT
;
795 u32
ata_low_level_rw_lba48(int dev
, u32 blknr
, lbaint_t blkcnt
,
796 const void *buffer
, int is_write
)
806 max_blks
= ATA_MAX_SECTORS_LBA48
;
809 if (blks
> max_blks
) {
810 if (max_blks
!= dwc_ahsata_rw_cmd_ext(dev
, start
,
811 max_blks
, addr
, is_write
))
815 addr
+= ATA_SECT_SIZE
* max_blks
;
817 if (blks
!= dwc_ahsata_rw_cmd_ext(dev
, start
,
818 blks
, addr
, is_write
))
822 addr
+= ATA_SECT_SIZE
* blks
;
829 u32
ata_low_level_rw_lba28(int dev
, u32 blknr
, lbaint_t blkcnt
,
830 const void *buffer
, int is_write
)
840 max_blks
= ATA_MAX_SECTORS
;
842 if (blks
> max_blks
) {
843 if (max_blks
!= dwc_ahsata_rw_cmd(dev
, start
,
844 max_blks
, addr
, is_write
))
848 addr
+= ATA_SECT_SIZE
* max_blks
;
850 if (blks
!= dwc_ahsata_rw_cmd(dev
, start
,
851 blks
, addr
, is_write
))
855 addr
+= ATA_SECT_SIZE
* blks
;
863 * SATA interface between low level driver and command layer
865 ulong
sata_read(int dev
, ulong blknr
, lbaint_t blkcnt
, void *buffer
)
869 if (sata_dev_desc
[dev
].lba48
)
870 rc
= ata_low_level_rw_lba48(dev
, blknr
, blkcnt
,
873 rc
= ata_low_level_rw_lba28(dev
, blknr
, blkcnt
,
878 ulong
sata_write(int dev
, ulong blknr
, lbaint_t blkcnt
, const void *buffer
)
881 struct ahci_probe_ent
*probe_ent
=
882 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
883 u32 flags
= probe_ent
->flags
;
885 if (sata_dev_desc
[dev
].lba48
) {
886 rc
= ata_low_level_rw_lba48(dev
, blknr
, blkcnt
,
888 if ((flags
& SATA_FLAG_WCACHE
) &&
889 (flags
& SATA_FLAG_FLUSH_EXT
))
890 dwc_ahsata_flush_cache_ext(dev
);
892 rc
= ata_low_level_rw_lba28(dev
, blknr
, blkcnt
,
894 if ((flags
& SATA_FLAG_WCACHE
) &&
895 (flags
& SATA_FLAG_FLUSH
))
896 dwc_ahsata_flush_cache(dev
);
901 int scan_sata(int dev
)
903 u8 serial
[ATA_ID_SERNO_LEN
+ 1] = { 0 };
904 u8 firmware
[ATA_ID_FW_REV_LEN
+ 1] = { 0 };
905 u8 product
[ATA_ID_PROD_LEN
+ 1] = { 0 };
908 struct ahci_probe_ent
*probe_ent
=
909 (struct ahci_probe_ent
*)sata_dev_desc
[dev
].priv
;
910 u8 port
= probe_ent
->hard_port_no
;
911 block_dev_desc_t
*pdev
= &(sata_dev_desc
[dev
]);
913 id
= (u16
*)memalign(ARCH_DMA_MINALIGN
,
914 roundup(ARCH_DMA_MINALIGN
,
915 (ATA_ID_WORDS
* 2)));
917 printf("id malloc failed\n\r");
921 /* Identify device to get information */
922 dwc_ahsata_identify(dev
, id
);
925 ata_id_c_string(id
, serial
, ATA_ID_SERNO
, sizeof(serial
));
926 memcpy(pdev
->product
, serial
, sizeof(serial
));
928 /* Firmware version */
929 ata_id_c_string(id
, firmware
, ATA_ID_FW_REV
, sizeof(firmware
));
930 memcpy(pdev
->revision
, firmware
, sizeof(firmware
));
933 ata_id_c_string(id
, product
, ATA_ID_PROD
, sizeof(product
));
934 memcpy(pdev
->vendor
, product
, sizeof(product
));
937 n_sectors
= ata_id_n_sectors(id
);
938 pdev
->lba
= (u32
)n_sectors
;
940 pdev
->type
= DEV_TYPE_HARDDISK
;
941 pdev
->blksz
= ATA_SECT_SIZE
;
944 /* Check if support LBA48 */
945 if (ata_id_has_lba48(id
)) {
947 debug("Device support LBA48\n\r");
950 /* Get the NCQ queue depth from device */
951 probe_ent
->flags
&= (~SATA_FLAG_Q_DEP_MASK
);
952 probe_ent
->flags
|= ata_id_queue_depth(id
);
954 /* Get the xfer mode from device */
955 dwc_ahsata_xfer_mode(dev
, id
);
957 /* Get the write cache status from device */
958 dwc_ahsata_init_wcache(dev
, id
);
960 /* Set the xfer mode to highest speed */
961 ahci_set_feature(dev
, port
);
965 dwc_ahsata_print_info(dev
);