drivers/block/fsl_sata.h

   1 /*
   2  * Copyright (C) 2007-2008 Freescale Semiconductor, Inc.
   3  *              Dave Liu <daveliu@freescale.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #ifndef __FSL_SATA_H__
  22 #define __FSL_SATA_H__
  23
  24 #define SATA_HC_MAX_NUM         4 /* Max host controller numbers */
  25 #define SATA_HC_MAX_CMD         16 /* Max command queue depth per host controller */
  26 #define SATA_HC_MAX_PORT        16 /* Max port number per host controller */
  27
  28 /*
  29 * SATA Host Controller Registers
  30 */
  31 typedef struct fsl_sata_reg {
  32         /* SATA command registers */
  33         u32 cqr;                /* Command queue register */
  34         u8 res1[0x4];
  35         u32 car;                /* Command active register */
  36         u8 res2[0x4];
  37         u32 ccr;                /* Command completed register */
  38         u8 res3[0x4];
  39         u32 cer;                /* Command error register */
  40         u8 res4[0x4];
  41         u32 der;                /* Device error register */
  42         u32 chba;               /* Command header base address */
  43         u32 hstatus;            /* Host status register */
  44         u32 hcontrol;           /* Host control register */
  45         u32 cqpmp;              /* Port number queue register */
  46         u32 sig;                /* Signature register */
  47         u32 icc;                /* Interrupt coalescing control register */
  48         u8 res5[0xc4];
  49
  50         /* SATA supperset registers */
  51         u32 sstatus;            /* SATA interface status register */
  52         u32 serror;             /* SATA interface error register */
  53         u32 scontrol;           /* SATA interface control register */
  54         u32 snotification;      /* SATA interface notification register */
  55         u8 res6[0x30];
  56
  57         /* SATA control status registers */
  58         u32 transcfg;           /* Transport layer configuration */
  59         u32 transstatus;        /* Transport layer status */
  60         u32 linkcfg;            /* Link layer configuration */
  61         u32 linkcfg1;           /* Link layer configuration1 */
  62         u32 linkcfg2;           /* Link layer configuration2 */
  63         u32 linkstatus;         /* Link layer status */
  64         u32 linkstatus1;        /* Link layer status1 */
  65         u32 phyctrlcfg;         /* PHY control configuration */
  66         u8 res7[0x2b0];
  67
  68         /* SATA system control registers */
  69         u32 syspr;              /* System priority register - big endian */
  70         u8 res8[0xbec];
  71 } __attribute__ ((packed)) fsl_sata_reg_t;
  72
  73 /* HStatus register
  74 */
  75 #define HSTATUS_ONOFF                   0x80000000 /* Online/offline status */
  76 #define HSTATUS_FORCE_OFFLINE           0x40000000 /* In process going offline */
  77 #define HSTATUS_BIST_ERR                0x20000000
  78
  79 /* Fatal error */
  80 #define HSTATUS_MASTER_ERR              0x00004000
  81 #define HSTATUS_DATA_UNDERRUN           0x00002000
  82 #define HSTATUS_DATA_OVERRUN            0x00001000
  83 #define HSTATUS_CRC_ERR_TX              0x00000800
  84 #define HSTATUS_CRC_ERR_RX              0x00000400
  85 #define HSTATUS_FIFO_OVERFLOW_TX        0x00000200
  86 #define HSTATUS_FIFO_OVERFLOW_RX        0x00000100
  87 #define HSTATUS_FATAL_ERR_ALL           (HSTATUS_MASTER_ERR | \
  88                                         HSTATUS_DATA_UNDERRUN | \
  89                                         HSTATUS_DATA_OVERRUN | \
  90                                         HSTATUS_CRC_ERR_TX | \
  91                                         HSTATUS_CRC_ERR_RX | \
  92                                         HSTATUS_FIFO_OVERFLOW_TX | \
  93                                         HSTATUS_FIFO_OVERFLOW_RX)
  94 /* Interrupt status */
  95 #define HSTATUS_FATAL_ERR               0x00000020
  96 #define HSTATUS_PHY_RDY                 0x00000010
  97 #define HSTATUS_SIGNATURE               0x00000008
  98 #define HSTATUS_SNOTIFY                 0x00000004
  99 #define HSTATUS_DEVICE_ERR              0x00000002
 100 #define HSTATUS_CMD_COMPLETE            0x00000001
 101
 102 /* HControl register
 103 */
 104 #define HCONTROL_ONOFF                  0x80000000 /* Online or offline request */
 105 #define HCONTROL_FORCE_OFFLINE          0x40000000 /* Force offline request */
 106 #define HCONTROL_HDR_SNOOP              0x00000400 /* Command header snoop */
 107 #define HCONTROL_PMP_ATTACHED           0x00000200 /* Port multiplier attached */
 108
 109 /* Interrupt enable */
 110 #define HCONTROL_FATAL_ERR              0x00000020
 111 #define HCONTROL_PHY_RDY                0x00000010
 112 #define HCONTROL_SIGNATURE              0x00000008
 113 #define HCONTROL_SNOTIFY                0x00000004
 114 #define HCONTROL_DEVICE_ERR             0x00000002
 115 #define HCONTROL_CMD_COMPLETE           0x00000001
 116
 117 #define HCONTROL_INT_EN_ALL             (HCONTROL_FATAL_ERR | \
 118                                         HCONTROL_PHY_RDY | \
 119                                         HCONTROL_SIGNATURE | \
 120                                         HCONTROL_SNOTIFY | \
 121                                         HCONTROL_DEVICE_ERR | \
 122                                         HCONTROL_CMD_COMPLETE)
 123
 124 /* SStatus register
 125 */
 126 #define SSTATUS_IPM_MASK                0x00000780
 127 #define SSTATUS_IPM_NOPRESENT           0x00000000
 128 #define SSTATUS_IPM_ACTIVE              0x00000080
 129 #define SSTATUS_IPM_PATIAL              0x00000100
 130 #define SSTATUS_IPM_SLUMBER             0x00000300
 131
 132 #define SSTATUS_SPD_MASK                0x000000f0
 133 #define SSTATUS_SPD_GEN1                0x00000010
 134 #define SSTATUS_SPD_GEN2                0x00000020
 135
 136 #define SSTATUS_DET_MASK                0x0000000f
 137 #define SSTATUS_DET_NODEVICE            0x00000000
 138 #define SSTATUS_DET_DISCONNECT          0x00000001
 139 #define SSTATUS_DET_CONNECT             0x00000003
 140 #define SSTATUS_DET_PHY_OFFLINE         0x00000004
 141
 142 /* SControl register
 143 */
 144 #define SCONTROL_SPM_MASK               0x0000f000
 145 #define SCONTROL_SPM_GO_PARTIAL         0x00001000
 146 #define SCONTROL_SPM_GO_SLUMBER         0x00002000
 147 #define SCONTROL_SPM_GO_ACTIVE          0x00004000
 148
 149 #define SCONTROL_IPM_MASK               0x00000f00
 150 #define SCONTROL_IPM_NO_RESTRICT        0x00000000
 151 #define SCONTROL_IPM_PARTIAL            0x00000100
 152 #define SCONTROL_IPM_SLUMBER            0x00000200
 153 #define SCONTROL_IPM_PART_SLUM          0x00000300
 154
 155 #define SCONTROL_SPD_MASK               0x000000f0
 156 #define SCONTROL_SPD_NO_RESTRICT        0x00000000
 157 #define SCONTROL_SPD_GEN1               0x00000010
 158 #define SCONTROL_SPD_GEN2               0x00000020
 159
 160 #define SCONTROL_DET_MASK               0x0000000f
 161 #define SCONTROL_DET_HRESET             0x00000001
 162 #define SCONTROL_DET_DISABLE            0x00000004
 163
 164 /* TransCfg register
 165 */
 166 #define TRANSCFG_DFIS_SIZE_SHIFT        16
 167 #define TRANSCFG_RX_WATER_MARK_MASK     0x0000001f
 168
 169 /* PhyCtrlCfg register
 170 */
 171 #define PHYCTRLCFG_FPRFTI_MASK          0x00000018
 172 #define PHYCTRLCFG_LOOPBACK_MASK        0x0000000e
 173
 174 /*
 175 * Command Header Entry
 176 */
 177 typedef struct cmd_hdr_entry {
 178         u32 cda;                /* Command Descriptor Address, 4 bytes aligned */
 179         u32 prde_fis_len;       /* Number of PRD entries and FIS length */
 180         u32 ttl;                /* Total transfer length */
 181         u32 attribute;          /* the attribute of command */
 182 } __attribute__ ((packed)) cmd_hdr_entry_t;
 183
 184 #define SATA_HC_CMD_HDR_ENTRY_SIZE      sizeof(struct cmd_hdr_entry)
 185
 186 /* cda
 187 */
 188 #define CMD_HDR_CDA_ALIGN       4
 189
 190 /* prde_fis_len
 191 */
 192 #define CMD_HDR_PRD_ENTRY_SHIFT 16
 193 #define CMD_HDR_PRD_ENTRY_MASK  0x003f0000
 194 #define CMD_HDR_FIS_LEN_SHIFT   2
 195
 196 /* attribute
 197 */
 198 #define CMD_HDR_ATTR_RES        0x00000800 /* Reserved bit, should be 1 */
 199 #define CMD_HDR_ATTR_VBIST      0x00000400 /* Vendor BIST */
 200 #define CMD_HDR_ATTR_SNOOP      0x00000200 /* Snoop enable for all descriptor */
 201 #define CMD_HDR_ATTR_FPDMA      0x00000100 /* FPDMA queued command */
 202 #define CMD_HDR_ATTR_RESET      0x00000080 /* Reset - a SRST or device reset */
 203 #define CMD_HDR_ATTR_BIST       0x00000040 /* BIST - require the host to enter BIST mode */
 204 #define CMD_HDR_ATTR_ATAPI      0x00000020 /* ATAPI command */
 205 #define CMD_HDR_ATTR_TAG        0x0000001f /* TAG mask */
 206
 207 /* command type
 208 */
 209 enum cmd_type {
 210         CMD_VENDOR_BIST,
 211         CMD_BIST,
 212         CMD_RESET,      /* SRST or device reset */
 213         CMD_ATAPI,
 214         CMD_NCQ,
 215         CMD_ATA,        /* None of all above */
 216 };
 217
 218 /*
 219 * Command Header Table
 220 */
 221 typedef struct cmd_hdr_tbl {
 222         cmd_hdr_entry_t cmd_slot[SATA_HC_MAX_CMD];
 223 } __attribute__ ((packed)) cmd_hdr_tbl_t;
 224
 225 #define SATA_HC_CMD_HDR_TBL_SIZE        sizeof(struct cmd_hdr_tbl)
 226 #define SATA_HC_CMD_HDR_TBL_ALIGN       4
 227
 228 /*
 229 * PRD entry - Physical Region Descriptor entry
 230 */
 231 typedef struct prd_entry {
 232         u32 dba;        /* Data base address, 4 bytes aligned */
 233         u32 res1;
 234         u32 res2;
 235         u32 ext_c_ddc;  /* Indirect PRD flags, snoop and data word count */
 236 } __attribute__ ((packed)) prd_entry_t;
 237
 238 #define SATA_HC_CMD_DESC_PRD_SIZE       sizeof(struct prd_entry)
 239
 240 /* dba
 241 */
 242 #define PRD_ENTRY_DBA_ALIGN     4
 243
 244 /* ext_c_ddc
 245 */
 246 #define PRD_ENTRY_EXT           0x80000000 /* extension flag or called indirect descriptor flag */
 247 #define PRD_ENTRY_DATA_SNOOP    0x00400000 /* Snoop enable for all data associated with the PRD entry */
 248 #define PRD_ENTRY_LEN_MASK      0x003fffff /* Data word count */
 249
 250 #define PRD_ENTRY_MAX_XFER_SZ   (PRD_ENTRY_LEN_MASK + 1)
 251
 252 /*
 253  * This SATA host controller supports a max of 16 direct PRD entries, but if use
 254  * chained indirect PRD entries, then the contollers supports upto a max of 63
 255  * entries including direct and indirect PRD entries.
 256  * The PRDT is an array of 63 PRD entries contigiously, but the PRD entries#15
 257  * will be setup as an indirect descriptor, pointing to it's next (contigious)
 258  * PRD entries#16.
 259  */
 260 #define SATA_HC_MAX_PRD         63 /* Max PRD entry numbers per command */
 261 #define SATA_HC_MAX_PRD_DIRECT  16 /* Direct PRDT entries */
 262 #define SATA_HC_MAX_PRD_USABLE  (SATA_HC_MAX_PRD - 1)
 263 #define SATA_HC_MAX_XFER_LEN    0x4000000
 264
 265 /*
 266 * PRDT - Physical Region Descriptor Table
 267 */
 268 typedef struct prdt {
 269         prd_entry_t prdt[SATA_HC_MAX_PRD];
 270 } __attribute__ ((packed)) prdt_t;
 271
 272 /*
 273 * Command Descriptor
 274 */
 275 #define SATA_HC_CMD_DESC_CFIS_SIZE      32 /* bytes */
 276 #define SATA_HC_CMD_DESC_SFIS_SIZE      32 /* bytes */
 277 #define SATA_HC_CMD_DESC_ACMD_SIZE      16 /* bytes */
 278 #define SATA_HC_CMD_DESC_RES            16 /* bytes */
 279
 280 typedef struct cmd_desc {
 281         u8 cfis[SATA_HC_CMD_DESC_CFIS_SIZE];
 282         u8 sfis[SATA_HC_CMD_DESC_SFIS_SIZE];
 283         u8 acmd[SATA_HC_CMD_DESC_ACMD_SIZE];
 284         u8 res[SATA_HC_CMD_DESC_RES];
 285         prd_entry_t prdt[SATA_HC_MAX_PRD];
 286 } __attribute__ ((packed)) cmd_desc_t;
 287
 288 #define SATA_HC_CMD_DESC_SIZE           sizeof(struct cmd_desc)
 289 #define SATA_HC_CMD_DESC_ALIGN          4
 290
 291 /*
 292 * CFIS - Command FIS, which is H2D register FIS, the struct defination
 293 * of Non-Queued command is different than NCQ command. see them is sata2.h
 294 */
 295 typedef struct cfis {
 296         u8 fis_type;
 297         u8 pm_port_c;
 298         u8 command;
 299         u8 features;
 300         u8 lba_low;
 301         u8 lba_mid;
 302         u8 lba_high;
 303         u8 device;
 304         u8 lba_low_exp;
 305         u8 lba_mid_exp;
 306         u8 lba_high_exp;
 307         u8 features_exp;
 308         u8 sector_count;
 309         u8 sector_count_exp;
 310         u8 res1;
 311         u8 control;
 312         u8 res2[4];
 313 } __attribute__ ((packed)) cfis_t;
 314
 315 /*
 316 * SFIS - Status FIS, which is D2H register FIS.
 317 */
 318 typedef struct sfis {
 319         u8 fis_type;
 320         u8 pm_port_i;
 321         u8 status;
 322         u8 error;
 323         u8 lba_low;
 324         u8 lba_mid;
 325         u8 lba_high;
 326         u8 device;
 327         u8 lba_low_exp;
 328         u8 lba_mid_exp;
 329         u8 lba_high_exp;
 330         u8 res1;
 331         u8 sector_count;
 332         u8 sector_count_exp;
 333         u8 res2[2];
 334         u8 res3[4];
 335 } __attribute__ ((packed)) sfis_t;
 336
 337 /*
 338  * SATA device driver info
 339  */
 340 typedef struct fsl_sata_info {
 341         u32     sata_reg_base;
 342         u32     flags;
 343 } fsl_sata_info_t;
 344
 345 #define FLAGS_DMA       0x00000000
 346 #define FLAGS_FPDMA     0x00000001
 347
 348 /*
 349  * SATA device driver struct
 350  */
 351 typedef struct fsl_sata {
 352         char            name[12];
 353         fsl_sata_reg_t  *reg_base;              /* the base address of controller register */
 354         void            *cmd_hdr_tbl_offset;    /* alloc address of command header table */
 355         cmd_hdr_tbl_t   *cmd_hdr;               /* aligned address of command header table */
 356         void            *cmd_desc_offset;       /* alloc address of command descriptor */
 357         cmd_desc_t      *cmd_desc;              /* aligned address of command descriptor */
 358         int             link;                   /* PHY link status */
 359         /* device attribute */
 360         int             ata_device_type;        /* device type */
 361         int             lba48;
 362         int             queue_depth;            /* Max NCQ queue depth */
 363         u16             pio;
 364         u16             mwdma;
 365         u16             udma;
 366         int             wcache;
 367         int             flush;
 368         int             flush_ext;
 369 } fsl_sata_t;
 370
 371 #define READ_CMD        0
 372 #define WRITE_CMD       1
 373
 374 #endif /* __FSL_SATA_H__ */