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ARM: ixp4xx: include irqs.h where needed
[thirdparty/kernel/linux.git] / drivers / block / swim3.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for the SWIM3 (Super Woz Integrated Machine 3)
4 * floppy controller found on Power Macintoshes.
5 *
6 * Copyright (C) 1996 Paul Mackerras.
7 */
8
9 /*
10 * TODO:
11 * handle 2 drives
12 * handle GCR disks
13 */
14
15 #undef DEBUG
16
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/sched/signal.h>
20 #include <linux/timer.h>
21 #include <linux/delay.h>
22 #include <linux/fd.h>
23 #include <linux/ioctl.h>
24 #include <linux/blk-mq.h>
25 #include <linux/interrupt.h>
26 #include <linux/mutex.h>
27 #include <linux/module.h>
28 #include <linux/spinlock.h>
29 #include <linux/wait.h>
30 #include <asm/io.h>
31 #include <asm/dbdma.h>
32 #include <asm/prom.h>
33 #include <linux/uaccess.h>
34 #include <asm/mediabay.h>
35 #include <asm/machdep.h>
36 #include <asm/pmac_feature.h>
37
38 #define MAX_FLOPPIES 2
39
40 static DEFINE_MUTEX(swim3_mutex);
41 static struct gendisk *disks[MAX_FLOPPIES];
42
43 enum swim_state {
44 idle,
45 locating,
46 seeking,
47 settling,
48 do_transfer,
49 jogging,
50 available,
51 revalidating,
52 ejecting
53 };
54
55 #define REG(x) unsigned char x; char x ## _pad[15];
56
57 /*
58 * The names for these registers mostly represent speculation on my part.
59 * It will be interesting to see how close they are to the names Apple uses.
60 */
61 struct swim3 {
62 REG(data);
63 REG(timer); /* counts down at 1MHz */
64 REG(error);
65 REG(mode);
66 REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
67 REG(setup);
68 REG(control); /* writing bits clears them */
69 REG(status); /* writing bits sets them in control */
70 REG(intr);
71 REG(nseek); /* # tracks to seek */
72 REG(ctrack); /* current track number */
73 REG(csect); /* current sector number */
74 REG(gap3); /* size of gap 3 in track format */
75 REG(sector); /* sector # to read or write */
76 REG(nsect); /* # sectors to read or write */
77 REG(intr_enable);
78 };
79
80 #define control_bic control
81 #define control_bis status
82
83 /* Bits in select register */
84 #define CA_MASK 7
85 #define LSTRB 8
86
87 /* Bits in control register */
88 #define DO_SEEK 0x80
89 #define FORMAT 0x40
90 #define SELECT 0x20
91 #define WRITE_SECTORS 0x10
92 #define DO_ACTION 0x08
93 #define DRIVE2_ENABLE 0x04
94 #define DRIVE_ENABLE 0x02
95 #define INTR_ENABLE 0x01
96
97 /* Bits in status register */
98 #define FIFO_1BYTE 0x80
99 #define FIFO_2BYTE 0x40
100 #define ERROR 0x20
101 #define DATA 0x08
102 #define RDDATA 0x04
103 #define INTR_PENDING 0x02
104 #define MARK_BYTE 0x01
105
106 /* Bits in intr and intr_enable registers */
107 #define ERROR_INTR 0x20
108 #define DATA_CHANGED 0x10
109 #define TRANSFER_DONE 0x08
110 #define SEEN_SECTOR 0x04
111 #define SEEK_DONE 0x02
112 #define TIMER_DONE 0x01
113
114 /* Bits in error register */
115 #define ERR_DATA_CRC 0x80
116 #define ERR_ADDR_CRC 0x40
117 #define ERR_OVERRUN 0x04
118 #define ERR_UNDERRUN 0x01
119
120 /* Bits in setup register */
121 #define S_SW_RESET 0x80
122 #define S_GCR_WRITE 0x40
123 #define S_IBM_DRIVE 0x20
124 #define S_TEST_MODE 0x10
125 #define S_FCLK_DIV2 0x08
126 #define S_GCR 0x04
127 #define S_COPY_PROT 0x02
128 #define S_INV_WDATA 0x01
129
130 /* Select values for swim3_action */
131 #define SEEK_POSITIVE 0
132 #define SEEK_NEGATIVE 4
133 #define STEP 1
134 #define MOTOR_ON 2
135 #define MOTOR_OFF 6
136 #define INDEX 3
137 #define EJECT 7
138 #define SETMFM 9
139 #define SETGCR 13
140
141 /* Select values for swim3_select and swim3_readbit */
142 #define STEP_DIR 0
143 #define STEPPING 1
144 #define MOTOR_ON 2
145 #define RELAX 3 /* also eject in progress */
146 #define READ_DATA_0 4
147 #define ONEMEG_DRIVE 5
148 #define SINGLE_SIDED 6 /* drive or diskette is 4MB type? */
149 #define DRIVE_PRESENT 7
150 #define DISK_IN 8
151 #define WRITE_PROT 9
152 #define TRACK_ZERO 10
153 #define TACHO 11
154 #define READ_DATA_1 12
155 #define GCR_MODE 13
156 #define SEEK_COMPLETE 14
157 #define TWOMEG_MEDIA 15
158
159 /* Definitions of values used in writing and formatting */
160 #define DATA_ESCAPE 0x99
161 #define GCR_SYNC_EXC 0x3f
162 #define GCR_SYNC_CONV 0x80
163 #define GCR_FIRST_MARK 0xd5
164 #define GCR_SECOND_MARK 0xaa
165 #define GCR_ADDR_MARK "\xd5\xaa\x00"
166 #define GCR_DATA_MARK "\xd5\xaa\x0b"
167 #define GCR_SLIP_BYTE "\x27\xaa"
168 #define GCR_SELF_SYNC "\x3f\xbf\x1e\x34\x3c\x3f"
169
170 #define DATA_99 "\x99\x99"
171 #define MFM_ADDR_MARK "\x99\xa1\x99\xa1\x99\xa1\x99\xfe"
172 #define MFM_INDEX_MARK "\x99\xc2\x99\xc2\x99\xc2\x99\xfc"
173 #define MFM_GAP_LEN 12
174
175 struct floppy_state {
176 enum swim_state state;
177 struct swim3 __iomem *swim3; /* hardware registers */
178 struct dbdma_regs __iomem *dma; /* DMA controller registers */
179 int swim3_intr; /* interrupt number for SWIM3 */
180 int dma_intr; /* interrupt number for DMA channel */
181 int cur_cyl; /* cylinder head is on, or -1 */
182 int cur_sector; /* last sector we saw go past */
183 int req_cyl; /* the cylinder for the current r/w request */
184 int head; /* head number ditto */
185 int req_sector; /* sector number ditto */
186 int scount; /* # sectors we're transferring at present */
187 int retries;
188 int settle_time;
189 int secpercyl; /* disk geometry information */
190 int secpertrack;
191 int total_secs;
192 int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */
193 struct dbdma_cmd *dma_cmd;
194 int ref_count;
195 int expect_cyl;
196 struct timer_list timeout;
197 int timeout_pending;
198 int ejected;
199 wait_queue_head_t wait;
200 int wanted;
201 struct macio_dev *mdev;
202 char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)];
203 int index;
204 struct request *cur_req;
205 struct blk_mq_tag_set tag_set;
206 };
207
208 #define swim3_err(fmt, arg...) dev_err(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
209 #define swim3_warn(fmt, arg...) dev_warn(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
210 #define swim3_info(fmt, arg...) dev_info(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
211
212 #ifdef DEBUG
213 #define swim3_dbg(fmt, arg...) dev_dbg(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
214 #else
215 #define swim3_dbg(fmt, arg...) do { } while(0)
216 #endif
217
218 static struct floppy_state floppy_states[MAX_FLOPPIES];
219 static int floppy_count = 0;
220 static DEFINE_SPINLOCK(swim3_lock);
221
222 static unsigned short write_preamble[] = {
223 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, /* gap field */
224 0, 0, 0, 0, 0, 0, /* sync field */
225 0x99a1, 0x99a1, 0x99a1, 0x99fb, /* data address mark */
226 0x990f /* no escape for 512 bytes */
227 };
228
229 static unsigned short write_postamble[] = {
230 0x9904, /* insert CRC */
231 0x4e4e, 0x4e4e,
232 0x9908, /* stop writing */
233 0, 0, 0, 0, 0, 0
234 };
235
236 static void seek_track(struct floppy_state *fs, int n);
237 static void init_dma(struct dbdma_cmd *cp, int cmd, void *buf, int count);
238 static void act(struct floppy_state *fs);
239 static void scan_timeout(struct timer_list *t);
240 static void seek_timeout(struct timer_list *t);
241 static void settle_timeout(struct timer_list *t);
242 static void xfer_timeout(struct timer_list *t);
243 static irqreturn_t swim3_interrupt(int irq, void *dev_id);
244 /*static void fd_dma_interrupt(int irq, void *dev_id);*/
245 static int grab_drive(struct floppy_state *fs, enum swim_state state,
246 int interruptible);
247 static void release_drive(struct floppy_state *fs);
248 static int fd_eject(struct floppy_state *fs);
249 static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
250 unsigned int cmd, unsigned long param);
251 static int floppy_open(struct block_device *bdev, fmode_t mode);
252 static void floppy_release(struct gendisk *disk, fmode_t mode);
253 static unsigned int floppy_check_events(struct gendisk *disk,
254 unsigned int clearing);
255 static int floppy_revalidate(struct gendisk *disk);
256
257 static bool swim3_end_request(struct floppy_state *fs, blk_status_t err, unsigned int nr_bytes)
258 {
259 struct request *req = fs->cur_req;
260
261 swim3_dbg(" end request, err=%d nr_bytes=%d, cur_req=%p\n",
262 err, nr_bytes, req);
263
264 if (err)
265 nr_bytes = blk_rq_cur_bytes(req);
266 if (blk_update_request(req, err, nr_bytes))
267 return true;
268 __blk_mq_end_request(req, err);
269 fs->cur_req = NULL;
270 return false;
271 }
272
273 static void swim3_select(struct floppy_state *fs, int sel)
274 {
275 struct swim3 __iomem *sw = fs->swim3;
276
277 out_8(&sw->select, RELAX);
278 if (sel & 8)
279 out_8(&sw->control_bis, SELECT);
280 else
281 out_8(&sw->control_bic, SELECT);
282 out_8(&sw->select, sel & CA_MASK);
283 }
284
285 static void swim3_action(struct floppy_state *fs, int action)
286 {
287 struct swim3 __iomem *sw = fs->swim3;
288
289 swim3_select(fs, action);
290 udelay(1);
291 out_8(&sw->select, sw->select | LSTRB);
292 udelay(2);
293 out_8(&sw->select, sw->select & ~LSTRB);
294 udelay(1);
295 }
296
297 static int swim3_readbit(struct floppy_state *fs, int bit)
298 {
299 struct swim3 __iomem *sw = fs->swim3;
300 int stat;
301
302 swim3_select(fs, bit);
303 udelay(1);
304 stat = in_8(&sw->status);
305 return (stat & DATA) == 0;
306 }
307
308 static blk_status_t swim3_queue_rq(struct blk_mq_hw_ctx *hctx,
309 const struct blk_mq_queue_data *bd)
310 {
311 struct floppy_state *fs = hctx->queue->queuedata;
312 struct request *req = bd->rq;
313 unsigned long x;
314
315 spin_lock_irq(&swim3_lock);
316 if (fs->cur_req || fs->state != idle) {
317 spin_unlock_irq(&swim3_lock);
318 return BLK_STS_DEV_RESOURCE;
319 }
320 blk_mq_start_request(req);
321 fs->cur_req = req;
322 if (fs->mdev->media_bay &&
323 check_media_bay(fs->mdev->media_bay) != MB_FD) {
324 swim3_dbg("%s", " media bay absent, dropping req\n");
325 swim3_end_request(fs, BLK_STS_IOERR, 0);
326 goto out;
327 }
328 if (fs->ejected) {
329 swim3_dbg("%s", " disk ejected\n");
330 swim3_end_request(fs, BLK_STS_IOERR, 0);
331 goto out;
332 }
333 if (rq_data_dir(req) == WRITE) {
334 if (fs->write_prot < 0)
335 fs->write_prot = swim3_readbit(fs, WRITE_PROT);
336 if (fs->write_prot) {
337 swim3_dbg("%s", " try to write, disk write protected\n");
338 swim3_end_request(fs, BLK_STS_IOERR, 0);
339 goto out;
340 }
341 }
342
343 /*
344 * Do not remove the cast. blk_rq_pos(req) is now a sector_t and can be
345 * 64 bits, but it will never go past 32 bits for this driver anyway, so
346 * we can safely cast it down and not have to do a 64/32 division
347 */
348 fs->req_cyl = ((long)blk_rq_pos(req)) / fs->secpercyl;
349 x = ((long)blk_rq_pos(req)) % fs->secpercyl;
350 fs->head = x / fs->secpertrack;
351 fs->req_sector = x % fs->secpertrack + 1;
352 fs->state = do_transfer;
353 fs->retries = 0;
354
355 act(fs);
356
357 out:
358 spin_unlock_irq(&swim3_lock);
359 return BLK_STS_OK;
360 }
361
362 static void set_timeout(struct floppy_state *fs, int nticks,
363 void (*proc)(struct timer_list *t))
364 {
365 if (fs->timeout_pending)
366 del_timer(&fs->timeout);
367 fs->timeout.expires = jiffies + nticks;
368 fs->timeout.function = proc;
369 add_timer(&fs->timeout);
370 fs->timeout_pending = 1;
371 }
372
373 static inline void scan_track(struct floppy_state *fs)
374 {
375 struct swim3 __iomem *sw = fs->swim3;
376
377 swim3_select(fs, READ_DATA_0);
378 in_8(&sw->intr); /* clear SEEN_SECTOR bit */
379 in_8(&sw->error);
380 out_8(&sw->intr_enable, SEEN_SECTOR);
381 out_8(&sw->control_bis, DO_ACTION);
382 /* enable intr when track found */
383 set_timeout(fs, HZ, scan_timeout); /* enable timeout */
384 }
385
386 static inline void seek_track(struct floppy_state *fs, int n)
387 {
388 struct swim3 __iomem *sw = fs->swim3;
389
390 if (n >= 0) {
391 swim3_action(fs, SEEK_POSITIVE);
392 sw->nseek = n;
393 } else {
394 swim3_action(fs, SEEK_NEGATIVE);
395 sw->nseek = -n;
396 }
397 fs->expect_cyl = (fs->cur_cyl >= 0)? fs->cur_cyl + n: -1;
398 swim3_select(fs, STEP);
399 in_8(&sw->error);
400 /* enable intr when seek finished */
401 out_8(&sw->intr_enable, SEEK_DONE);
402 out_8(&sw->control_bis, DO_SEEK);
403 set_timeout(fs, 3*HZ, seek_timeout); /* enable timeout */
404 fs->settle_time = 0;
405 }
406
407 static inline void init_dma(struct dbdma_cmd *cp, int cmd,
408 void *buf, int count)
409 {
410 cp->req_count = cpu_to_le16(count);
411 cp->command = cpu_to_le16(cmd);
412 cp->phy_addr = cpu_to_le32(virt_to_bus(buf));
413 cp->xfer_status = 0;
414 }
415
416 static inline void setup_transfer(struct floppy_state *fs)
417 {
418 int n;
419 struct swim3 __iomem *sw = fs->swim3;
420 struct dbdma_cmd *cp = fs->dma_cmd;
421 struct dbdma_regs __iomem *dr = fs->dma;
422 struct request *req = fs->cur_req;
423
424 if (blk_rq_cur_sectors(req) <= 0) {
425 swim3_warn("%s", "Transfer 0 sectors ?\n");
426 return;
427 }
428 if (rq_data_dir(req) == WRITE)
429 n = 1;
430 else {
431 n = fs->secpertrack - fs->req_sector + 1;
432 if (n > blk_rq_cur_sectors(req))
433 n = blk_rq_cur_sectors(req);
434 }
435
436 swim3_dbg(" setup xfer at sect %d (of %d) head %d for %d\n",
437 fs->req_sector, fs->secpertrack, fs->head, n);
438
439 fs->scount = n;
440 swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0);
441 out_8(&sw->sector, fs->req_sector);
442 out_8(&sw->nsect, n);
443 out_8(&sw->gap3, 0);
444 out_le32(&dr->cmdptr, virt_to_bus(cp));
445 if (rq_data_dir(req) == WRITE) {
446 /* Set up 3 dma commands: write preamble, data, postamble */
447 init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble));
448 ++cp;
449 init_dma(cp, OUTPUT_MORE, bio_data(req->bio), 512);
450 ++cp;
451 init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble));
452 } else {
453 init_dma(cp, INPUT_LAST, bio_data(req->bio), n * 512);
454 }
455 ++cp;
456 out_le16(&cp->command, DBDMA_STOP);
457 out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
458 in_8(&sw->error);
459 out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
460 if (rq_data_dir(req) == WRITE)
461 out_8(&sw->control_bis, WRITE_SECTORS);
462 in_8(&sw->intr);
463 out_le32(&dr->control, (RUN << 16) | RUN);
464 /* enable intr when transfer complete */
465 out_8(&sw->intr_enable, TRANSFER_DONE);
466 out_8(&sw->control_bis, DO_ACTION);
467 set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */
468 }
469
470 static void act(struct floppy_state *fs)
471 {
472 for (;;) {
473 swim3_dbg(" act loop, state=%d, req_cyl=%d, cur_cyl=%d\n",
474 fs->state, fs->req_cyl, fs->cur_cyl);
475
476 switch (fs->state) {
477 case idle:
478 return; /* XXX shouldn't get here */
479
480 case locating:
481 if (swim3_readbit(fs, TRACK_ZERO)) {
482 swim3_dbg("%s", " locate track 0\n");
483 fs->cur_cyl = 0;
484 if (fs->req_cyl == 0)
485 fs->state = do_transfer;
486 else
487 fs->state = seeking;
488 break;
489 }
490 scan_track(fs);
491 return;
492
493 case seeking:
494 if (fs->cur_cyl < 0) {
495 fs->expect_cyl = -1;
496 fs->state = locating;
497 break;
498 }
499 if (fs->req_cyl == fs->cur_cyl) {
500 swim3_warn("%s", "Whoops, seeking 0\n");
501 fs->state = do_transfer;
502 break;
503 }
504 seek_track(fs, fs->req_cyl - fs->cur_cyl);
505 return;
506
507 case settling:
508 /* check for SEEK_COMPLETE after 30ms */
509 fs->settle_time = (HZ + 32) / 33;
510 set_timeout(fs, fs->settle_time, settle_timeout);
511 return;
512
513 case do_transfer:
514 if (fs->cur_cyl != fs->req_cyl) {
515 if (fs->retries > 5) {
516 swim3_err("Wrong cylinder in transfer, want: %d got %d\n",
517 fs->req_cyl, fs->cur_cyl);
518 swim3_end_request(fs, BLK_STS_IOERR, 0);
519 fs->state = idle;
520 return;
521 }
522 fs->state = seeking;
523 break;
524 }
525 setup_transfer(fs);
526 return;
527
528 case jogging:
529 seek_track(fs, -5);
530 return;
531
532 default:
533 swim3_err("Unknown state %d\n", fs->state);
534 return;
535 }
536 }
537 }
538
539 static void scan_timeout(struct timer_list *t)
540 {
541 struct floppy_state *fs = from_timer(fs, t, timeout);
542 struct swim3 __iomem *sw = fs->swim3;
543 unsigned long flags;
544
545 swim3_dbg("* scan timeout, state=%d\n", fs->state);
546
547 spin_lock_irqsave(&swim3_lock, flags);
548 fs->timeout_pending = 0;
549 out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
550 out_8(&sw->select, RELAX);
551 out_8(&sw->intr_enable, 0);
552 fs->cur_cyl = -1;
553 if (fs->retries > 5) {
554 swim3_end_request(fs, BLK_STS_IOERR, 0);
555 fs->state = idle;
556 } else {
557 fs->state = jogging;
558 act(fs);
559 }
560 spin_unlock_irqrestore(&swim3_lock, flags);
561 }
562
563 static void seek_timeout(struct timer_list *t)
564 {
565 struct floppy_state *fs = from_timer(fs, t, timeout);
566 struct swim3 __iomem *sw = fs->swim3;
567 unsigned long flags;
568
569 swim3_dbg("* seek timeout, state=%d\n", fs->state);
570
571 spin_lock_irqsave(&swim3_lock, flags);
572 fs->timeout_pending = 0;
573 out_8(&sw->control_bic, DO_SEEK);
574 out_8(&sw->select, RELAX);
575 out_8(&sw->intr_enable, 0);
576 swim3_err("%s", "Seek timeout\n");
577 swim3_end_request(fs, BLK_STS_IOERR, 0);
578 fs->state = idle;
579 spin_unlock_irqrestore(&swim3_lock, flags);
580 }
581
582 static void settle_timeout(struct timer_list *t)
583 {
584 struct floppy_state *fs = from_timer(fs, t, timeout);
585 struct swim3 __iomem *sw = fs->swim3;
586 unsigned long flags;
587
588 swim3_dbg("* settle timeout, state=%d\n", fs->state);
589
590 spin_lock_irqsave(&swim3_lock, flags);
591 fs->timeout_pending = 0;
592 if (swim3_readbit(fs, SEEK_COMPLETE)) {
593 out_8(&sw->select, RELAX);
594 fs->state = locating;
595 act(fs);
596 goto unlock;
597 }
598 out_8(&sw->select, RELAX);
599 if (fs->settle_time < 2*HZ) {
600 ++fs->settle_time;
601 set_timeout(fs, 1, settle_timeout);
602 goto unlock;
603 }
604 swim3_err("%s", "Seek settle timeout\n");
605 swim3_end_request(fs, BLK_STS_IOERR, 0);
606 fs->state = idle;
607 unlock:
608 spin_unlock_irqrestore(&swim3_lock, flags);
609 }
610
611 static void xfer_timeout(struct timer_list *t)
612 {
613 struct floppy_state *fs = from_timer(fs, t, timeout);
614 struct swim3 __iomem *sw = fs->swim3;
615 struct dbdma_regs __iomem *dr = fs->dma;
616 unsigned long flags;
617 int n;
618
619 swim3_dbg("* xfer timeout, state=%d\n", fs->state);
620
621 spin_lock_irqsave(&swim3_lock, flags);
622 fs->timeout_pending = 0;
623 out_le32(&dr->control, RUN << 16);
624 /* We must wait a bit for dbdma to stop */
625 for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++)
626 udelay(1);
627 out_8(&sw->intr_enable, 0);
628 out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
629 out_8(&sw->select, RELAX);
630 swim3_err("Timeout %sing sector %ld\n",
631 (rq_data_dir(fs->cur_req)==WRITE? "writ": "read"),
632 (long)blk_rq_pos(fs->cur_req));
633 swim3_end_request(fs, BLK_STS_IOERR, 0);
634 fs->state = idle;
635 spin_unlock_irqrestore(&swim3_lock, flags);
636 }
637
638 static irqreturn_t swim3_interrupt(int irq, void *dev_id)
639 {
640 struct floppy_state *fs = (struct floppy_state *) dev_id;
641 struct swim3 __iomem *sw = fs->swim3;
642 int intr, err, n;
643 int stat, resid;
644 struct dbdma_regs __iomem *dr;
645 struct dbdma_cmd *cp;
646 unsigned long flags;
647 struct request *req = fs->cur_req;
648
649 swim3_dbg("* interrupt, state=%d\n", fs->state);
650
651 spin_lock_irqsave(&swim3_lock, flags);
652 intr = in_8(&sw->intr);
653 err = (intr & ERROR_INTR)? in_8(&sw->error): 0;
654 if ((intr & ERROR_INTR) && fs->state != do_transfer)
655 swim3_err("Non-transfer error interrupt: state=%d, dir=%x, intr=%x, err=%x\n",
656 fs->state, rq_data_dir(req), intr, err);
657 switch (fs->state) {
658 case locating:
659 if (intr & SEEN_SECTOR) {
660 out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
661 out_8(&sw->select, RELAX);
662 out_8(&sw->intr_enable, 0);
663 del_timer(&fs->timeout);
664 fs->timeout_pending = 0;
665 if (sw->ctrack == 0xff) {
666 swim3_err("%s", "Seen sector but cyl=ff?\n");
667 fs->cur_cyl = -1;
668 if (fs->retries > 5) {
669 swim3_end_request(fs, BLK_STS_IOERR, 0);
670 fs->state = idle;
671 } else {
672 fs->state = jogging;
673 act(fs);
674 }
675 break;
676 }
677 fs->cur_cyl = sw->ctrack;
678 fs->cur_sector = sw->csect;
679 if (fs->expect_cyl != -1 && fs->expect_cyl != fs->cur_cyl)
680 swim3_err("Expected cyl %d, got %d\n",
681 fs->expect_cyl, fs->cur_cyl);
682 fs->state = do_transfer;
683 act(fs);
684 }
685 break;
686 case seeking:
687 case jogging:
688 if (sw->nseek == 0) {
689 out_8(&sw->control_bic, DO_SEEK);
690 out_8(&sw->select, RELAX);
691 out_8(&sw->intr_enable, 0);
692 del_timer(&fs->timeout);
693 fs->timeout_pending = 0;
694 if (fs->state == seeking)
695 ++fs->retries;
696 fs->state = settling;
697 act(fs);
698 }
699 break;
700 case settling:
701 out_8(&sw->intr_enable, 0);
702 del_timer(&fs->timeout);
703 fs->timeout_pending = 0;
704 act(fs);
705 break;
706 case do_transfer:
707 if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0)
708 break;
709 out_8(&sw->intr_enable, 0);
710 out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
711 out_8(&sw->select, RELAX);
712 del_timer(&fs->timeout);
713 fs->timeout_pending = 0;
714 dr = fs->dma;
715 cp = fs->dma_cmd;
716 if (rq_data_dir(req) == WRITE)
717 ++cp;
718 /*
719 * Check that the main data transfer has finished.
720 * On writing, the swim3 sometimes doesn't use
721 * up all the bytes of the postamble, so we can still
722 * see DMA active here. That doesn't matter as long
723 * as all the sector data has been transferred.
724 */
725 if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) {
726 /* wait a little while for DMA to complete */
727 for (n = 0; n < 100; ++n) {
728 if (cp->xfer_status != 0)
729 break;
730 udelay(1);
731 barrier();
732 }
733 }
734 /* turn off DMA */
735 out_le32(&dr->control, (RUN | PAUSE) << 16);
736 stat = le16_to_cpu(cp->xfer_status);
737 resid = le16_to_cpu(cp->res_count);
738 if (intr & ERROR_INTR) {
739 n = fs->scount - 1 - resid / 512;
740 if (n > 0) {
741 blk_update_request(req, 0, n << 9);
742 fs->req_sector += n;
743 }
744 if (fs->retries < 5) {
745 ++fs->retries;
746 act(fs);
747 } else {
748 swim3_err("Error %sing block %ld (err=%x)\n",
749 rq_data_dir(req) == WRITE? "writ": "read",
750 (long)blk_rq_pos(req), err);
751 swim3_end_request(fs, BLK_STS_IOERR, 0);
752 fs->state = idle;
753 }
754 } else {
755 if ((stat & ACTIVE) == 0 || resid != 0) {
756 /* musta been an error */
757 swim3_err("fd dma error: stat=%x resid=%d\n", stat, resid);
758 swim3_err(" state=%d, dir=%x, intr=%x, err=%x\n",
759 fs->state, rq_data_dir(req), intr, err);
760 swim3_end_request(fs, BLK_STS_IOERR, 0);
761 fs->state = idle;
762 break;
763 }
764 fs->retries = 0;
765 if (swim3_end_request(fs, 0, fs->scount << 9)) {
766 fs->req_sector += fs->scount;
767 if (fs->req_sector > fs->secpertrack) {
768 fs->req_sector -= fs->secpertrack;
769 if (++fs->head > 1) {
770 fs->head = 0;
771 ++fs->req_cyl;
772 }
773 }
774 act(fs);
775 } else
776 fs->state = idle;
777 }
778 break;
779 default:
780 swim3_err("Don't know what to do in state %d\n", fs->state);
781 }
782 spin_unlock_irqrestore(&swim3_lock, flags);
783 return IRQ_HANDLED;
784 }
785
786 /*
787 static void fd_dma_interrupt(int irq, void *dev_id)
788 {
789 }
790 */
791
792 /* Called under the mutex to grab exclusive access to a drive */
793 static int grab_drive(struct floppy_state *fs, enum swim_state state,
794 int interruptible)
795 {
796 unsigned long flags;
797
798 swim3_dbg("%s", "-> grab drive\n");
799
800 spin_lock_irqsave(&swim3_lock, flags);
801 if (fs->state != idle && fs->state != available) {
802 ++fs->wanted;
803 /* this will enable irqs in order to sleep */
804 if (!interruptible)
805 wait_event_lock_irq(fs->wait,
806 fs->state == available,
807 swim3_lock);
808 else if (wait_event_interruptible_lock_irq(fs->wait,
809 fs->state == available,
810 swim3_lock)) {
811 --fs->wanted;
812 spin_unlock_irqrestore(&swim3_lock, flags);
813 return -EINTR;
814 }
815 --fs->wanted;
816 }
817 fs->state = state;
818 spin_unlock_irqrestore(&swim3_lock, flags);
819
820 return 0;
821 }
822
823 static void release_drive(struct floppy_state *fs)
824 {
825 struct request_queue *q = disks[fs->index]->queue;
826 unsigned long flags;
827
828 swim3_dbg("%s", "-> release drive\n");
829
830 spin_lock_irqsave(&swim3_lock, flags);
831 fs->state = idle;
832 spin_unlock_irqrestore(&swim3_lock, flags);
833
834 blk_mq_freeze_queue(q);
835 blk_mq_quiesce_queue(q);
836 blk_mq_unquiesce_queue(q);
837 blk_mq_unfreeze_queue(q);
838 }
839
840 static int fd_eject(struct floppy_state *fs)
841 {
842 int err, n;
843
844 err = grab_drive(fs, ejecting, 1);
845 if (err)
846 return err;
847 swim3_action(fs, EJECT);
848 for (n = 20; n > 0; --n) {
849 if (signal_pending(current)) {
850 err = -EINTR;
851 break;
852 }
853 swim3_select(fs, RELAX);
854 schedule_timeout_interruptible(1);
855 if (swim3_readbit(fs, DISK_IN) == 0)
856 break;
857 }
858 swim3_select(fs, RELAX);
859 udelay(150);
860 fs->ejected = 1;
861 release_drive(fs);
862 return err;
863 }
864
865 static struct floppy_struct floppy_type =
866 { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,NULL }; /* 7 1.44MB 3.5" */
867
868 static int floppy_locked_ioctl(struct block_device *bdev, fmode_t mode,
869 unsigned int cmd, unsigned long param)
870 {
871 struct floppy_state *fs = bdev->bd_disk->private_data;
872 int err;
873
874 if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))
875 return -EPERM;
876
877 if (fs->mdev->media_bay &&
878 check_media_bay(fs->mdev->media_bay) != MB_FD)
879 return -ENXIO;
880
881 switch (cmd) {
882 case FDEJECT:
883 if (fs->ref_count != 1)
884 return -EBUSY;
885 err = fd_eject(fs);
886 return err;
887 case FDGETPRM:
888 if (copy_to_user((void __user *) param, &floppy_type,
889 sizeof(struct floppy_struct)))
890 return -EFAULT;
891 return 0;
892 }
893 return -ENOTTY;
894 }
895
896 static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
897 unsigned int cmd, unsigned long param)
898 {
899 int ret;
900
901 mutex_lock(&swim3_mutex);
902 ret = floppy_locked_ioctl(bdev, mode, cmd, param);
903 mutex_unlock(&swim3_mutex);
904
905 return ret;
906 }
907
908 static int floppy_open(struct block_device *bdev, fmode_t mode)
909 {
910 struct floppy_state *fs = bdev->bd_disk->private_data;
911 struct swim3 __iomem *sw = fs->swim3;
912 int n, err = 0;
913
914 if (fs->ref_count == 0) {
915 if (fs->mdev->media_bay &&
916 check_media_bay(fs->mdev->media_bay) != MB_FD)
917 return -ENXIO;
918 out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2);
919 out_8(&sw->control_bic, 0xff);
920 out_8(&sw->mode, 0x95);
921 udelay(10);
922 out_8(&sw->intr_enable, 0);
923 out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE);
924 swim3_action(fs, MOTOR_ON);
925 fs->write_prot = -1;
926 fs->cur_cyl = -1;
927 for (n = 0; n < 2 * HZ; ++n) {
928 if (n >= HZ/30 && swim3_readbit(fs, SEEK_COMPLETE))
929 break;
930 if (signal_pending(current)) {
931 err = -EINTR;
932 break;
933 }
934 swim3_select(fs, RELAX);
935 schedule_timeout_interruptible(1);
936 }
937 if (err == 0 && (swim3_readbit(fs, SEEK_COMPLETE) == 0
938 || swim3_readbit(fs, DISK_IN) == 0))
939 err = -ENXIO;
940 swim3_action(fs, SETMFM);
941 swim3_select(fs, RELAX);
942
943 } else if (fs->ref_count == -1 || mode & FMODE_EXCL)
944 return -EBUSY;
945
946 if (err == 0 && (mode & FMODE_NDELAY) == 0
947 && (mode & (FMODE_READ|FMODE_WRITE))) {
948 check_disk_change(bdev);
949 if (fs->ejected)
950 err = -ENXIO;
951 }
952
953 if (err == 0 && (mode & FMODE_WRITE)) {
954 if (fs->write_prot < 0)
955 fs->write_prot = swim3_readbit(fs, WRITE_PROT);
956 if (fs->write_prot)
957 err = -EROFS;
958 }
959
960 if (err) {
961 if (fs->ref_count == 0) {
962 swim3_action(fs, MOTOR_OFF);
963 out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE);
964 swim3_select(fs, RELAX);
965 }
966 return err;
967 }
968
969 if (mode & FMODE_EXCL)
970 fs->ref_count = -1;
971 else
972 ++fs->ref_count;
973
974 return 0;
975 }
976
977 static int floppy_unlocked_open(struct block_device *bdev, fmode_t mode)
978 {
979 int ret;
980
981 mutex_lock(&swim3_mutex);
982 ret = floppy_open(bdev, mode);
983 mutex_unlock(&swim3_mutex);
984
985 return ret;
986 }
987
988 static void floppy_release(struct gendisk *disk, fmode_t mode)
989 {
990 struct floppy_state *fs = disk->private_data;
991 struct swim3 __iomem *sw = fs->swim3;
992
993 mutex_lock(&swim3_mutex);
994 if (fs->ref_count > 0)
995 --fs->ref_count;
996 else if (fs->ref_count == -1)
997 fs->ref_count = 0;
998 if (fs->ref_count == 0) {
999 swim3_action(fs, MOTOR_OFF);
1000 out_8(&sw->control_bic, 0xff);
1001 swim3_select(fs, RELAX);
1002 }
1003 mutex_unlock(&swim3_mutex);
1004 }
1005
1006 static unsigned int floppy_check_events(struct gendisk *disk,
1007 unsigned int clearing)
1008 {
1009 struct floppy_state *fs = disk->private_data;
1010 return fs->ejected ? DISK_EVENT_MEDIA_CHANGE : 0;
1011 }
1012
1013 static int floppy_revalidate(struct gendisk *disk)
1014 {
1015 struct floppy_state *fs = disk->private_data;
1016 struct swim3 __iomem *sw;
1017 int ret, n;
1018
1019 if (fs->mdev->media_bay &&
1020 check_media_bay(fs->mdev->media_bay) != MB_FD)
1021 return -ENXIO;
1022
1023 sw = fs->swim3;
1024 grab_drive(fs, revalidating, 0);
1025 out_8(&sw->intr_enable, 0);
1026 out_8(&sw->control_bis, DRIVE_ENABLE);
1027 swim3_action(fs, MOTOR_ON); /* necessary? */
1028 fs->write_prot = -1;
1029 fs->cur_cyl = -1;
1030 mdelay(1);
1031 for (n = HZ; n > 0; --n) {
1032 if (swim3_readbit(fs, SEEK_COMPLETE))
1033 break;
1034 if (signal_pending(current))
1035 break;
1036 swim3_select(fs, RELAX);
1037 schedule_timeout_interruptible(1);
1038 }
1039 ret = swim3_readbit(fs, SEEK_COMPLETE) == 0
1040 || swim3_readbit(fs, DISK_IN) == 0;
1041 if (ret)
1042 swim3_action(fs, MOTOR_OFF);
1043 else {
1044 fs->ejected = 0;
1045 swim3_action(fs, SETMFM);
1046 }
1047 swim3_select(fs, RELAX);
1048
1049 release_drive(fs);
1050 return ret;
1051 }
1052
1053 static const struct block_device_operations floppy_fops = {
1054 .open = floppy_unlocked_open,
1055 .release = floppy_release,
1056 .ioctl = floppy_ioctl,
1057 .check_events = floppy_check_events,
1058 .revalidate_disk= floppy_revalidate,
1059 };
1060
1061 static const struct blk_mq_ops swim3_mq_ops = {
1062 .queue_rq = swim3_queue_rq,
1063 };
1064
1065 static void swim3_mb_event(struct macio_dev* mdev, int mb_state)
1066 {
1067 struct floppy_state *fs = macio_get_drvdata(mdev);
1068 struct swim3 __iomem *sw;
1069
1070 if (!fs)
1071 return;
1072
1073 sw = fs->swim3;
1074
1075 if (mb_state != MB_FD)
1076 return;
1077
1078 /* Clear state */
1079 out_8(&sw->intr_enable, 0);
1080 in_8(&sw->intr);
1081 in_8(&sw->error);
1082 }
1083
1084 static int swim3_add_device(struct macio_dev *mdev, int index)
1085 {
1086 struct device_node *swim = mdev->ofdev.dev.of_node;
1087 struct floppy_state *fs = &floppy_states[index];
1088 int rc = -EBUSY;
1089
1090 fs->mdev = mdev;
1091 fs->index = index;
1092
1093 /* Check & Request resources */
1094 if (macio_resource_count(mdev) < 2) {
1095 swim3_err("%s", "No address in device-tree\n");
1096 return -ENXIO;
1097 }
1098 if (macio_irq_count(mdev) < 1) {
1099 swim3_err("%s", "No interrupt in device-tree\n");
1100 return -ENXIO;
1101 }
1102 if (macio_request_resource(mdev, 0, "swim3 (mmio)")) {
1103 swim3_err("%s", "Can't request mmio resource\n");
1104 return -EBUSY;
1105 }
1106 if (macio_request_resource(mdev, 1, "swim3 (dma)")) {
1107 swim3_err("%s", "Can't request dma resource\n");
1108 macio_release_resource(mdev, 0);
1109 return -EBUSY;
1110 }
1111 dev_set_drvdata(&mdev->ofdev.dev, fs);
1112
1113 if (mdev->media_bay == NULL)
1114 pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1);
1115
1116 fs->state = idle;
1117 fs->swim3 = (struct swim3 __iomem *)
1118 ioremap(macio_resource_start(mdev, 0), 0x200);
1119 if (fs->swim3 == NULL) {
1120 swim3_err("%s", "Couldn't map mmio registers\n");
1121 rc = -ENOMEM;
1122 goto out_release;
1123 }
1124 fs->dma = (struct dbdma_regs __iomem *)
1125 ioremap(macio_resource_start(mdev, 1), 0x200);
1126 if (fs->dma == NULL) {
1127 swim3_err("%s", "Couldn't map dma registers\n");
1128 iounmap(fs->swim3);
1129 rc = -ENOMEM;
1130 goto out_release;
1131 }
1132 fs->swim3_intr = macio_irq(mdev, 0);
1133 fs->dma_intr = macio_irq(mdev, 1);
1134 fs->cur_cyl = -1;
1135 fs->cur_sector = -1;
1136 fs->secpercyl = 36;
1137 fs->secpertrack = 18;
1138 fs->total_secs = 2880;
1139 init_waitqueue_head(&fs->wait);
1140
1141 fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space);
1142 memset(fs->dma_cmd, 0, 2 * sizeof(struct dbdma_cmd));
1143 fs->dma_cmd[1].command = cpu_to_le16(DBDMA_STOP);
1144
1145 if (mdev->media_bay == NULL || check_media_bay(mdev->media_bay) == MB_FD)
1146 swim3_mb_event(mdev, MB_FD);
1147
1148 if (request_irq(fs->swim3_intr, swim3_interrupt, 0, "SWIM3", fs)) {
1149 swim3_err("%s", "Couldn't request interrupt\n");
1150 pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 0);
1151 goto out_unmap;
1152 }
1153
1154 timer_setup(&fs->timeout, NULL, 0);
1155
1156 swim3_info("SWIM3 floppy controller %s\n",
1157 mdev->media_bay ? "in media bay" : "");
1158
1159 return 0;
1160
1161 out_unmap:
1162 iounmap(fs->dma);
1163 iounmap(fs->swim3);
1164
1165 out_release:
1166 macio_release_resource(mdev, 0);
1167 macio_release_resource(mdev, 1);
1168
1169 return rc;
1170 }
1171
1172 static int swim3_attach(struct macio_dev *mdev,
1173 const struct of_device_id *match)
1174 {
1175 struct floppy_state *fs;
1176 struct gendisk *disk;
1177 int rc;
1178
1179 if (floppy_count >= MAX_FLOPPIES)
1180 return -ENXIO;
1181
1182 if (floppy_count == 0) {
1183 rc = register_blkdev(FLOPPY_MAJOR, "fd");
1184 if (rc)
1185 return rc;
1186 }
1187
1188 disk = alloc_disk(1);
1189 if (disk == NULL) {
1190 rc = -ENOMEM;
1191 goto out_unregister;
1192 }
1193
1194 fs = &floppy_states[floppy_count];
1195 memset(fs, 0, sizeof(*fs));
1196
1197 disk->queue = blk_mq_init_sq_queue(&fs->tag_set, &swim3_mq_ops, 2,
1198 BLK_MQ_F_SHOULD_MERGE);
1199 if (IS_ERR(disk->queue)) {
1200 rc = PTR_ERR(disk->queue);
1201 disk->queue = NULL;
1202 goto out_put_disk;
1203 }
1204 blk_queue_bounce_limit(disk->queue, BLK_BOUNCE_HIGH);
1205 disk->queue->queuedata = fs;
1206
1207 rc = swim3_add_device(mdev, floppy_count);
1208 if (rc)
1209 goto out_cleanup_queue;
1210
1211 disk->major = FLOPPY_MAJOR;
1212 disk->first_minor = floppy_count;
1213 disk->fops = &floppy_fops;
1214 disk->private_data = fs;
1215 disk->events = DISK_EVENT_MEDIA_CHANGE;
1216 disk->flags |= GENHD_FL_REMOVABLE;
1217 sprintf(disk->disk_name, "fd%d", floppy_count);
1218 set_capacity(disk, 2880);
1219 add_disk(disk);
1220
1221 disks[floppy_count++] = disk;
1222 return 0;
1223
1224 out_cleanup_queue:
1225 blk_cleanup_queue(disk->queue);
1226 disk->queue = NULL;
1227 blk_mq_free_tag_set(&fs->tag_set);
1228 out_put_disk:
1229 put_disk(disk);
1230 out_unregister:
1231 if (floppy_count == 0)
1232 unregister_blkdev(FLOPPY_MAJOR, "fd");
1233 return rc;
1234 }
1235
1236 static const struct of_device_id swim3_match[] =
1237 {
1238 {
1239 .name = "swim3",
1240 },
1241 {
1242 .compatible = "ohare-swim3"
1243 },
1244 {
1245 .compatible = "swim3"
1246 },
1247 { /* end of list */ }
1248 };
1249
1250 static struct macio_driver swim3_driver =
1251 {
1252 .driver = {
1253 .name = "swim3",
1254 .of_match_table = swim3_match,
1255 },
1256 .probe = swim3_attach,
1257 #ifdef CONFIG_PMAC_MEDIABAY
1258 .mediabay_event = swim3_mb_event,
1259 #endif
1260 #if 0
1261 .suspend = swim3_suspend,
1262 .resume = swim3_resume,
1263 #endif
1264 };
1265
1266
1267 int swim3_init(void)
1268 {
1269 macio_register_driver(&swim3_driver);
1270 return 0;
1271 }
1272
1273 module_init(swim3_init)
1274
1275 MODULE_LICENSE("GPL");
1276 MODULE_AUTHOR("Paul Mackerras");
1277 MODULE_ALIAS_BLOCKDEV_MAJOR(FLOPPY_MAJOR);
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