drivers/block/systemace.c

   1 /*
   2  * Copyright (c) 2004 Picture Elements, Inc.
   3  *    Stephen Williams (XXXXXXXXXXXXXXXX)
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * The Xilinx SystemACE chip support is activated by defining
  10  * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE
  11  * to set the base address of the device. This code currently
  12  * assumes that the chip is connected via a byte-wide bus.
  13  *
  14  * The CONFIG_SYSTEMACE also adds to fat support the device class
  15  * "ace" that allows the user to execute "fatls ace 0" and the
  16  * like. This works by making the systemace_get_dev function
  17  * available to cmd_fat.c:get_dev and filling in a block device
  18  * description that has all the bits needed for FAT support to
  19  * read sectors.
  20  *
  21  * According to Xilinx technical support, before accessing the
  22  * SystemACE CF you need to set the following control bits:
  23  *      FORCECFGMODE : 1
  24  *      CFGMODE : 0
  25  *      CFGSTART : 0
  26  */
  27
  28 #include <common.h>
  29 #include <command.h>
  30 #include <dm.h>
  31 #include <part.h>
  32 #include <asm/io.h>
  33
  34 /*
  35  * The ace_readw and writew functions read/write 16bit words, but the
  36  * offset value is the BYTE offset as most used in the Xilinx
  37  * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined
  38  * to be the base address for the chip, usually in the local
  39  * peripheral bus.
  40  */
  41
  42 static u32 base = CONFIG_SYS_SYSTEMACE_BASE;
  43 static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH;
  44
  45 static void ace_writew(u16 val, unsigned off)
  46 {
  47         if (width == 8) {
  48 #if !defined(__BIG_ENDIAN)
  49                 writeb(val >> 8, base + off);
  50                 writeb(val, base + off + 1);
  51 #else
  52                 writeb(val, base + off);
  53                 writeb(val >> 8, base + off + 1);
  54 #endif
  55         } else
  56                 out16(base + off, val);
  57 }
  58
  59 static u16 ace_readw(unsigned off)
  60 {
  61         if (width == 8) {
  62 #if !defined(__BIG_ENDIAN)
  63                 return (readb(base + off) << 8) | readb(base + off + 1);
  64 #else
  65                 return readb(base + off) | (readb(base + off + 1) << 8);
  66 #endif
  67         }
  68
  69         return in16(base + off);
  70 }
  71
  72 #ifndef CONFIG_BLK
  73 static struct blk_desc systemace_dev = { 0 };
  74 #endif
  75
  76 static int get_cf_lock(void)
  77 {
  78         int retry = 10;
  79
  80         /* CONTROLREG = LOCKREG */
  81         unsigned val = ace_readw(0x18);
  82         val |= 0x0002;
  83         ace_writew((val & 0xffff), 0x18);
  84
  85         /* Wait for MPULOCK in STATUSREG[15:0] */
  86         while (!(ace_readw(0x04) & 0x0002)) {
  87
  88                 if (retry < 0)
  89                         return -1;
  90
  91                 udelay(100000);
  92                 retry -= 1;
  93         }
  94
  95         return 0;
  96 }
  97
  98 static void release_cf_lock(void)
  99 {
 100         unsigned val = ace_readw(0x18);
 101         val &= ~(0x0002);
 102         ace_writew((val & 0xffff), 0x18);
 103 }
 104
 105 /*
 106  * This function is called (by dereferencing the block_read pointer in
 107  * the dev_desc) to read blocks of data. The return value is the
 108  * number of blocks read. A zero return indicates an error.
 109  */
 110 #ifdef CONFIG_BLK
 111 static unsigned long systemace_read(struct udevice *dev, unsigned long start,
 112                                     lbaint_t blkcnt, void *buffer)
 113 #else
 114 static unsigned long systemace_read(struct blk_desc *block_dev,
 115                                     unsigned long start, lbaint_t blkcnt,
 116                                     void *buffer)
 117 #endif
 118 {
 119         int retry;
 120         unsigned blk_countdown;
 121         unsigned char *dp = buffer;
 122         unsigned val;
 123
 124         if (get_cf_lock() < 0) {
 125                 unsigned status = ace_readw(0x04);
 126
 127                 /* If CFDETECT is false, card is missing. */
 128                 if (!(status & 0x0010)) {
 129                         printf("** CompactFlash card not present. **\n");
 130                         return 0;
 131                 }
 132
 133                 printf("**** ACE locked away from me (STATUSREG=%04x)\n",
 134                        status);
 135                 return 0;
 136         }
 137 #ifdef DEBUG_SYSTEMACE
 138         printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
 139 #endif
 140
 141         retry = 2000;
 142         for (;;) {
 143                 val = ace_readw(0x04);
 144
 145                 /* If CFDETECT is false, card is missing. */
 146                 if (!(val & 0x0010)) {
 147                         printf("**** ACE CompactFlash not found.\n");
 148                         release_cf_lock();
 149                         return 0;
 150                 }
 151
 152                 /* If RDYFORCMD, then we are ready to go. */
 153                 if (val & 0x0100)
 154                         break;
 155
 156                 if (retry < 0) {
 157                         printf("**** SystemACE not ready.\n");
 158                         release_cf_lock();
 159                         return 0;
 160                 }
 161
 162                 udelay(1000);
 163                 retry -= 1;
 164         }
 165
 166         /* The SystemACE can only transfer 256 sectors at a time, so
 167            limit the current chunk of sectors. The blk_countdown
 168            variable is the number of sectors left to transfer. */
 169
 170         blk_countdown = blkcnt;
 171         while (blk_countdown > 0) {
 172                 unsigned trans = blk_countdown;
 173
 174                 if (trans > 256)
 175                         trans = 256;
 176
 177 #ifdef DEBUG_SYSTEMACE
 178                 printf("... transfer %lu sector in a chunk\n", trans);
 179 #endif
 180                 /* Write LBA block address */
 181                 ace_writew((start >> 0) & 0xffff, 0x10);
 182                 ace_writew((start >> 16) & 0x0fff, 0x12);
 183
 184                 /* NOTE: in the Write Sector count below, a count of 0
 185                    causes a transfer of 256, so &0xff gives the right
 186                    value for whatever transfer count we want. */
 187
 188                 /* Write sector count | ReadMemCardData. */
 189                 ace_writew((trans & 0xff) | 0x0300, 0x14);
 190
 191 /*
 192  * For FPGA configuration via SystemACE is reset unacceptable
 193  * CFGDONE bit in STATUSREG is not set to 1.
 194  */
 195 #ifndef SYSTEMACE_CONFIG_FPGA
 196                 /* Reset the configruation controller */
 197                 val = ace_readw(0x18);
 198                 val |= 0x0080;
 199                 ace_writew(val, 0x18);
 200 #endif
 201
 202                 retry = trans * 16;
 203                 while (retry > 0) {
 204                         int idx;
 205
 206                         /* Wait for buffer to become ready. */
 207                         while (!(ace_readw(0x04) & 0x0020)) {
 208                                 udelay(100);
 209                         }
 210
 211                         /* Read 16 words of 2bytes from the sector buffer. */
 212                         for (idx = 0; idx < 16; idx += 1) {
 213                                 unsigned short val = ace_readw(0x40);
 214                                 *dp++ = val & 0xff;
 215                                 *dp++ = (val >> 8) & 0xff;
 216                         }
 217
 218                         retry -= 1;
 219                 }
 220
 221                 /* Clear the configruation controller reset */
 222                 val = ace_readw(0x18);
 223                 val &= ~0x0080;
 224                 ace_writew(val, 0x18);
 225
 226                 /* Count the blocks we transfer this time. */
 227                 start += trans;
 228                 blk_countdown -= trans;
 229         }
 230
 231         release_cf_lock();
 232
 233         return blkcnt;
 234 }
 235
 236 #ifdef CONFIG_BLK
 237 static int systemace_bind(struct udevice *dev)
 238 {
 239         struct blk_desc *bdesc;
 240         struct udevice *bdev;
 241         int ret;
 242
 243         ret = blk_create_devicef(dev, "systemace_blk", "blk", IF_TYPE_SYSTEMACE,
 244                                  -1, 512, 0, &bdev);
 245         if (ret) {
 246                 debug("Cannot create block device\n");
 247                 return ret;
 248         }
 249         bdesc = dev_get_uclass_platdata(bdev);
 250         bdesc->removable = 1;
 251         bdesc->part_type = PART_TYPE_UNKNOWN;
 252         bdesc->log2blksz = LOG2(bdesc->blksz);
 253
 254         /* Ensure the correct bus mode (8/16 bits) gets enabled */
 255         ace_writew(width == 8 ? 0 : 0x0001, 0);
 256
 257         return 0;
 258 }
 259
 260 static const struct blk_ops systemace_blk_ops = {
 261         .read   = systemace_read,
 262 };
 263
 264 U_BOOT_DRIVER(systemace_blk) = {
 265         .name           = "systemace_blk",
 266         .id             = UCLASS_BLK,
 267         .ops            = &systemace_blk_ops,
 268         .bind           = systemace_bind,
 269 };
 270 #else
 271 static int systemace_get_dev(int dev, struct blk_desc **descp)
 272 {
 273         /* The first time through this, the systemace_dev object is
 274            not yet initialized. In that case, fill it in. */
 275         if (systemace_dev.blksz == 0) {
 276                 systemace_dev.if_type = IF_TYPE_UNKNOWN;
 277                 systemace_dev.devnum = 0;
 278                 systemace_dev.part_type = PART_TYPE_UNKNOWN;
 279                 systemace_dev.type = DEV_TYPE_HARDDISK;
 280                 systemace_dev.blksz = 512;
 281                 systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
 282                 systemace_dev.removable = 1;
 283                 systemace_dev.block_read = systemace_read;
 284
 285                 /*
 286                  * Ensure the correct bus mode (8/16 bits) gets enabled
 287                  */
 288                 ace_writew(width == 8 ? 0 : 0x0001, 0);
 289
 290                 part_init(&systemace_dev);
 291         }
 292         *descp = &systemace_dev;
 293
 294         return 0;
 295 }
 296
 297 U_BOOT_LEGACY_BLK(systemace) = {
 298         .if_typename    = "ace",
 299         .if_type        = IF_TYPE_SYSTEMACE,
 300         .max_devs       = 1,
 301         .get_dev        = systemace_get_dev,
 302 };
 303 #endif