drivers/bus/mhi/core/internal.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   4  *
   5  */
   6
   7 #ifndef _MHI_INT_H
   8 #define _MHI_INT_H
   9
  10 #include <linux/mhi.h>
  11
  12 extern struct bus_type mhi_bus_type;
  13
  14 /* MHI MMIO register mapping */
  15 #define PCI_INVALID_READ(val) (val == U32_MAX)
  16
  17 #define MHIREGLEN (0x0)
  18 #define MHIREGLEN_MHIREGLEN_MASK (0xFFFFFFFF)
  19 #define MHIREGLEN_MHIREGLEN_SHIFT (0)
  20
  21 #define MHIVER (0x8)
  22 #define MHIVER_MHIVER_MASK (0xFFFFFFFF)
  23 #define MHIVER_MHIVER_SHIFT (0)
  24
  25 #define MHICFG (0x10)
  26 #define MHICFG_NHWER_MASK (0xFF000000)
  27 #define MHICFG_NHWER_SHIFT (24)
  28 #define MHICFG_NER_MASK (0xFF0000)
  29 #define MHICFG_NER_SHIFT (16)
  30 #define MHICFG_NHWCH_MASK (0xFF00)
  31 #define MHICFG_NHWCH_SHIFT (8)
  32 #define MHICFG_NCH_MASK (0xFF)
  33 #define MHICFG_NCH_SHIFT (0)
  34
  35 #define CHDBOFF (0x18)
  36 #define CHDBOFF_CHDBOFF_MASK (0xFFFFFFFF)
  37 #define CHDBOFF_CHDBOFF_SHIFT (0)
  38
  39 #define ERDBOFF (0x20)
  40 #define ERDBOFF_ERDBOFF_MASK (0xFFFFFFFF)
  41 #define ERDBOFF_ERDBOFF_SHIFT (0)
  42
  43 #define BHIOFF (0x28)
  44 #define BHIOFF_BHIOFF_MASK (0xFFFFFFFF)
  45 #define BHIOFF_BHIOFF_SHIFT (0)
  46
  47 #define BHIEOFF (0x2C)
  48 #define BHIEOFF_BHIEOFF_MASK (0xFFFFFFFF)
  49 #define BHIEOFF_BHIEOFF_SHIFT (0)
  50
  51 #define DEBUGOFF (0x30)
  52 #define DEBUGOFF_DEBUGOFF_MASK (0xFFFFFFFF)
  53 #define DEBUGOFF_DEBUGOFF_SHIFT (0)
  54
  55 #define MHICTRL (0x38)
  56 #define MHICTRL_MHISTATE_MASK (0x0000FF00)
  57 #define MHICTRL_MHISTATE_SHIFT (8)
  58 #define MHICTRL_RESET_MASK (0x2)
  59 #define MHICTRL_RESET_SHIFT (1)
  60
  61 #define MHISTATUS (0x48)
  62 #define MHISTATUS_MHISTATE_MASK (0x0000FF00)
  63 #define MHISTATUS_MHISTATE_SHIFT (8)
  64 #define MHISTATUS_SYSERR_MASK (0x4)
  65 #define MHISTATUS_SYSERR_SHIFT (2)
  66 #define MHISTATUS_READY_MASK (0x1)
  67 #define MHISTATUS_READY_SHIFT (0)
  68
  69 #define CCABAP_LOWER (0x58)
  70 #define CCABAP_LOWER_CCABAP_LOWER_MASK (0xFFFFFFFF)
  71 #define CCABAP_LOWER_CCABAP_LOWER_SHIFT (0)
  72
  73 #define CCABAP_HIGHER (0x5C)
  74 #define CCABAP_HIGHER_CCABAP_HIGHER_MASK (0xFFFFFFFF)
  75 #define CCABAP_HIGHER_CCABAP_HIGHER_SHIFT (0)
  76
  77 #define ECABAP_LOWER (0x60)
  78 #define ECABAP_LOWER_ECABAP_LOWER_MASK (0xFFFFFFFF)
  79 #define ECABAP_LOWER_ECABAP_LOWER_SHIFT (0)
  80
  81 #define ECABAP_HIGHER (0x64)
  82 #define ECABAP_HIGHER_ECABAP_HIGHER_MASK (0xFFFFFFFF)
  83 #define ECABAP_HIGHER_ECABAP_HIGHER_SHIFT (0)
  84
  85 #define CRCBAP_LOWER (0x68)
  86 #define CRCBAP_LOWER_CRCBAP_LOWER_MASK (0xFFFFFFFF)
  87 #define CRCBAP_LOWER_CRCBAP_LOWER_SHIFT (0)
  88
  89 #define CRCBAP_HIGHER (0x6C)
  90 #define CRCBAP_HIGHER_CRCBAP_HIGHER_MASK (0xFFFFFFFF)
  91 #define CRCBAP_HIGHER_CRCBAP_HIGHER_SHIFT (0)
  92
  93 #define CRDB_LOWER (0x70)
  94 #define CRDB_LOWER_CRDB_LOWER_MASK (0xFFFFFFFF)
  95 #define CRDB_LOWER_CRDB_LOWER_SHIFT (0)
  96
  97 #define CRDB_HIGHER (0x74)
  98 #define CRDB_HIGHER_CRDB_HIGHER_MASK (0xFFFFFFFF)
  99 #define CRDB_HIGHER_CRDB_HIGHER_SHIFT (0)
 100
 101 #define MHICTRLBASE_LOWER (0x80)
 102 #define MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_MASK (0xFFFFFFFF)
 103 #define MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_SHIFT (0)
 104
 105 #define MHICTRLBASE_HIGHER (0x84)
 106 #define MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_MASK (0xFFFFFFFF)
 107 #define MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_SHIFT (0)
 108
 109 #define MHICTRLLIMIT_LOWER (0x88)
 110 #define MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_MASK (0xFFFFFFFF)
 111 #define MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_SHIFT (0)
 112
 113 #define MHICTRLLIMIT_HIGHER (0x8C)
 114 #define MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_MASK (0xFFFFFFFF)
 115 #define MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_SHIFT (0)
 116
 117 #define MHIDATABASE_LOWER (0x98)
 118 #define MHIDATABASE_LOWER_MHIDATABASE_LOWER_MASK (0xFFFFFFFF)
 119 #define MHIDATABASE_LOWER_MHIDATABASE_LOWER_SHIFT (0)
 120
 121 #define MHIDATABASE_HIGHER (0x9C)
 122 #define MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_MASK (0xFFFFFFFF)
 123 #define MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_SHIFT (0)
 124
 125 #define MHIDATALIMIT_LOWER (0xA0)
 126 #define MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_MASK (0xFFFFFFFF)
 127 #define MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_SHIFT (0)
 128
 129 #define MHIDATALIMIT_HIGHER (0xA4)
 130 #define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_MASK (0xFFFFFFFF)
 131 #define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_SHIFT (0)
 132
 133 /* Host request register */
 134 #define MHI_SOC_RESET_REQ_OFFSET (0xB0)
 135 #define MHI_SOC_RESET_REQ BIT(0)
 136
 137 /* MHI BHI offfsets */
 138 #define BHI_BHIVERSION_MINOR (0x00)
 139 #define BHI_BHIVERSION_MAJOR (0x04)
 140 #define BHI_IMGADDR_LOW (0x08)
 141 #define BHI_IMGADDR_HIGH (0x0C)
 142 #define BHI_IMGSIZE (0x10)
 143 #define BHI_RSVD1 (0x14)
 144 #define BHI_IMGTXDB (0x18)
 145 #define BHI_TXDB_SEQNUM_BMSK (0x3FFFFFFF)
 146 #define BHI_TXDB_SEQNUM_SHFT (0)
 147 #define BHI_RSVD2 (0x1C)
 148 #define BHI_INTVEC (0x20)
 149 #define BHI_RSVD3 (0x24)
 150 #define BHI_EXECENV (0x28)
 151 #define BHI_STATUS (0x2C)
 152 #define BHI_ERRCODE (0x30)
 153 #define BHI_ERRDBG1 (0x34)
 154 #define BHI_ERRDBG2 (0x38)
 155 #define BHI_ERRDBG3 (0x3C)
 156 #define BHI_SERIALNU (0x40)
 157 #define BHI_SBLANTIROLLVER (0x44)
 158 #define BHI_NUMSEG (0x48)
 159 #define BHI_MSMHWID(n) (0x4C + (0x4 * n))
 160 #define BHI_OEMPKHASH(n) (0x64 + (0x4 * n))
 161 #define BHI_RSVD5 (0xC4)
 162 #define BHI_STATUS_MASK (0xC0000000)
 163 #define BHI_STATUS_SHIFT (30)
 164 #define BHI_STATUS_ERROR (3)
 165 #define BHI_STATUS_SUCCESS (2)
 166 #define BHI_STATUS_RESET (0)
 167
 168 /* MHI BHIE offsets */
 169 #define BHIE_MSMSOCID_OFFS (0x0000)
 170 #define BHIE_TXVECADDR_LOW_OFFS (0x002C)
 171 #define BHIE_TXVECADDR_HIGH_OFFS (0x0030)
 172 #define BHIE_TXVECSIZE_OFFS (0x0034)
 173 #define BHIE_TXVECDB_OFFS (0x003C)
 174 #define BHIE_TXVECDB_SEQNUM_BMSK (0x3FFFFFFF)
 175 #define BHIE_TXVECDB_SEQNUM_SHFT (0)
 176 #define BHIE_TXVECSTATUS_OFFS (0x0044)
 177 #define BHIE_TXVECSTATUS_SEQNUM_BMSK (0x3FFFFFFF)
 178 #define BHIE_TXVECSTATUS_SEQNUM_SHFT (0)
 179 #define BHIE_TXVECSTATUS_STATUS_BMSK (0xC0000000)
 180 #define BHIE_TXVECSTATUS_STATUS_SHFT (30)
 181 #define BHIE_TXVECSTATUS_STATUS_RESET (0x00)
 182 #define BHIE_TXVECSTATUS_STATUS_XFER_COMPL (0x02)
 183 #define BHIE_TXVECSTATUS_STATUS_ERROR (0x03)
 184 #define BHIE_RXVECADDR_LOW_OFFS (0x0060)
 185 #define BHIE_RXVECADDR_HIGH_OFFS (0x0064)
 186 #define BHIE_RXVECSIZE_OFFS (0x0068)
 187 #define BHIE_RXVECDB_OFFS (0x0070)
 188 #define BHIE_RXVECDB_SEQNUM_BMSK (0x3FFFFFFF)
 189 #define BHIE_RXVECDB_SEQNUM_SHFT (0)
 190 #define BHIE_RXVECSTATUS_OFFS (0x0078)
 191 #define BHIE_RXVECSTATUS_SEQNUM_BMSK (0x3FFFFFFF)
 192 #define BHIE_RXVECSTATUS_SEQNUM_SHFT (0)
 193 #define BHIE_RXVECSTATUS_STATUS_BMSK (0xC0000000)
 194 #define BHIE_RXVECSTATUS_STATUS_SHFT (30)
 195 #define BHIE_RXVECSTATUS_STATUS_RESET (0x00)
 196 #define BHIE_RXVECSTATUS_STATUS_XFER_COMPL (0x02)
 197 #define BHIE_RXVECSTATUS_STATUS_ERROR (0x03)
 198
 199 #define SOC_HW_VERSION_OFFS (0x224)
 200 #define SOC_HW_VERSION_FAM_NUM_BMSK (0xF0000000)
 201 #define SOC_HW_VERSION_FAM_NUM_SHFT (28)
 202 #define SOC_HW_VERSION_DEV_NUM_BMSK (0x0FFF0000)
 203 #define SOC_HW_VERSION_DEV_NUM_SHFT (16)
 204 #define SOC_HW_VERSION_MAJOR_VER_BMSK (0x0000FF00)
 205 #define SOC_HW_VERSION_MAJOR_VER_SHFT (8)
 206 #define SOC_HW_VERSION_MINOR_VER_BMSK (0x000000FF)
 207 #define SOC_HW_VERSION_MINOR_VER_SHFT (0)
 208
 209 #define EV_CTX_RESERVED_MASK GENMASK(7, 0)
 210 #define EV_CTX_INTMODC_MASK GENMASK(15, 8)
 211 #define EV_CTX_INTMODC_SHIFT 8
 212 #define EV_CTX_INTMODT_MASK GENMASK(31, 16)
 213 #define EV_CTX_INTMODT_SHIFT 16
 214 struct mhi_event_ctxt {
 215         __u32 intmod;
 216         __u32 ertype;
 217         __u32 msivec;
 218
 219         __u64 rbase __packed __aligned(4);
 220         __u64 rlen __packed __aligned(4);
 221         __u64 rp __packed __aligned(4);
 222         __u64 wp __packed __aligned(4);
 223 };
 224
 225 #define CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
 226 #define CHAN_CTX_CHSTATE_SHIFT 0
 227 #define CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
 228 #define CHAN_CTX_BRSTMODE_SHIFT 8
 229 #define CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
 230 #define CHAN_CTX_POLLCFG_SHIFT 10
 231 #define CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
 232 struct mhi_chan_ctxt {
 233         __u32 chcfg;
 234         __u32 chtype;
 235         __u32 erindex;
 236
 237         __u64 rbase __packed __aligned(4);
 238         __u64 rlen __packed __aligned(4);
 239         __u64 rp __packed __aligned(4);
 240         __u64 wp __packed __aligned(4);
 241 };
 242
 243 struct mhi_cmd_ctxt {
 244         __u32 reserved0;
 245         __u32 reserved1;
 246         __u32 reserved2;
 247
 248         __u64 rbase __packed __aligned(4);
 249         __u64 rlen __packed __aligned(4);
 250         __u64 rp __packed __aligned(4);
 251         __u64 wp __packed __aligned(4);
 252 };
 253
 254 struct mhi_ctxt {
 255         struct mhi_event_ctxt *er_ctxt;
 256         struct mhi_chan_ctxt *chan_ctxt;
 257         struct mhi_cmd_ctxt *cmd_ctxt;
 258         dma_addr_t er_ctxt_addr;
 259         dma_addr_t chan_ctxt_addr;
 260         dma_addr_t cmd_ctxt_addr;
 261 };
 262
 263 struct mhi_tre {
 264         u64 ptr;
 265         u32 dword[2];
 266 };
 267
 268 struct bhi_vec_entry {
 269         u64 dma_addr;
 270         u64 size;
 271 };
 272
 273 enum mhi_cmd_type {
 274         MHI_CMD_NOP = 1,
 275         MHI_CMD_RESET_CHAN = 16,
 276         MHI_CMD_STOP_CHAN = 17,
 277         MHI_CMD_START_CHAN = 18,
 278 };
 279
 280 /* No operation command */
 281 #define MHI_TRE_CMD_NOOP_PTR (0)
 282 #define MHI_TRE_CMD_NOOP_DWORD0 (0)
 283 #define MHI_TRE_CMD_NOOP_DWORD1 (MHI_CMD_NOP << 16)
 284
 285 /* Channel reset command */
 286 #define MHI_TRE_CMD_RESET_PTR (0)
 287 #define MHI_TRE_CMD_RESET_DWORD0 (0)
 288 #define MHI_TRE_CMD_RESET_DWORD1(chid) ((chid << 24) | \
 289                                         (MHI_CMD_RESET_CHAN << 16))
 290
 291 /* Channel stop command */
 292 #define MHI_TRE_CMD_STOP_PTR (0)
 293 #define MHI_TRE_CMD_STOP_DWORD0 (0)
 294 #define MHI_TRE_CMD_STOP_DWORD1(chid) ((chid << 24) | \
 295                                        (MHI_CMD_STOP_CHAN << 16))
 296
 297 /* Channel start command */
 298 #define MHI_TRE_CMD_START_PTR (0)
 299 #define MHI_TRE_CMD_START_DWORD0 (0)
 300 #define MHI_TRE_CMD_START_DWORD1(chid) ((chid << 24) | \
 301                                         (MHI_CMD_START_CHAN << 16))
 302
 303 #define MHI_TRE_GET_CMD_CHID(tre) (((tre)->dword[1] >> 24) & 0xFF)
 304 #define MHI_TRE_GET_CMD_TYPE(tre) (((tre)->dword[1] >> 16) & 0xFF)
 305
 306 /* Event descriptor macros */
 307 #define MHI_TRE_EV_PTR(ptr) (ptr)
 308 #define MHI_TRE_EV_DWORD0(code, len) ((code << 24) | len)
 309 #define MHI_TRE_EV_DWORD1(chid, type) ((chid << 24) | (type << 16))
 310 #define MHI_TRE_GET_EV_PTR(tre) ((tre)->ptr)
 311 #define MHI_TRE_GET_EV_CODE(tre) (((tre)->dword[0] >> 24) & 0xFF)
 312 #define MHI_TRE_GET_EV_LEN(tre) ((tre)->dword[0] & 0xFFFF)
 313 #define MHI_TRE_GET_EV_CHID(tre) (((tre)->dword[1] >> 24) & 0xFF)
 314 #define MHI_TRE_GET_EV_TYPE(tre) (((tre)->dword[1] >> 16) & 0xFF)
 315 #define MHI_TRE_GET_EV_STATE(tre) (((tre)->dword[0] >> 24) & 0xFF)
 316 #define MHI_TRE_GET_EV_EXECENV(tre) (((tre)->dword[0] >> 24) & 0xFF)
 317 #define MHI_TRE_GET_EV_SEQ(tre) ((tre)->dword[0])
 318 #define MHI_TRE_GET_EV_TIME(tre) ((tre)->ptr)
 319 #define MHI_TRE_GET_EV_COOKIE(tre) lower_32_bits((tre)->ptr)
 320 #define MHI_TRE_GET_EV_VEID(tre) (((tre)->dword[0] >> 16) & 0xFF)
 321 #define MHI_TRE_GET_EV_LINKSPEED(tre) (((tre)->dword[1] >> 24) & 0xFF)
 322 #define MHI_TRE_GET_EV_LINKWIDTH(tre) ((tre)->dword[0] & 0xFF)
 323
 324 /* Transfer descriptor macros */
 325 #define MHI_TRE_DATA_PTR(ptr) (ptr)
 326 #define MHI_TRE_DATA_DWORD0(len) (len & MHI_MAX_MTU)
 327 #define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) ((2 << 16) | (bei << 10) \
 328         | (ieot << 9) | (ieob << 8) | chain)
 329
 330 /* RSC transfer descriptor macros */
 331 #define MHI_RSCTRE_DATA_PTR(ptr, len) (((u64)len << 48) | ptr)
 332 #define MHI_RSCTRE_DATA_DWORD0(cookie) (cookie)
 333 #define MHI_RSCTRE_DATA_DWORD1 (MHI_PKT_TYPE_COALESCING << 16)
 334
 335 enum mhi_pkt_type {
 336         MHI_PKT_TYPE_INVALID = 0x0,
 337         MHI_PKT_TYPE_NOOP_CMD = 0x1,
 338         MHI_PKT_TYPE_TRANSFER = 0x2,
 339         MHI_PKT_TYPE_COALESCING = 0x8,
 340         MHI_PKT_TYPE_RESET_CHAN_CMD = 0x10,
 341         MHI_PKT_TYPE_STOP_CHAN_CMD = 0x11,
 342         MHI_PKT_TYPE_START_CHAN_CMD = 0x12,
 343         MHI_PKT_TYPE_STATE_CHANGE_EVENT = 0x20,
 344         MHI_PKT_TYPE_CMD_COMPLETION_EVENT = 0x21,
 345         MHI_PKT_TYPE_TX_EVENT = 0x22,
 346         MHI_PKT_TYPE_RSC_TX_EVENT = 0x28,
 347         MHI_PKT_TYPE_EE_EVENT = 0x40,
 348         MHI_PKT_TYPE_TSYNC_EVENT = 0x48,
 349         MHI_PKT_TYPE_BW_REQ_EVENT = 0x50,
 350         MHI_PKT_TYPE_STALE_EVENT, /* internal event */
 351 };
 352
 353 /* MHI transfer completion events */
 354 enum mhi_ev_ccs {
 355         MHI_EV_CC_INVALID = 0x0,
 356         MHI_EV_CC_SUCCESS = 0x1,
 357         MHI_EV_CC_EOT = 0x2, /* End of transfer event */
 358         MHI_EV_CC_OVERFLOW = 0x3,
 359         MHI_EV_CC_EOB = 0x4, /* End of block event */
 360         MHI_EV_CC_OOB = 0x5, /* Out of block event */
 361         MHI_EV_CC_DB_MODE = 0x6,
 362         MHI_EV_CC_UNDEFINED_ERR = 0x10,
 363         MHI_EV_CC_BAD_TRE = 0x11,
 364 };
 365
 366 enum mhi_ch_state {
 367         MHI_CH_STATE_DISABLED = 0x0,
 368         MHI_CH_STATE_ENABLED = 0x1,
 369         MHI_CH_STATE_RUNNING = 0x2,
 370         MHI_CH_STATE_SUSPENDED = 0x3,
 371         MHI_CH_STATE_STOP = 0x4,
 372         MHI_CH_STATE_ERROR = 0x5,
 373 };
 374
 375 #define MHI_INVALID_BRSTMODE(mode) (mode != MHI_DB_BRST_DISABLE && \
 376                                     mode != MHI_DB_BRST_ENABLE)
 377
 378 extern const char * const mhi_ee_str[MHI_EE_MAX];
 379 #define TO_MHI_EXEC_STR(ee) (((ee) >= MHI_EE_MAX) ? \
 380                              "INVALID_EE" : mhi_ee_str[ee])
 381
 382 #define MHI_IN_PBL(ee) (ee == MHI_EE_PBL || ee == MHI_EE_PTHRU || \
 383                         ee == MHI_EE_EDL)
 384
 385 #define MHI_IN_MISSION_MODE(ee) (ee == MHI_EE_AMSS || ee == MHI_EE_WFW)
 386
 387 enum dev_st_transition {
 388         DEV_ST_TRANSITION_PBL,
 389         DEV_ST_TRANSITION_READY,
 390         DEV_ST_TRANSITION_SBL,
 391         DEV_ST_TRANSITION_MISSION_MODE,
 392         DEV_ST_TRANSITION_MAX,
 393 };
 394
 395 extern const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX];
 396 #define TO_DEV_STATE_TRANS_STR(state) (((state) >= DEV_ST_TRANSITION_MAX) ? \
 397                                 "INVALID_STATE" : dev_state_tran_str[state])
 398
 399 extern const char * const mhi_state_str[MHI_STATE_MAX];
 400 #define TO_MHI_STATE_STR(state) ((state >= MHI_STATE_MAX || \
 401                                   !mhi_state_str[state]) ? \
 402                                 "INVALID_STATE" : mhi_state_str[state])
 403
 404 /* internal power states */
 405 enum mhi_pm_state {
 406         MHI_PM_STATE_DISABLE,
 407         MHI_PM_STATE_POR,
 408         MHI_PM_STATE_M0,
 409         MHI_PM_STATE_M2,
 410         MHI_PM_STATE_M3_ENTER,
 411         MHI_PM_STATE_M3,
 412         MHI_PM_STATE_M3_EXIT,
 413         MHI_PM_STATE_FW_DL_ERR,
 414         MHI_PM_STATE_SYS_ERR_DETECT,
 415         MHI_PM_STATE_SYS_ERR_PROCESS,
 416         MHI_PM_STATE_SHUTDOWN_PROCESS,
 417         MHI_PM_STATE_LD_ERR_FATAL_DETECT,
 418         MHI_PM_STATE_MAX
 419 };
 420
 421 #define MHI_PM_DISABLE                  BIT(0)
 422 #define MHI_PM_POR                      BIT(1)
 423 #define MHI_PM_M0                       BIT(2)
 424 #define MHI_PM_M2                       BIT(3)
 425 #define MHI_PM_M3_ENTER                 BIT(4)
 426 #define MHI_PM_M3                       BIT(5)
 427 #define MHI_PM_M3_EXIT                  BIT(6)
 428 /* firmware download failure state */
 429 #define MHI_PM_FW_DL_ERR                BIT(7)
 430 #define MHI_PM_SYS_ERR_DETECT           BIT(8)
 431 #define MHI_PM_SYS_ERR_PROCESS          BIT(9)
 432 #define MHI_PM_SHUTDOWN_PROCESS         BIT(10)
 433 /* link not accessible */
 434 #define MHI_PM_LD_ERR_FATAL_DETECT      BIT(11)
 435
 436 #define MHI_REG_ACCESS_VALID(pm_state) ((pm_state & (MHI_PM_POR | MHI_PM_M0 | \
 437                 MHI_PM_M2 | MHI_PM_M3_ENTER | MHI_PM_M3_EXIT | \
 438                 MHI_PM_SYS_ERR_DETECT | MHI_PM_SYS_ERR_PROCESS | \
 439                 MHI_PM_SHUTDOWN_PROCESS | MHI_PM_FW_DL_ERR)))
 440 #define MHI_PM_IN_ERROR_STATE(pm_state) (pm_state >= MHI_PM_FW_DL_ERR)
 441 #define MHI_PM_IN_FATAL_STATE(pm_state) (pm_state == MHI_PM_LD_ERR_FATAL_DETECT)
 442 #define MHI_DB_ACCESS_VALID(mhi_cntrl) (mhi_cntrl->pm_state & \
 443                                         mhi_cntrl->db_access)
 444 #define MHI_WAKE_DB_CLEAR_VALID(pm_state) (pm_state & (MHI_PM_M0 | \
 445                                                 MHI_PM_M2 | MHI_PM_M3_EXIT))
 446 #define MHI_WAKE_DB_SET_VALID(pm_state) (pm_state & MHI_PM_M2)
 447 #define MHI_WAKE_DB_FORCE_SET_VALID(pm_state) MHI_WAKE_DB_CLEAR_VALID(pm_state)
 448 #define MHI_EVENT_ACCESS_INVALID(pm_state) (pm_state == MHI_PM_DISABLE || \
 449                                             MHI_PM_IN_ERROR_STATE(pm_state))
 450 #define MHI_PM_IN_SUSPEND_STATE(pm_state) (pm_state & \
 451                                            (MHI_PM_M3_ENTER | MHI_PM_M3))
 452
 453 #define NR_OF_CMD_RINGS                 1
 454 #define CMD_EL_PER_RING                 128
 455 #define PRIMARY_CMD_RING                0
 456 #define MHI_DEV_WAKE_DB                 127
 457 #define MHI_MAX_MTU                     0xffff
 458
 459 enum mhi_er_type {
 460         MHI_ER_TYPE_INVALID = 0x0,
 461         MHI_ER_TYPE_VALID = 0x1,
 462 };
 463
 464 struct db_cfg {
 465         bool reset_req;
 466         bool db_mode;
 467         u32 pollcfg;
 468         enum mhi_db_brst_mode brstmode;
 469         dma_addr_t db_val;
 470         void (*process_db)(struct mhi_controller *mhi_cntrl,
 471                            struct db_cfg *db_cfg, void __iomem *io_addr,
 472                            dma_addr_t db_val);
 473 };
 474
 475 struct mhi_pm_transitions {
 476         enum mhi_pm_state from_state;
 477         u32 to_states;
 478 };
 479
 480 struct state_transition {
 481         struct list_head node;
 482         enum dev_st_transition state;
 483 };
 484
 485 struct mhi_ring {
 486         dma_addr_t dma_handle;
 487         dma_addr_t iommu_base;
 488         u64 *ctxt_wp; /* point to ctxt wp */
 489         void *pre_aligned;
 490         void *base;
 491         void *rp;
 492         void *wp;
 493         size_t el_size;
 494         size_t len;
 495         size_t elements;
 496         size_t alloc_size;
 497         void __iomem *db_addr;
 498 };
 499
 500 struct mhi_cmd {
 501         struct mhi_ring ring;
 502         spinlock_t lock;
 503 };
 504
 505 struct mhi_buf_info {
 506         void *v_addr;
 507         void *bb_addr;
 508         void *wp;
 509         void *cb_buf;
 510         dma_addr_t p_addr;
 511         size_t len;
 512         enum dma_data_direction dir;
 513         bool used; /* Indicates whether the buffer is used or not */
 514         bool pre_mapped; /* Already pre-mapped by client */
 515 };
 516
 517 struct mhi_event {
 518         struct mhi_controller *mhi_cntrl;
 519         struct mhi_chan *mhi_chan; /* dedicated to channel */
 520         u32 er_index;
 521         u32 intmod;
 522         u32 irq;
 523         int chan; /* this event ring is dedicated to a channel (optional) */
 524         u32 priority;
 525         enum mhi_er_data_type data_type;
 526         struct mhi_ring ring;
 527         struct db_cfg db_cfg;
 528         struct tasklet_struct task;
 529         spinlock_t lock;
 530         int (*process_event)(struct mhi_controller *mhi_cntrl,
 531                              struct mhi_event *mhi_event,
 532                              u32 event_quota);
 533         bool hw_ring;
 534         bool cl_manage;
 535         bool offload_ev; /* managed by a device driver */
 536 };
 537
 538 struct mhi_chan {
 539         const char *name;
 540         /*
 541          * Important: When consuming, increment tre_ring first and when
 542          * releasing, decrement buf_ring first. If tre_ring has space, buf_ring
 543          * is guranteed to have space so we do not need to check both rings.
 544          */
 545         struct mhi_ring buf_ring;
 546         struct mhi_ring tre_ring;
 547         u32 chan;
 548         u32 er_index;
 549         u32 intmod;
 550         enum mhi_ch_type type;
 551         enum dma_data_direction dir;
 552         struct db_cfg db_cfg;
 553         enum mhi_ch_ee_mask ee_mask;
 554         enum mhi_ch_state ch_state;
 555         enum mhi_ev_ccs ccs;
 556         struct mhi_device *mhi_dev;
 557         void (*xfer_cb)(struct mhi_device *mhi_dev, struct mhi_result *result);
 558         struct mutex mutex;
 559         struct completion completion;
 560         rwlock_t lock;
 561         struct list_head node;
 562         bool lpm_notify;
 563         bool configured;
 564         bool offload_ch;
 565         bool pre_alloc;
 566         bool auto_start;
 567         bool wake_capable;
 568 };
 569
 570 /* Default MHI timeout */
 571 #define MHI_TIMEOUT_MS (1000)
 572
 573 struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl);
 574
 575 int mhi_destroy_device(struct device *dev, void *data);
 576 void mhi_create_devices(struct mhi_controller *mhi_cntrl);
 577
 578 int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl,
 579                          struct image_info **image_info, size_t alloc_size);
 580 void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl,
 581                          struct image_info *image_info);
 582
 583 /* Power management APIs */
 584 enum mhi_pm_state __must_check mhi_tryset_pm_state(
 585                                         struct mhi_controller *mhi_cntrl,
 586                                         enum mhi_pm_state state);
 587 const char *to_mhi_pm_state_str(enum mhi_pm_state state);
 588 enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl);
 589 int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl,
 590                                enum dev_st_transition state);
 591 void mhi_pm_st_worker(struct work_struct *work);
 592 void mhi_pm_sys_err_worker(struct work_struct *work);
 593 void mhi_fw_load_worker(struct work_struct *work);
 594 int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl);
 595 void mhi_ctrl_ev_task(unsigned long data);
 596 int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl);
 597 void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl);
 598 int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl);
 599 int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl);
 600 int mhi_send_cmd(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan,
 601                  enum mhi_cmd_type cmd);
 602
 603 /* Register access methods */
 604 void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, struct db_cfg *db_cfg,
 605                      void __iomem *db_addr, dma_addr_t db_val);
 606 void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl,
 607                              struct db_cfg *db_mode, void __iomem *db_addr,
 608                              dma_addr_t db_val);
 609 int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl,
 610                               void __iomem *base, u32 offset, u32 *out);
 611 int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl,
 612                                     void __iomem *base, u32 offset, u32 mask,
 613                                     u32 shift, u32 *out);
 614 void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
 615                    u32 offset, u32 val);
 616 void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base,
 617                          u32 offset, u32 mask, u32 shift, u32 val);
 618 void mhi_ring_er_db(struct mhi_event *mhi_event);
 619 void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr,
 620                   dma_addr_t db_val);
 621 void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd);
 622 void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
 623                       struct mhi_chan *mhi_chan);
 624
 625 /* Initialization methods */
 626 int mhi_init_mmio(struct mhi_controller *mhi_cntrl);
 627 int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl);
 628 void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl);
 629 int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl);
 630 void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl);
 631 void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl,
 632                       struct image_info *img_info);
 633 int mhi_prepare_channel(struct mhi_controller *mhi_cntrl,
 634                         struct mhi_chan *mhi_chan);
 635 int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,
 636                        struct mhi_chan *mhi_chan);
 637 void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,
 638                           struct mhi_chan *mhi_chan);
 639 void mhi_reset_chan(struct mhi_controller *mhi_cntrl,
 640                     struct mhi_chan *mhi_chan);
 641
 642 /* Memory allocation methods */
 643 static inline void *mhi_alloc_coherent(struct mhi_controller *mhi_cntrl,
 644                                        size_t size,
 645                                        dma_addr_t *dma_handle,
 646                                        gfp_t gfp)
 647 {
 648         void *buf = dma_alloc_coherent(mhi_cntrl->cntrl_dev, size, dma_handle,
 649                                        gfp);
 650
 651         return buf;
 652 }
 653
 654 static inline void mhi_free_coherent(struct mhi_controller *mhi_cntrl,
 655                                      size_t size,
 656                                      void *vaddr,
 657                                      dma_addr_t dma_handle)
 658 {
 659         dma_free_coherent(mhi_cntrl->cntrl_dev, size, vaddr, dma_handle);
 660 }
 661
 662 /* Event processing methods */
 663 void mhi_ctrl_ev_task(unsigned long data);
 664 void mhi_ev_task(unsigned long data);
 665 int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl,
 666                                 struct mhi_event *mhi_event, u32 event_quota);
 667 int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl,
 668                              struct mhi_event *mhi_event, u32 event_quota);
 669
 670 /* ISR handlers */
 671 irqreturn_t mhi_irq_handler(int irq_number, void *dev);
 672 irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev);
 673 irqreturn_t mhi_intvec_handler(int irq_number, void *dev);
 674
 675 int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan,
 676                 void *buf, void *cb, size_t buf_len, enum mhi_flags flags);
 677
 678 int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl,
 679                          struct mhi_buf_info *buf_info);
 680 int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl,
 681                           struct mhi_buf_info *buf_info);
 682 void mhi_unmap_single_no_bb(struct mhi_controller *mhi_cntrl,
 683                             struct mhi_buf_info *buf_info);
 684 void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl,
 685                              struct mhi_buf_info *buf_info);
 686
 687 #endif /* _MHI_INT_H */